CN115866076A - Asynchronous BiSS-C protocol decoding method based on FPGA - Google Patents

Abstract

The asynchronous BiSS-C protocol decoding method based on the FPGA comprises a baud rate clock module, a BiSS-C data decoding module and a CRC (cyclic redundancy check) module; sampling encoder position data transmitted by an SLO line by using the baud rate clock module; decoding encoder position data transmitted by an SLO line by using a BiSS-C data decoding module based on a BiSS-C data protocol to obtain decoded data of the encoder position data; and the CRC check module is used for moving the decoded data of the encoder position data into a register to obtain a CRC check code of the encoder position data after detecting the encoder position data decoding completion mark, comparing the CRC code of the encoder position data with the CRC check code, and obtaining the encoder position data if the CRC code of the encoder position data is consistent with the CRC check code of the encoder position data. The method and the device solve the problem that the position information of the encoder transmitted by the BiSS-C protocol is analyzed by using the FPGA under an asynchronous clock.

Description

Asynchronous BiSS-C protocol decoding method based on FPGA

Technical Field

The invention belongs to the technical field of data acquisition of grating encoders, and particularly relates to an asynchronous BiSS-C protocol decoding method based on an FPGA.

Background

The BISS communication protocol is a full-duplex synchronous serial bus communication protocol and is specially designed for meeting the requirements of real-time, bidirectional and high-speed sensor communication. The current version of the BISS communication protocol is BISS-C, and in servo systems, the BISS-C protocol is mostly used by encoders. In the BISS-C protocol, two communication parties are respectively a master station and a slave station, an encoder is used as the slave station, a servo driver or a motion controller is used as the master station, and the master station reads position information acquired by the encoder through the BISS-C protocol. The BISS-C protocol is divided into two communication modes of a sensor mode and a register mode, wherein the master station can only read sensor information sent by the slave station in the sensor mode, and the register mode can acquire all open information of the slave station and set parameters of the slave station.

The existing processing technology related to the BiSS-C protocol in the FPGA is performed based on a synchronous clock, that is, a main signal MA in the BiSS-C protocol is used as an operation clock of the FPGA. In some application occasions, the main signal MA signal is not transmitted to the encoder by the rotary control board of the encoder without passing through the FPGA, in this case, the FPGA is required to analyze the position data transmitted by the BiSS-C under an asynchronous clock, and no relevant literature is provided in China for explaining how to process the situation. In addition, for the FPGA software implementation of BiSS-C protocol decoding, detailed data are not disclosed in China.

Disclosure of Invention

The invention overcomes one of the defects of the prior art, and provides an asynchronous BiSS-C protocol decoding method based on an FPGA (field programmable gate array), so as to solve the problem of analyzing the position information of a coder transmitted by the BiSS-C protocol by using the FPGA under an asynchronous clock.

According to one aspect of the disclosure, the invention provides an asynchronous BiSS-C protocol decoding method based on an FPGA, wherein the FPGA comprises a baud rate clock module, a BiSS-C data decoding module and a CRC (cyclic redundancy check) module, and the method comprises the following steps:

sampling encoder position data transmitted by an SLO line by using the Baud rate clock module;

decoding encoder position data transmitted by an SLO line by using a BiSS-C data decoding module based on a BiSS-C data protocol to obtain decoded data of the encoder position data;

and the CRC check module is used for moving the decoded data of the encoder position data into a register to obtain a CRC check code of the encoder position data after detecting the encoder position data decoding completion mark, comparing the CRC code of the encoder position data with the CRC check code, and obtaining the encoder position data if the CRC code of the encoder position data is consistent with the CRC check code of the encoder position data.

In one possible implementation manner, the sampling, by the baud rate clock module, encoder position data transmitted by an SLO line includes:

dividing the frequency of a system clock signal of the baud rate clock module to obtain a baud rate clock signal of the baud rate clock module;

and sampling the encoder position data transmitted by the SLO line based on the frequency of the baud rate clock signal of the baud rate clock module.

In one possible implementation manner, the decoding, by using the BiSS-C data decoding module, encoder position data transmitted by an SLO line based on the BiSS-C data protocol includes:

setting a state machine of the BiSS-C data decoding module based on a data frame format of a BiSS-C data protocol;

decoding encoder position data transmitted by an SLO line by using a state machine of the BiSS-C data decoding module;

wherein the state machine includes a WAIT state, an IDLE state, an ACK state, a START state, a ZERO state, and a DATA state.

In one possible implementation manner, the decoding, by using the state machine of the BiSS-C data decoding module, the encoder position data transmitted by the SLO line includes:

when a system reset signal is detected, the state machine enters a WAIT state, and when an input signal of the SLO line is 1, the state machine jumps to an IDLE state;

in an IDLE state, when an input signal of the SLO line is 0, the state machine jumps to an ACK state;

in the ACK state, when the input signal level of the SLO line is 1, the state machine jumps to the START state;

in a START state, when a START bit of the encoder position data frame is detected, the state machine transitions to a ZERO state;

in the ZERO state, when a "0" bit of an encoder position DATA frame is detected, the state machine jumps to the DATA state;

in the DATA state, encoder position DATA transmitted by an SLO line is received according to bits on the rising edge of a baud rate clock signal, and the encoder position DATA is moved into a shift register to be latched according to the sequence with the high bits in front, so that decoding DATA of the encoder position DATA is obtained.

In one possible implementation, in the ACK state, when the input signal level of the SLO line is 1, the state machine jumps to a START state; in a START state, when a START bit of the encoder position data frame is detected, the state machine transitions to a ZERO state; the method comprises the following steps:

wherein the START status comprises a START1 status and a START2 status;

in the ACK state, when the input signal level of the SLO line is 1, the state machine jumps to the state of START 1;

adding 1 to a baud rate clock counting signal baud _ counter on the rising edge of the baud rate clock signal, and sampling the input signal level of an SLO line to be used as a flag bit _ samp when the baud rate clock counting signal baud _ counter is 7;

in the case that the baud rate clock signal (baud _ pulse) is 1 and the baud rate clock count signal baud _ counter is greater than 8, when the flag bit _ samp is 1, the state machine jumps from the START1 state to the START2 state;

and adding 1 to the time count value cnt of the START2 state at the rising edge of the Baud rate clock signal, wherein when the level of the SLO line input signal is 0 and the time count value cnt of the START2 state is less than 20, the flag bit _ samp is the START bit of the encoder position data frame, and the state machine jumps to the ZERO state.

In one possible implementation, the "0" bit of the encoder position data frame includes:

in the ZERO state, adding 1 to the baud rate clock counting signal baud _ counter on the rising edge of the baud rate clock signal, and when the baud rate clock counting signal baud _ counter is greater than 8, and the flag bit _ samp is 0, taking the flag bit _ samp as the 0 bit of the encoder position data frame.

In one possible implementation, the bit-wise receiving, in the DATA state, encoder position DATA transmitted by the SLO line on a rising edge of the baud-rate clock signal includes:

in the DATA state, encoder position DATA transmitted by the SLO line is received in a bit mode on the rising edge of a baud rate clock signal, when one bit of encoder position DATA is received, a DATA DATA bit count value bit _ counter is added with 1, and the DATA DATA bit count value bit _ counter is circularly and incrementally increased from 0 to 33.

In one possible implementation, the encoder position data and the decoded data of the encoder position data include: 26 bits of encoder position data, 1 bit of error bits, 1 bit of warning bits, 6 bits of CRC code.

In a possible implementation manner, the CRC check module, after detecting the encoder position data decoding completion flag, moves the decoded data of the encoder position data into a register to obtain a CRC check code of the encoder position data, compares the CRC code of the encoder position data with the CRC check code, and if the two are consistent, obtains the encoder position data, including:

p1: when the encoder position data decoding completion flag is detected, initializing a data register, storing 26-bit encoder position data, a 1-bit error bit and a 1-bit warning bit of decoded data of the encoder position data into the data register, and supplementing the latter 6 bits of the data register with 0;

p2: shifting the data of the data register by one bit to the left, reading in new data, placing the new data into the lowest bit of the data register, and performing exclusive-or operation on the data in the data register and the generated polynomial when the shifted-out bit data is 1;

p3: repeating the step P2 until the 26-bit data bit is processed, wherein the content in the data register is CRC check code;

p4: and comparing the CRC code and the CRC check code of the encoder position data, and outputting to obtain the encoder position data if the CRC code and the CRC check code of the encoder position data are consistent and the error bit is 1.

In one possible implementation, the frequency of the baud rate clock signal of the baud rate clock module is 16 times that of the MA frequency of the BiSS-C protocol clock.

The asynchronous BiSS-C protocol decoding method based on the FPGA comprises a baud rate clock module, a BiSS-C data decoding module and a CRC (cyclic redundancy check) module; sampling encoder position data transmitted by an SLO line by using the baud rate clock module; based on a BiSS-C data protocol, decoding encoder position data transmitted by an SLO line by using the BiSS-C data decoding module to obtain decoded data of the encoder position data; and the CRC check module is used for moving the decoded data of the encoder position data into a register to obtain a CRC check code of the encoder position data after detecting the encoder position data decoding completion mark, comparing the CRC code of the encoder position data with the CRC check code, and obtaining the encoder position data if the CRC code of the encoder position data is consistent with the CRC check code of the encoder position data. The method solves the problem that the position information of the encoder transmitted by the BiSS-C protocol is analyzed by using the FPGA under an asynchronous clock.

Drawings

The accompanying drawings are included to provide a further understanding of the technology or prior art of the present application and are incorporated in and constitute a part of this specification. The drawings expressing the embodiments of the present application are used for explaining the technical solutions of the present application, and should not be construed as limiting the technical solutions of the present application.

FIG. 1 shows a block schematic diagram of an FPGA according to an embodiment of the present disclosure;

figure 2 illustrates a flow diagram of an FPGA-based asynchronous BiSS-C protocol decoding method according to an embodiment of the present disclosure;

figure 3 illustrates a skip module schematic of a state machine of a BiSS-C data decoding module according to an embodiment of the present disclosure;

FIG. 4 illustrates a ModelSim emulated state transition diagram, according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram illustrating simulation results of inputting 3 frames of correct encoder position data according to an embodiment of the present disclosure;

FIG. 6 is a diagram illustrating simulation results of inputting 1 frame of correct encoder position data and 2 frames of incorrect encoder position data according to an embodiment of the present disclosure.

Detailed Description

The following detailed description of the embodiments of the present invention will be provided with reference to the accompanying drawings and examples, so that how to apply the technical means to solve the technical problems and achieve the corresponding technical effects can be fully understood and implemented. The embodiments and the features of the embodiments can be combined without conflict, and the technical solutions formed are all within the scope of the present invention.

Additionally, the steps illustrated in the flow charts of the figures may be performed in a computer such as a set of computer-executable instructions. Also, while a logical order is shown in the flow diagrams, in some cases, the steps shown or described may be performed in an order different than here.

FIG. 1 shows a block schematic diagram of an FPGA according to an embodiment of the present disclosure.

As shown in fig. 1, the FPGA software includes a baud rate clock module, a BiSS-C data decoding module, and a CRC check module. Wherein, baud rate clock module totally 3 signal interface: a system clock signal clk, a system reset signal reset _ n, and a baud rate clock signal baud _ pulse. The BiSS-C data decoding module has 5 signal interfaces: the system clock signal clk, the system reset signal reset _ n, the baud rate clock signal baud _ pulse, the SLO line serial data rxd, and the decoded output data bissc _ in. The CRC check module has 4 signal interfaces: a system clock signal clk, a system reset signal reset _ n, decoded output data bissc _ in, and check output data bissc _ out.

Figure 2 illustrates a flow diagram of an FPGA-based asynchronous BiSS-C protocol decoding method according to an embodiment of the present disclosure; the method utilizes asynchronous decoding of the FPGA as shown in fig. 1, and as shown in fig. 2, the method may include:

step S1: and sampling encoder position data transmitted by an SLO line by using the Baud rate clock module.

Wherein the encoder position data and the decoded data of the encoder position data include: 26 bits of encoder position data, 1 bit of error bits, 1 bit of warning bits, 6 bits of CRC code.

The method comprises the steps of dividing a system clock signal clk of a baud rate clock module to obtain a baud rate clock signal number baud _ pulse of the baud rate clock module, and sampling encoder position data transmitted by an SLO line based on the frequency of the baud rate clock signal baud _ pulse of the baud rate clock module. The frequency of the baud rate clock signal number baud _ pulse of the baud rate clock module can be 16 times of the frequency of the BiSS-C protocol clock MA, and can be used for sampling 16 times of encoder position data transmitted by the SLO line. For example, the frequency of the system clock clk is 50MHz, the frequency of the BiSS-C protocol clock MA is 1MHz, and the frequency of the baud rate clock signal number baud _ pulse is 16MHz.

Step S2: and based on a BiSS-C data protocol, decoding the encoder position data transmitted by the SLO line by using the BiSS-C data decoding module to obtain the decoded data of the encoder position data.

The BiSS-C data decoding module comprises a state machine used for decoding the encoder position data transmitted by the SLO line. Setting a state machine of the BiSS-C data decoding module based on a data frame format of a BiSS-C data protocol, namely setting state skip by the state machine according to the data frame format of the BiSS-C protocol; and decoding the encoder position data transmitted by the SLO line by using a state machine of the BiSS-C data decoding module. The encoder position data may be serial data (SLO line transfer serial data).

In an example, decoding, with a state machine of the BiSS-C data decoding module, encoder position data transmitted by an SLO line may include:

when a system reset signal is detected, the state machine enters a WAIT state, and when an input signal of the SLO line is 1, the state machine jumps to an IDLE state;

in an IDLE state, when an input signal of the SLO line is 0, the state machine jumps to an ACK state;

in the ACK state, when the input signal level of the SLO line is 1, the state machine jumps to the START state;

in a START state, when a START bit of the encoder position data frame is detected, the state machine transitions to a ZERO state;

in the ZERO state, when a "0" bit of an encoder position DATA frame is detected, the state machine jumps to the DATA state;

in the DATA state, encoder position DATA transmitted by an SLO line is received according to bits on the rising edge of a baud rate clock signal, and the encoder position DATA is moved into a shift register to be latched according to the sequence with the high bits in front, so that decoding DATA of the encoder position DATA is obtained.

Fig. 3 illustrates a skip module schematic of a state machine of a BiSS-C data decoding module according to an embodiment of the present disclosure.

Specifically, as shown in FIG. 3, the state machine may include a WAIT state, an IDLE state, an ACK state, a START state, a ZERO state, a DATA state, a TIMEOUT state, and a FINISH state.

In the state machine of the BiSS-C data decoding module, the default state is the WAIT state, and when the system reset signal reset _ n is detected to be valid, the state machine enters the WAIT state. In the WAIT state, if the input signal level rxd of the SLO line is 1, the state machine state jumps to the IDLE state, otherwise, the state machine stays in the WAIT state; in the IDLE state, if the input signal level rxd of the SLO line is 0, the state machine jumps to the ACK state, otherwise, the state machine stays in the IDLE state; and after entering the ACK state, if the input signal rxd of the SLO line is 1, the state machine jumps to the START state, and otherwise, the state machine stays in the ACK state to wait.

Wherein the START state includes a START1 state and a START2 state; in the ACK state, when the input signal level of the SLO line is 1, the state machine jumps to the state of START 1.

And defining a baud rate clock count signal baud _ counter, adding 1 to the baud rate clock count signal baud _ counter on the rising edge of the baud rate clock signal, and sampling the input signal level of the SLO line as a flag bit _ samp when the baud rate clock count signal baud _ counter is 7. For example, the baud rate clock count signal baud _ counter cycles from 0 to 15, i.e., each baud rate clock count signal baud _ counter corresponds to one sample of encoder position data. The 7 th sample value is the middle value of the encoder position data, which can represent the level of this bit data. And defining a sampling intermediate value flag bit _ samp, and setting the flag bit _ samp to be 1 when the intermediate value of the serial data input by the SLO line is 1.

Under the condition that the baud rate clock signal (baud _ pulse) is 1 and the baud rate clock count signal baud _ counter is greater than 8, when the flag bit _ samp is 1, the state machine jumps from the START1 state to the START2 state, otherwise, the state jumps to WAIT;

defining a time count value cnt as a START2 state count value in a START2 state, adding 1 to the time count value cnt of the START2 state on a rising edge of a baud rate clock signal, indicating that the START2 state lasts for half of 1-bit data when an SLO line input signal level is 0 and the time count value cnt of the START2 state is less than 20, the sum of the durations of the START1 state and the START2 state equals a START bit transmission time, the flag bit _ samp is a START bit of an encoder position data frame, and the state machine jumps to a ZERO state; otherwise, the flag bit _ samp is invalid, and the state machine jumps to the WAIT state.

In the ZERO state, adding 1 to the baud rate clock count signal baud _ counter on the rising edge of the baud rate clock signal, and when the baud rate clock count signal baud _ counter is greater than 8, and the flag bit _ samp is 0, taking the flag bit _ samp as the 0 bit of the encoder position DATA frame, and jumping to the DATA state by the state machine.

In the DATA state, the DATA state requires 34 bits of DATA including 26 bits of position DATA, 1 bit Error bit, 1 bit Warn bit, and 6 bits of CRC bit of the encoder position DATA frame inputted from SLO.

In the DATA state, encoder position DATA transmitted by the SLO line is received in a bit mode on the rising edge of a baud rate clock signal, when the encoder position DATA of one bit is received, a count value bit _ counter is added to be 1, and the count value bit _ counter is circularly and incrementally increased from 0 to 33. For example, in the DATA state, the signal bit _ counter is defined as a DATA bit count, and the value of the DATA bit count value bit _ counter is incremented by 1 from 0 to 33 cycles every time one bit of DATA is received. The definition signal bit _ counter _ grt is the data bit count value bit _ counter count, and when the value of the data bit count value bit _ counter is greater than 33, the bit _ counter _ grt is set to 1, which indicates that 34 bits of valid data are received. And determining that the secondary state goes to the destination by judging whether the value of the signal bit _ counter _ grt is 1, if the value of the signal bit _ counter _ grt is 1, jumping to the WAIT state by the state machine, and if not, staying in the DATA state to continue receiving the DATA. In the DATA state, when the rising edge of the baud rate clock comes, the encoder position DATA transmitted by the SLO line sequentially enters the shift register in the order of the leading high bits, and the shift register stores the DATA by shifting left one by one. The bit width of the shift register is 34, and the shift register is used for storing 26 bits of position data of the encoder position data, 1 bit of error bits, 1 bit of warning bits and 6 bits of CRC check bits. In particular, the data in the shift register is latched before being output, resulting in decoded data of the encoder position data. After the shift register latches the data, the shift register latches a signal at a high level.

Through the above process, the decoded data of the encoder position data transmitted by the SLO line can be obtained and latched into the shift register, so that the CRC check module in step S3 can perform check comparison.

And step S3: and the CRC check module is used for moving the decoded data of the encoder position data into a register to obtain a CRC check code of the encoder position data after detecting the encoder position data decoding completion mark, comparing the CRC code of the encoder position data with the CRC check code, and obtaining the encoder position data if the CRC code of the encoder position data is consistent with the CRC check code of the encoder position data.

The method specifically comprises the following steps:

step P1: when the encoder position data decoding completion mark is detected, initializing a data register, storing 26 bits of encoder position data, 1 bit error bits and 1 bit warning bits of the decoded data of the encoder position data into the data register, and supplementing the last 6 bits of the data register with 0;

step P2: shifting the data of the data register by one bit to the left, reading in new data, placing the new data into the lowest bit of the data register, and performing exclusive or operation on the data in the data register and the generated polynomial when the shifted-out bit data is 1; if the shift-out bit data is 0, no processing is performed.

Step P3: repeating the step P2 until the 26-bit data bit is processed, wherein the content in the data register is CRC check code;

and step P4: comparing the CRC code and the CRC check code of the encoder position data, and outputting to obtain the encoder position data if the CRC code and the CRC check code of the encoder position data are consistent and the error bit is 1; otherwise, the frame data is discarded, and the next frame data is continuously checked.

FIG. 4 illustrates a ModelSim emulated state transition diagram, according to an embodiment of the present disclosure; FIG. 5 is a schematic diagram illustrating simulation results of inputting 3 frames of correct encoder position data according to an embodiment of the present disclosure; FIG. 6 is a diagram illustrating simulation results of inputting 1 frame of correct encoder position data and 2 frames of incorrect encoder position data according to an embodiment of the present disclosure.

For example, the FPGA-based asynchronous BiSS-C protocol decoding method is subjected to simulation verification by using ModelSim. As shown in fig. 4, the state jump diagram of the state machine of the BiSS-C data decoding module shows the decoding effect of the BiSS-C data decoding module when the transmission of the position data of the encoder is correct. If the 3 frames of valid serial data at the rxd end of the SLO line input signal are 60H, 480H and 81H, the CRC check codes corresponding to the valid serial data are 24H, 1EH and 1EH through calculation, and the error bit is 1, then the 3 frames of signals transmitted by the SLO line are obtained as follows: 18393FH, 12027BFH, 2067BFH. As can be seen from fig. 5, the output signals of the check output data biss _ out of the CRC check module are 60H, 480H, and 81H, that is, correct three frame data are obtained. And verifying the decoding effect of the BiSS-C data decoding module under the condition of the transmission error of the encoder position data, for example, the first frame data keeps 60E4H unchanged, the error bit of the second frame data is changed to 0, and the CRC check code of the third frame data is changed to EH. At this time, the serial data (encoder position data) inputted from the SLO line is correct only for the first frame data, and the ModelSim simulation result is shown in fig. 6. The simulation result shows that the output end of the bissc _ out signal of the check output data of the CRC check module is 60H, that is, only one correct frame of data is output after passing through the CRC check module, two frames of data with errors in transmission are discarded, and the simulation result is correct.

The asynchronous BiSS-C protocol decoding method based on the FPGA comprises a baud rate clock module, a BiSS-C data decoding module and a CRC (cyclic redundancy check) module; sampling encoder position data transmitted by an SLO line by using the baud rate clock module; decoding encoder position data transmitted by an SLO line by using a BiSS-C data decoding module based on a BiSS-C data protocol to obtain decoded data of the encoder position data; and the CRC check module is used for moving the decoded data of the encoder position data into a register to obtain a CRC check code of the encoder position data after detecting the encoder position data decoding completion mark, comparing the CRC code of the encoder position data with the CRC check code, and obtaining the encoder position data if the CRC code of the encoder position data is consistent with the CRC check code of the encoder position data. The method solves the problem that the position information of the encoder transmitted by the BiSS-C protocol is analyzed by using the FPGA under an asynchronous clock.

Although the embodiments of the present invention have been described above, the above descriptions are only for the convenience of understanding the present invention, and are not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (10)

1. An asynchronous BiSS-C protocol decoding method based on an FPGA is characterized in that the FPGA comprises a baud rate clock module, a BiSS-C data decoding module and a CRC checking module, and the method comprises the following steps:

sampling encoder position data transmitted by an SLO line by using the Baud rate clock module;

decoding encoder position data transmitted by an SLO line by using a BiSS-C data decoding module based on a BiSS-C data protocol to obtain decoded data of the encoder position data;

and when the encoder position data decoding completion mark is detected, the CRC check module moves the decoded data of the encoder position data into a register to obtain a CRC check code of the encoder position data, compares the CRC code of the encoder position data with the CRC check code, and obtains the encoder position data if the two codes are consistent.

2. The asynchronous BiSS-C protocol decoding method of claim 1, wherein said sampling encoder position data transmitted by SLO lines using said baud rate clock module comprises:

dividing the frequency of a system clock signal of the baud rate clock module to obtain a baud rate clock signal of the baud rate clock module;

and sampling the encoder position data transmitted by the SLO line based on the frequency of the baud rate clock signal of the baud rate clock module.

3. The asynchronous BiSS-C protocol decoding method of claim 1, wherein the decoding of the encoder position data transmitted by the SLO line using the BiSS-C data decoding module based on the BiSS-C data protocol comprises:

setting a state machine of the BiSS-C data decoding module based on a data frame format of a BiSS-C data protocol;

decoding encoder position data transmitted by an SLO line by using a state machine of the BiSS-C data decoding module;

wherein the state machine includes a WAIT state, an IDLE state, an ACK state, a START state, a ZERO state, and a DATA state.

4. The asynchronous BiSS-C protocol decoding method of claim 3, wherein said decoding encoder position data transmitted by an SLO line using a state machine of the BiSS-C data decoding module comprises:

when a system reset signal is detected, the state machine enters a WAIT state, and when an input signal of the SLO line is 1, the state machine jumps to an IDLE state;

in an IDLE state, when the input signal level of the SLO line is 0, the state machine jumps to an ACK state;

in the ACK state, when the input signal level of the SLO line is 1, the state machine jumps to the START state;

in a START state, when a START bit of the encoder position data frame is detected, the state machine jumps to a ZERO state;

in the ZERO state, when a "0" bit of an encoder position DATA frame is detected, the state machine jumps to the DATA state;

in the DATA state, encoder position DATA transmitted by an SLO line is received according to bits on the rising edge of a baud rate clock signal, and the encoder position DATA is moved into a shift register to be latched according to the sequence with the high bits in front, so that decoding DATA of the encoder position DATA is obtained.

5. The asynchronous BiSS-C protocol decoding method according to claim 4 wherein, in the ACK state, when the input signal level of the SLO line is 1, the state machine jumps to a START state; in a START state, when a START bit of the encoder position data frame is detected, the state machine transitions to a ZERO state; the method comprises the following steps:

wherein the START status comprises a START1 status and a START2 status;

in the ACK state, when the input signal level of the SLO line is 1, the state machine jumps to the state of START 1;

adding 1 to a baud rate clock counting signal baud _ counter on the rising edge of the baud rate clock signal, and sampling the input signal level of an SLO line to be used as a flag bit _ samp when the baud rate clock counting signal baud _ counter is 7;

in the case that the baud rate clock signal (baud _ pulse) is 1 and the baud rate clock count signal baud _ counter is greater than 8, when the flag bit _ samp is 1, the state machine jumps from the START1 state to the START2 state;

and adding 1 to the time count value cnt of the START2 state at the rising edge of the Baud rate clock signal, wherein when the level of the SLO line input signal is 0 and the time count value cnt of the START2 state is less than 20, the flag bit _ samp is the START bit of the encoder position data frame, and the state machine jumps to the ZERO state.

6. The asynchronous BiSS-C protocol decoding method of claim 5, wherein the "0" bit of the encoder position data frame comprises:

in the ZERO state, adding 1 to the baud rate clock count signal baud _ counter on the rising edge of the baud rate clock signal, and when the baud rate clock count signal baud _ counter is greater than 8, and the flag bit _ samp is 0, taking the flag bit _ samp as the 0 bit of the encoder position data frame.

7. The asynchronous BiSS-C protocol decoding method of claim 4, wherein said bit-wise receiving encoder position DATA transmitted by the SLO line on a rising edge of a baud-rate clock signal in the DATA state comprises:

and in the DATA state, receiving the encoder position DATA transmitted by the SLO line according to bits at the rising edge of a baud rate clock signal, and when receiving one-bit encoder position DATA, adding 1 to a DATA DATA bit counter value bit _ counter which increases from 0 to 33 in a circulating manner.

8. The asynchronous BiSS-C protocol decoding method of claim 7, wherein the encoder position data and decoded data of the encoder position data comprise: 26 bits of encoder position data, 1 bit of error bits, 1 bit of warning bits, 6 bits of CRC code.

9. The asynchronous BiSS-C protocol decoding method of claim 8, wherein the step of, after detecting the encoder position data decoding completion flag, the CRC check module moving the decoded encoder position data into a register to obtain a CRC check code of the encoder position data, comparing the CRC code of the encoder position data with the CRC check code, and if the two codes are identical, obtaining the encoder position data comprises:

p1: when the encoder position data decoding completion flag is detected, initializing a data register, storing 26-bit encoder position data, a 1-bit error bit and a 1-bit warning bit of decoded data of the encoder position data into the data register, and supplementing the latter 6 bits of the data register with 0;

p2: shifting the data of the data register by one bit to the left, reading in new data, placing the new data into the lowest bit of the data register, and performing exclusive-or operation on the data in the data register and the generated polynomial when the shifted-out bit data is 1;

p3: repeating the step P2 until the 26-bit data bit is processed, wherein the content in the data register is CRC check code;

p4: and comparing the CRC code and the CRC check code of the encoder position data, and outputting to obtain the encoder position data if the CRC code and the CRC check code of the encoder position data are consistent and the error bit is 1.

10. The asynchronous BiSS-C protocol decoding method of claim 1, wherein the frequency of the baud rate clock signal of the baud rate clock module is 16 times the MA frequency of the BiSS-C protocol clock.

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