CN115865755B - Parallel data calibration method for interconnection among multiple networks and electronic equipment - Google Patents
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Abstract
The invention discloses a parallel data calibration method and electronic equipment for interconnection among multiple networks. The method firstly adjusts the delay coefficient of the clock channel, finds a state which can enable most data channels to be sampled correctly, and then adjusts the delay coefficient of each data channel respectively. If all the data channels can not be correctly sampled in the clock channel delay state, the clock channel delay coefficient is adjusted again. The invention can achieve the aim that each data channel can be aligned with the clock channel by self-adapting dynamic adjustment of the time delay coefficients of the clock and the data channels, thereby ensuring the correct transmission of parallel data interconnected among a plurality of networks.
Description
Technical Field
The invention relates to the field of network-on-chip, in particular to a parallel data calibration method and electronic equipment for interconnection among multiple networks.
Background
With more and more processor cores integrated onto a single Chip, network On Chip (NoC) has become the mainstream communication structure of System On Chip (SoC) due to its high bandwidth and good flexibility and scalability. In the context of high performance computing and big data applications, system architects are continually required to integrate more cores, accelerators, and memory within a given power range. With the development of integrated circuit technology, electronic and physical limitations have led to continuous miniaturization and upgrading of semiconductor advanced processes. The solution of continuously realizing a large-scale system through a single chip inevitably faces the problems of greatly reduced yield, sharply increased design and mask costs, and the like.
The traditional single chip design scheme is changed into a multi-chip design scheme, and a scheme of interconnection by utilizing a high-speed interface or integration by utilizing an advanced packaging process becomes a better choice. While on-chip network-to-chip interconnection is a fundamental but important communication mode for multi-chip/multi-chip integration, it is attracting great attention from the research community and industry. However, because clock skew (clock skew) is introduced in the PCB wiring and the inter-chip interface portion, there are problems in the parallel data transmission process, such as phase drift and incomplete duty ratios of high and low levels, which may cause sampling errors of the data transmitted between chips by the downstream chip, and further cause errors or even loss of data packets.
Aiming at the problem of transmission errors caused by time sequence differences of parallel data, the aim that each data channel can be aligned with a clock channel is achieved by adjusting channel delay. The traditional mode has the advantages that the delay coefficient is manually adjusted, and after the sampling result of each channel is observed through continuous experiments, the delay coefficient of each channel is repeatedly corrected until the parallel data is completely correct, so that the time and the labor are consumed. There are also studies to adjust the channel delay coefficients using an automatic calibration algorithm, but the algorithm is only very limited in the range of calibratable for the data channels. Therefore, it is desirable to design a method that can dynamically adaptively adjust both clock and data channel delay coefficients to maximize calibration capability.
Disclosure of Invention
Aiming at the defects in the prior art, the parallel data calibration method and the electronic equipment for interconnection among multiple pieces of networks solve the problem that the delay coefficient of a clock channel and a data channel cannot be adjusted simultaneously in the prior art.
In order to achieve the aim of the invention, the invention adopts the following technical scheme:
the parallel data calibration method for interconnection among multiple pieces of networks comprises the following steps:
s1, setting a convergence threshold interval, and setting initial delay coefficient values of a clock channel and each data channel; wherein the initial interval of the convergence threshold interval is [0, m);
s2, judging whether the left endpoint value of the current convergence threshold interval is smaller than or equal to the total number of data channels, if so, entering a step S3; otherwise, judging that the calibration is not successful;
s3, judging whether the number of the data channels which are not aligned currently meets the current convergence threshold interval, if so, entering a step S4; otherwise, entering step S5;
s4, adjusting the delay coefficient value of each data channel under the current delay coefficient value of the clock channel, judging whether all the data channels can be correctly sampled, and if so, entering a step S6; otherwise, restoring the initial delay coefficient value of the data channel, and entering step S5;
s5, judging whether all delay coefficient values of the clock channel in the current convergence threshold interval are traversed, if yes, increasing both end point values of the current convergence threshold interval by m, recovering the initial delay coefficient value of the clock channel, and returning to the step S2; otherwise, selecting a clock channel delay coefficient value which is not traversed in the current convergence threshold interval, and returning to the step S3;
s6, respectively obtaining delay coefficient values corresponding to the current clock channel and the data channel, and completing calibration.
Further, the selectable delay coefficient interval of the clock channel is the same as the selectable delay coefficient interval of the data channel; the initial delay coefficient value of the clock channel is the upper limit value of the selectable delay coefficient interval; the initial delay coefficient value of the data channel is the intermediate value of the selectable delay coefficient interval, and the expression is:
wherein a is an initial delay coefficient value for the data channel; a, a max An upper limit value of a selectable delay coefficient interval of the data channel; a, a min A selectable delay coefficient interval lower limit value for the data channel; []Representing an integer arithmetic operation.
Further, in step S4, the specific method for adjusting the delay coefficient value of each data channel under the current delay coefficient value of the clock channel is as follows:
and traversing the delay coefficient value of each data channel in the selectable delay coefficient interval under the current delay coefficient value of the clock channel.
Further, in step S5, the specific method for selecting the clock channel delay coefficient value not traversed in the current convergence threshold interval is as follows:
subtracting 1 from the current clock channel delay coefficient value, and when the clock channel delay coefficient value after subtracting 1 is smaller than the lower limit of the selectable delay coefficient of the clock channel, judging that all delay coefficient values of the clock channel in the current convergence threshold interval are traversed; otherwise, judging that the traversal is not completed.
Further, the specific method for obtaining the delay coefficient value corresponding to the current data channel in step S6 is as follows:
for each data channel, acquiring a corresponding feasible delay coefficient interval which can be correctly sampled under the current clock channel delay coefficient value, and selecting the intermediate value of the feasible delay coefficient interval as a final delay coefficient to obtain the delay coefficient value corresponding to the current data channel; the expression is as follows:
s is the intermediate value of the feasible delay coefficient interval; s is(s) max An upper limit value of the feasible time delay coefficient interval; s is(s) min Is the lower limit value of the feasible time delay coefficient interval.
Further, the value of the parameter m is one seventh or one eighth of the total number of data channels to be calibrated.
Further, the step S2 of determining that the calibration is not successful includes the following operations:
the delay coefficient value of the clock channel is set as the intermediate value of the selectable delay coefficient interval, and the best delay coefficient value of each data channel is taken as the final delay coefficient value.
There is provided an electronic device, comprising:
a memory storing executable instructions; and
a processor configured to execute the executable instructions in the memory to implement a parallel data alignment method oriented to the interconnection between the networks on the plurality of pieces.
The beneficial effects of the invention are as follows:
1. the invention can achieve the aim that each data channel can be aligned with the clock channel by self-adapting dynamic adjustment of the time delay coefficients of the clock and the data channels, thereby ensuring the correct transmission of parallel data interconnected among a plurality of networks.
2. The smaller the parameter m of the invention is, the more severe the clock channel delay condition is satisfied in the threshold interval, namely the smaller the range of the clock channel delay coefficient which is screened out to satisfy the condition is, so that the invention can adapt to different clock channel delay conditions.
3. The invention sets the initial delay coefficient value of the clock channel to be larger than the initial delay coefficient value of the data channel, which is convenient for solving the problem that the clock channel lags the data channel for a period of time when the clock rising edge is used for sampling the data.
4. The invention adopts the mode that the initial delay coefficient value of the clock channel gradually decreases from the maximum value, thereby being convenient for judging whether the traversal is completed under the current convergence threshold value interval.
5. The invention increases the left end point value when adjusting the convergence threshold interval, can avoid searching the clock channel delay coefficient which is tried to be matched with all the data channel delay coefficients again, and further shortens the searching total time.
6. Searching for the most appropriate delay factor for each data channel under the proposed clock channel delay state takes a long time, and if this is done sequentially for each clock channel delay state, the searching efficiency will be very low. Therefore, after the convergence threshold interval is set to screen out the possibly proper clock channel delay coefficient, the operation of adjusting the delay coefficient of each data channel is carried out, so that the matching success rate can be improved, and the calibration time is saved.
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FIG. 1 is a schematic flow chart of the method;
FIG. 2 is a process flow diagram in an embodiment of the invention.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and all the inventions which make use of the inventive concept are protected by the spirit and scope of the present invention as defined and defined in the appended claims to those skilled in the art.
As shown in fig. 1, the parallel data calibration method for interconnection between networks on multiple pieces comprises the following steps:
s1, setting a convergence threshold interval, and setting initial delay coefficient values of a clock channel and each data channel; wherein the initial interval of the convergence threshold interval is [0, m);
s2, judging whether the left endpoint value of the current convergence threshold interval is smaller than or equal to the total number of data channels, if so, entering a step S3; otherwise, judging that the calibration is not successful;
s3, judging whether the number of the data channels which are not aligned currently meets the current convergence threshold interval, if so, entering a step S4; otherwise, entering step S5;
s4, adjusting the delay coefficient value of each data channel under the current delay coefficient value of the clock channel, judging whether all the data channels can be correctly sampled, and if so, entering a step S6; otherwise, restoring the initial delay coefficient value of the data channel, and entering step S5;
s5, judging whether all delay coefficient values of the clock channel in the current convergence threshold interval are traversed, if yes, increasing both end point values of the current convergence threshold interval by m, recovering the initial delay coefficient value of the clock channel, and returning to the step S2; otherwise, selecting a clock channel delay coefficient value which is not traversed in the current convergence threshold interval, and returning to the step S3;
s6, respectively obtaining delay coefficient values corresponding to the current clock channel and the data channel, and completing calibration.
The selectable time delay coefficient interval of the clock channel is the same as the selectable time delay coefficient interval of the data channel; the initial delay coefficient value of the clock channel is the upper limit value of the selectable delay coefficient interval; the initial delay coefficient value of the data channel is the intermediate value of the selectable delay coefficient interval, and the expression is:
wherein a is an initial delay coefficient value for the data channel; a, a max Data channel availabilitySelecting the upper limit value of the delay coefficient interval; a, a min A selectable delay coefficient interval lower limit value for the data channel; []Representing an integer arithmetic operation.
In step S4, the specific method for adjusting the delay coefficient value of each data channel under the current delay coefficient value of the clock channel is as follows: and traversing the delay coefficient value of each data channel in the selectable delay coefficient interval under the current delay coefficient value of the clock channel.
In step S5, the specific method for selecting the clock channel delay coefficient value not traversed in the current convergence threshold interval is as follows: subtracting 1 from the current clock channel delay coefficient value, and when the clock channel delay coefficient value after subtracting 1 is smaller than the lower limit of the selectable delay coefficient of the clock channel, judging that all delay coefficient values of the clock channel in the current convergence threshold interval are traversed; otherwise, judging that the traversal is not completed. In addition, the clock channel delay coefficient value can be randomly selected.
The specific method for acquiring the delay coefficient value corresponding to the current data channel in the step S6 is as follows: for each data channel, acquiring a corresponding feasible delay coefficient interval which can be correctly sampled under the current clock channel delay coefficient value, and selecting the intermediate value of the feasible delay coefficient interval as a final delay coefficient to obtain the delay coefficient value corresponding to the current data channel; the expression is as follows:
s is the intermediate value of the feasible delay coefficient interval; s is(s) max An upper limit value of the feasible time delay coefficient interval; s is(s) min Is the lower limit value of the feasible time delay coefficient interval.
In the implementation process, the value of the parameter m can be selected according to the total number of data channels to be calibrated, and the smaller the m is, the more severe the clock channel delay condition is satisfied in the threshold interval, namely the smaller the range of the clock channel delay coefficient which is screened out to satisfy the condition is, the faster the iteration clock channel delay coefficient is, but the slower the iteration threshold interval is. Preferably, the value of the parameter m is one seventh or one eighth of the total number of data channels to be calibrated. If the left end value k×m of the threshold interval is greater than the total number of data channels, it is indicated that an attempt has been made to adjust the delay coefficients of each data channel under all delay coefficients of the clock channel, but a delay condition combination that can enable all data channels to be sampled correctly cannot be found, so that it is determined that the situation is beyond the calibratable range and calibration cannot be successfully performed. The step S2 of determining that the calibration is not successful includes the following operations: the delay coefficient value of the clock channel is set as the intermediate value of the selectable delay coefficient interval, and the best delay coefficient value of each data channel is taken as the final delay coefficient value.
The electronic device includes:
a memory storing executable instructions; and
a processor configured to execute the executable instructions in the memory to implement a parallel data alignment method oriented to the interconnection between the networks on the plurality of pieces.
In one embodiment of the present invention, assuming 78 data lanes need to be aligned with the clock lanes, all lane delay factor adjustable ranges are [0,31 ]]I.e. an upper limit of 31 and a lower limit of 0. T in the figure apclk And T apdata Representing the delay coefficients of the clock channel and the data channel, respectively. Y and N represent satisfaction and non-satisfaction of the judgment condition, respectively. If a data channel is not aligned, that is, a signal transmitted by the data channel cannot be correctly sampled by a clock transmitted by a clock channel, the specific flow is described as follows:
as shown in fig. 2, first, by comprehensively considering the convergence difficulty and the convergence speed, the initial convergence threshold interval may be set to [0,10 ], the initial value of the clock channel delay coefficient is set to 31, and the initial values of all the data channel delay coefficients are set to 15.
And judging whether the number of the unaligned data channels under the clock channel delay coefficient condition meets a convergence domain value interval or not. If not, the clock channel delay coefficient needs to be subtracted by 1, and then the judgment is carried out again until the clock channel delay coefficient which can enable the number of unaligned data channels to meet the convergence domain value interval is found. Then, the search for the most appropriate delay coefficients for 78 data channels, respectively, can begin. If all data channels can search a delay coefficient which can be sampled correctly under the clock channel delay coefficient condition, the calibration is successful. Otherwise, the next clock channel delay coefficient that enables the number of misaligned data channels to meet the convergence threshold interval needs to be found again, but before that, the delay coefficients of all the data channels need to be restored to the initial value 15.
When the clock channel delay coefficient is reduced to 0, the convergence threshold interval needs to be readjusted, i.e. the left and right endpoints of the interval are increased by 10. If the increased left endpoint value is still not greater than the total number of data channels (78 in this example), the clock channel delay coefficient value may be restored to 31 and then the clock channel delay coefficient satisfying the new convergence domain value interval is re-found. Otherwise, the delay coefficient of the clock channel is directly set to be 15, and then the best delay coefficient of each data channel is searched on the basis. Although a combination of delay coefficients that will enable all data channels to be sampled correctly (i.e. calibration failure) cannot be found, it is guaranteed that the sampling situation is necessarily better than the original sampling state that has not been calibrated.
In summary, the invention can enlarge the application range of the calibration method and realize better calibration effect by considering the adjustment of the time delay of the clock channel and the data channel. The convergence speed of the calibration algorithm can be improved and the calibration efficiency can be improved by dynamically and adaptively changing the convergence threshold interval of the clock channel. Under the condition that the convergence threshold interval of the clock channel is met, each data channel independently searches a delay coefficient interval which can enable the data channel to be correctly sampled and searches out the most suitable delay coefficient, and therefore the accuracy of calibration can be improved.
Claims (8)
1. The parallel data calibration method for interconnection among multiple pieces of networks is characterized by comprising the following steps of:
s1, setting a convergence threshold interval, and setting initial delay coefficient values of a clock channel and each data channel; wherein the initial interval of the convergence threshold interval is [0, m);
s2, judging whether the left endpoint value of the current convergence threshold interval is smaller than or equal to the total number of data channels, if so, entering a step S3; otherwise, judging that the calibration is not successful;
s3, judging whether the number of the data channels which are not aligned currently meets the current convergence threshold interval, if so, entering a step S4; otherwise, entering step S5;
s4, adjusting the delay coefficient value of each data channel under the current delay coefficient value of the clock channel, judging whether all the data channels can be correctly sampled, and if so, entering a step S6; otherwise, restoring the initial delay coefficient value of the data channel, and entering step S5;
s5, judging whether all delay coefficient values of the clock channel in the current convergence threshold interval are traversed, if yes, increasing both end point values of the current convergence threshold interval by m, recovering the initial delay coefficient value of the clock channel, and returning to the step S2; otherwise, selecting a clock channel delay coefficient value which is not traversed in the current convergence threshold interval, and returning to the step S3;
s6, respectively obtaining delay coefficient values corresponding to the current clock channel and the data channel, and completing calibration.
2. The parallel data calibration method for interconnection between multiple networks on a chip according to claim 1, wherein the selectable delay coefficient interval of the clock channel is the same as the selectable delay coefficient interval of the data channel; the initial delay coefficient value of the clock channel is the upper limit value of the selectable delay coefficient interval; the initial delay coefficient value of the data channel is the intermediate value of the selectable delay coefficient interval, and the expression is:
wherein a is an initial delay coefficient value for the data channel; a, a max An upper limit value of a selectable delay coefficient interval of the data channel; a, a min A selectable delay coefficient interval lower limit value for the data channel; []Representing an integer arithmetic operation.
3. The parallel data calibration method for interconnection between multiple networks according to claim 2, wherein the specific method for adjusting the delay coefficient value of each data channel under the current delay coefficient value of the clock channel in step S4 is as follows:
and traversing the delay coefficient value of each data channel in the selectable delay coefficient interval under the current delay coefficient value of the clock channel.
4. The parallel data calibration method for interconnection between multiple networks according to claim 3, wherein the specific method for selecting the clock channel delay coefficient value not traversed in the current convergence threshold interval in step S5 is as follows:
subtracting 1 from the current clock channel delay coefficient value, and when the clock channel delay coefficient value after subtracting 1 is smaller than the lower limit of the selectable delay coefficient of the clock channel, judging that all delay coefficient values of the clock channel in the current convergence threshold interval are traversed; otherwise, judging that the traversal is not completed.
5. The parallel data calibration method for interconnection between multiple networks on the chip according to claim 3, wherein the specific method for obtaining the delay coefficient value corresponding to the current data channel in step S6 is as follows:
for each data channel, acquiring a corresponding feasible delay coefficient interval which can be correctly sampled under the current clock channel delay coefficient value, and selecting the intermediate value of the feasible delay coefficient interval as a final delay coefficient to obtain the delay coefficient value corresponding to the current data channel; the expression is as follows:
s is the intermediate value of the feasible delay coefficient interval; s is(s) max An upper limit value of the feasible time delay coefficient interval; s is(s) min Is the lower limit value of the feasible time delay coefficient interval.
6. The parallel data calibration method for interconnection between networks on a plurality of pieces according to claim 2, wherein the value of the parameter m is one seventh or one eighth of the total number of data channels to be calibrated.
7. The parallel data calibration method for interconnection between networks on multiple pieces according to claim 1, wherein after determining that the calibration cannot be successful in step S2 includes the following operations:
the delay coefficient value of the clock channel is set as the intermediate value of the selectable delay coefficient interval, and the best delay coefficient value of each data channel is taken as the final delay coefficient value.
8. An electronic device, comprising:
a memory storing executable instructions; and
a processor configured to execute executable instructions in memory to implement the parallel data alignment method for inter-network-on-chip interconnection of any of claims 1-7.
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