CN115865079A - High-precision phase difference measuring device and method for main clock link and standby clock link - Google Patents
High-precision phase difference measuring device and method for main clock link and standby clock link Download PDFInfo
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Abstract
The invention discloses a device and a method for measuring high-precision phase difference of a main clock link and a standby clock link, which are applied to the technical field of communication and comprise the following steps: reference signal common oscillator: the module for providing a common reference frequency signal, a same primary clock signal phase difference value measurement module and a standby clock signal phase difference value measurement module for the mixing phase discriminator comprises: a mixing phase discriminator: the phase-mixing detector is used for carrying out frequency-mixing phase demodulation on the clock signal to obtain a phase comparison signal; an analog-to-digital converter: for converting the phase-comparison signal into a digital signal; digital phase measurement analysis module: high-frequency sampling is carried out on the digital signals, and phase difference value calculation is carried out; the main and standby signal phase difference output module: and the phase difference module is used for outputting the phase difference of the main and standby signals according to the phase difference value output by the main clock signal phase difference value measuring module and the standby clock signal phase difference value measuring module. The invention improves the measurement resolution, enhances the anti-noise interference capability of measurement and ensures the measurement precision of the phase difference.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a device and a method for measuring a high-precision phase difference of a main clock link and a standby clock link.
Background
The redundant backup of the satellite clock reference signal is mainly realized by a method that two paths of mutually independent reference frequency signals are mutually hot-backed. Under normal conditions, the working reference frequency source is mainly relied on, the hot backup reference frequency source is automatically switched to when necessary, the two systems carry out a main-standby parallel operation mode and carry out signal cross comparison. In order to ensure the continuity and integrity of the reference frequency signal, the two sets of systems must be monitored in real time, when the change of the system is detected to exceed a preset threshold value, the change source is judged, the system which normally operates is automatically switched, and an alarm signal is generated. The difficulty of the stable switching technology of the satellite hot standby reference clock mainly lies in a high-precision synchronization method of a main standby clock reference signal and how to keep the phase and the frequency of a system output frequency signal consistent before and after switching.
In order to ensure that the frequency and phase consistency indexes of the main and standby clock links can meet the system requirements, the frequency and phase deviation of the main and standby clock links needs to be measured with high resolution and low noise, so that the stability, reliability and continuity of output clock frequency signals are ensured. A common phase comparison method is to condition two compared signals, and then obtain a phase-discriminated pulse, i.e., a phase-difference pulse width, through a phase discriminator. The switch gate of the counter is controlled by the phase discrimination pulse, and the pulse width of the phase difference is filled with the high-frequency clock pulse to measure the phase difference value. The counter uses the rising edge or the falling edge of the phase detection pulse signal as a trigger signal, so the method measures the counting error with +/-1 clock pulse, and the measurement resolution depends on the period of the clock pulse.
Therefore, how to provide a device and a method for measuring a high-precision phase difference of a main clock link and a standby clock link, which can measure the frequency and the phase deviation of the main clock link and the standby clock link with high resolution and low noise so as to ensure the stability, reliability and continuity of an output clock frequency signal, is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
In view of this, the present invention provides a device and a method for measuring a high-precision phase difference between a master clock link and a slave clock link.
In order to achieve the purpose, the invention adopts the following technical scheme:
a high-precision phase difference measuring device for a main clock link and a standby clock link comprises: the device comprises a reference signal common oscillator, a main clock signal phase difference value measuring module, a standby clock signal phase difference value measuring module and a main and standby signal phase difference output module;
the main clock signal phase difference value measuring module and the standby clock signal phase difference value measuring module are the same, and the method comprises the following steps:
a mixing phase discriminator: the phase-mixing detector is used for carrying out frequency-mixing phase demodulation on the clock signal to obtain a phase comparison signal;
an analog-to-digital converter: for converting the phase-comparison signal into a digital signal;
digital phase measurement analysis module: high-frequency sampling is carried out on the digital signals, and phase difference value calculation is carried out;
reference signal common oscillator: for providing a common reference frequency signal to the mixing phase detector;
the main and standby signal phase difference output module: and the phase difference module is used for outputting the phase difference of the main and standby signals according to the phase difference value output by the main clock signal phase difference value measuring module and the standby clock signal phase difference value measuring module.
Optionally, the digital direction finding bit analysis module includes: the digital phase-locked loop PLL, the digital sampling clock generator and the phase measurement output module;
digital phase locked loop, PLL, comprising: the digital frequency synthesizer DDS comprises a multiplier, an integral zero clearing device, a phase discriminator, a low-pass filter and a digital frequency synthesizer;
a multiplier: for multiplicative down-conversion of digital sinusoidal signals;
the integration zero clearing device is used for enabling the output signal to be output in proportion to the time integral value of the input signal;
a phase discriminator: phase discrimination for two digital sine multiplied signals;
a low-pass filter: loop low pass filtering for the integrated signal;
digital frequency synthesizer DDS: the digital low-pass filter is used for converting the output value of the digital low-pass filter into a reference frequency output;
digital sampling clock generator: the sampling clock is used for generating a non-integer frequency sampling clock from an input sampling clock signal and acting on a working clock of the digital phase-locked loop PLL;
a phase measurement output module: and the phase difference measuring device is used for measuring and outputting the phase difference value of the pulse per second signal PPS and the output signal of the digital phase-locked loop PLL.
Optionally, the phase difference between the main and standby signals is a difference between phase differences output by the main clock signal phase difference measurement module and the standby clock signal phase difference measurement module.
Optionally, the digital phase measurement analysis module and the main/standby signal phase difference output module are both stored in the computer.
The invention also provides a method for applying the high-precision phase difference measuring device for the main clock link and the standby clock link, which comprises the following steps:
step (1): respectively carrying out frequency mixing phase demodulation on the main clock signal and the standby clock signal through a frequency mixing phase discriminator based on a common reference frequency signal provided by a reference signal common oscillator to obtain a main phase comparison signal and a standby phase comparison signal;
step (2): respectively converting the main phase comparison signal and the standby phase comparison signal into digital signals through an analog-to-digital converter, and respectively inputting the digital signals into a digital phase measurement analysis module to calculate a phase difference value;
and (3): the main and standby signal phase difference output module outputs a main and standby signal phase difference according to the phase difference value of the main clock signal and the standby clock signal.
Optionally, the digital phase measurement analysis module performs phase difference calculation, specifically:
the main link is a, the standby link is B, and the sampling signals of a and B are respectively:
d A (n)＝Asin(θ)，d A (n-1)＝Asin(θ-φ)；
d B (n)＝B sin(θ+Δθ)，d B (n-1)＝B sin(θ+Δθ-φ)；
the phase difference measurement results are:
d(Δθ)＝d A (n-1)d B (n)-d B (n-1)d A (n)＝2AB sin(φ)sin(θ)；
design tense
Close to 90 degrees, d (Δ θ) ≈ 2AB · θ.
Optionally, the phase difference between the main and standby signals is a difference between phase differences of the main clock signal and the standby clock signal.
Optionally, the phase difference calculation and the phase difference calculation of the main and standby signals are both completed on a computer.
Compared with the prior art, the invention provides the device and the method for measuring the high-precision phase difference of the main clock link and the standby clock link. The phase difference value of the two signal sources can be obtained by using a common oscillator to respectively phase-discriminate with the two signal sources of which the phase difference needs to be measured and subtracting the two obtained phase differences to counteract the influence of the common oscillator. The measurement of two phase differences and the subtraction processing are completed in a computer after being converted into digital signals through a mode/counter device. The phase demodulation processing with the common oscillator can reduce the frequency of a signal source, is equivalent to amplifying the phase difference of two signals, improves the measurement resolution, and phase noise introduced by the common oscillator can be counteracted through a double-balanced structure design. In addition, the digital signal processing is used for replacing the phase difference measurement solution of the traditional counter, the signal output by the phase discriminator is sampled at a high sampling rate, the phase difference value is calculated, the functions of the traditional zero-crossing detection circuit and the traditional counter are replaced, the anti-noise interference measurement capability is enhanced, and the phase difference measurement precision is ensured.
Compared with the prior art, the invention has the following advantages:
the measurement bandwidth is greatly shrunk, and the measurement precision is greatly improved. After taking the phase measured by the narrow band tracking loop, the phase noise depends on the loop bandwidth,
wherein, P 10M (f) Is the noise power spectral density; b is L For loop bandwidth, the narrower the loop bandwidth, the higher the phase measurement accuracy, e.g. 10MHz reference clockAnd when the loop bandwidth is 1KHz, the measurement precision can reach within 50 ps.
The stability is good, and the clock edge judgment problem is avoided. The ADC only performs sampling action of hard-to-hard, the subsequent phase-locking algorithm is very simple, no judgment action statements such as if, else and then are available, and compared with an analog phase comparison mode, the stability is higher than 1 order of magnitude.
The anti-interference is strong. The circuit has very strong resistance to interference and glitch on a clock signal. When the clock signal has interference and glitch, other measurement methods may cause measurement errors or false operation, the problem does not exist in the invention, which is the advantage of narrow phase-locked loop PLL loop bandwidth. The requirements on the waveform are greatly reduced and the device can work at a very low signal-to-noise ratio.
The temperature drift is small. The direct sampling by the analog-to-digital converter ADC has no problem with shaping circuits. There is no zero crossing problem nor duty cycle variation problem caused by amplitude variation.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic structural diagram of the apparatus of the present invention.
Fig. 2 is a schematic structural diagram of a digital phase measurement analysis module according to the present invention.
FIG. 3 is a schematic flow chart of the method of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1:
the embodiment 1 of the present invention discloses a high-precision phase difference measuring apparatus for a master/slave clock link, as shown in fig. 1, including: the device comprises a reference signal common oscillator, a main clock signal phase difference value measuring module, a standby clock signal phase difference value measuring module and a main and standby signal phase difference output module;
the main clock signal phase difference value measuring module is the same as the standby clock signal phase difference value measuring module, and comprises the following steps:
the mixing phase discriminator: the phase-mixing detector is used for carrying out frequency-mixing phase demodulation on the clock signal to obtain a phase comparison signal;
an analog-to-digital converter: for converting the phase-comparison signal into a digital signal;
the digital phase measurement analysis module is stored in a computer: for high frequency sampling of a digital signal, performing a phase difference calculation, as shown in fig. 2, comprising: the digital phase-locked loop PLL, the digital sampling clock generator and the phase measurement output module;
digital phase locked loop, PLL, comprising: the digital frequency synthesizer DDS comprises a multiplier, an integral zero clearing device, a phase discriminator, a low-pass filter and a digital frequency synthesizer;
a multiplier: for multiplicative down-conversion of digital sinusoidal signals;
the integration zero clearing device is used for enabling the output signal to be output in proportion to the time integral value of the input signal;
a phase discriminator: phase discrimination for two digital sine-multiplied signals;
a low-pass filter: loop low pass filtering for the integrated signal;
digital frequency synthesizer DDS: the digital low-pass filter is used for converting the output value of the digital low-pass filter into a reference frequency output;
a digital sampling clock generator: the sampling clock is used for generating a non-integer frequency sampling clock from an input sampling clock signal and acting on a working clock of the digital phase-locked loop PLL;
a phase measurement output module: the phase difference measuring device is used for measuring and outputting the phase difference value of the PPS signal and the output signal of the digital phase-locked loop PLL;
reference signal common oscillator: for providing a common reference frequency signal to the mixing phase detector;
the main and standby signal phase difference output module is stored in the computer: and the phase difference module is used for outputting the phase difference of the main and standby signals according to the difference of the phase difference values output by the main clock signal phase difference value measuring module and the standby clock signal phase difference value measuring module.
Example 2:
the embodiment 2 of the invention discloses a satellite communication ranging method by using the high-precision phase difference measuring device of the main and standby clock links in the embodiment 1, and the specific results are as follows:
an important function of satellite communication ranging is to measure the difference between the system clock time of the satellite and the clock time of the communication transceiver. If the time difference is not measured, the measurement results cannot be directly used for time difference and autonomous orbit determination solution. Although the communication transceiver and the satellite are in the same time system source, a sine wave sent by a reference clock is used as a reference, for example, the 10MHz signal period corresponds to 100ns accuracy. For precise time synchronization measurement, the precision is still insufficient, and further measurement according to the precision is required.
By applying the high-precision phase difference measuring device of the main and standby clock links in the embodiment 1 of the invention to measure the phase of the reference signal sent to the communication transceiver and the phase of the local clock signal of the communication transceiver, the precision reaches 10ps magnitude.
Example 3:
embodiment 3 of the present invention discloses a method for applying the high-precision phase difference measurement apparatus of the main/standby clock links according to embodiment 1, as shown in fig. 3, including:
step (1): respectively carrying out frequency mixing phase demodulation on the main clock signal and the standby clock signal through a frequency mixing phase discriminator based on a common reference frequency signal provided by a reference signal common oscillator to obtain a main phase comparison signal and a standby phase comparison signal;
step (2): the main phase comparison signal and the standby phase comparison signal are converted into digital signals through the analog-to-digital converter and are respectively input into a digital phase measurement analysis module on a computer to calculate the phase difference value, and the method specifically comprises the following steps:
the main link is a, the standby link is B, and the sampling signals of a and B are respectively:
d A (n)＝Asin(θ)，d A (n-1)＝Asin(θ-φ)；
d B (n)＝B sin(θ+Δθ)，d B (n-1)＝B sin(θ+Δθ-φ)；
the phase difference measurement results are:
d(Δθ)＝d A (n-1)d B (n)-d B (n-1)d A (n)＝2AB sin(φ)sin(θ)；
design time
Close to 90 degrees, d (Δ θ) ≈ 2AB · θ.
Calculating a phase difference value by using a signal output by the high sampling rate phase discriminator to ensure the measurement precision of the phase difference;
when the clock of the sampling signal is 10MHz and the sampling bit number is 14 bits, the phase discrimination precision can reach d (delta theta) = 1/(10 x 10) 6 )/(2^14)＝6.1ps。
And (3): the main and standby signal phase difference output module on the computer outputs the main and standby signal phase difference according to the difference of the phase difference value of the main clock signal and the standby clock signal.
The embodiment of the invention discloses a device and a method for measuring high-precision phase difference of a main clock link and a standby clock link. The phase difference value of the two signal sources can be obtained by using a common oscillator to respectively phase-discriminate with the two signal sources of which the phase difference needs to be measured and subtracting the two obtained phase differences to counteract the influence of the common oscillator. The measurement of two phase differences and the subtraction processing are completed in a computer after being converted into digital signals through a mode/counter device. The phase discrimination processing with the common oscillator can reduce the frequency of a signal source, is equivalent to amplifying the phase difference of two signals, improves the measurement resolution, and the phase noise introduced by the common oscillator can be offset by the double-balanced structure design. And the digital signal processing is used for replacing the phase difference measurement solution of the traditional counter, the signal output by the phase discriminator is sampled at a high sampling rate, the phase difference value is calculated, the functions of the traditional zero-crossing detection circuit and the traditional counter are replaced, the anti-noise interference measurement capability is enhanced, and the phase difference measurement precision is ensured.
In the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (8)
1. A master-slave clock link high-precision phase difference measuring device is characterized by comprising: the device comprises a reference signal common oscillator, a main clock signal phase difference value measuring module, a standby clock signal phase difference value measuring module and a main and standby signal phase difference output module;
the master clock signal phase difference value measuring module and the standby clock signal phase difference value measuring module are the same and comprise:
a mixing phase discriminator: the phase-mixing detector is used for carrying out frequency-mixing phase demodulation on the clock signal to obtain a phase comparison signal;
an analog-to-digital converter: for converting the phase-comparison signal into a digital signal;
digital phase measurement analysis module: high-frequency sampling is carried out on the digital signals, and phase difference value calculation is carried out;
the reference signal common oscillator: for providing a common reference frequency signal to the mixing phase detector;
the main and standby signal phase difference output module: and the phase difference value measuring module is used for outputting the phase difference value of the main and standby signals according to the phase difference value output by the main clock signal phase difference value measuring module and the standby clock signal phase difference value measuring module.
2. The apparatus according to claim 1, wherein the digital direction-finding bit analyzing module comprises: the digital phase-locked loop PLL, the digital sampling clock generator and the phase measurement output module;
the digital phase-locked loop PLL includes: the digital frequency synthesizer DDS comprises a multiplier, an integral zero clearing device, a phase discriminator, a low-pass filter and a digital frequency synthesizer;
the multiplier: multiplication down-conversion for digital sinusoidal signals;
the integration zero clearing device is used for outputting an output signal in proportion to the time integral value of an input signal;
the phase discriminator is characterized in that: phase discrimination for two digital sine-multiplied signals;
the low-pass filter: loop low pass filtering for the integrated signal;
the digital frequency synthesizer DDS: the digital low-pass filter is used for converting the output value of the digital low-pass filter into a reference frequency output;
the digital sampling clock generator: the sampling clock is used for generating a non-integer frequency sampling clock from an input sampling clock signal and acting on the working clock of the digital phase-locked loop PLL;
the phase measurement output module: and the phase difference measuring device is used for measuring and outputting the phase difference value of the pulse per second signal PPS and the output signal of the digital phase-locked loop PLL.
3. The apparatus according to claim 1, wherein the phase difference between the main clock signal and the standby clock signal is a difference between phase differences output by the main clock signal phase difference measurement module and the standby clock signal phase difference measurement module.
4. The apparatus according to claim 1, wherein the digital phase measurement analysis module and the master/slave signal phase difference output module are both stored in a computer.
5. A method for applying the high-precision phase difference measuring device of the master/slave clock link according to any one of claims 1 to 4, comprising:
step (1): respectively carrying out frequency mixing phase demodulation on the main clock signal and the standby clock signal through a frequency mixing phase discriminator based on a common reference frequency signal provided by a reference signal common oscillator to obtain a main phase comparison signal and a standby phase comparison signal;
step (2): respectively converting the main phase comparison signal and the standby phase comparison signal into digital signals through an analog-to-digital converter, and respectively inputting the digital signals into a digital phase measurement analysis module to calculate a phase difference value;
and (3): and the main and standby signal phase difference output module outputs the main and standby signal phase difference according to the phase difference value of the main clock signal and the standby clock signal.
6. The method according to claim 5, wherein the digital phase measurement analysis module performs phase difference calculation, specifically:
the main link is a, the standby link is B, and the sampling signals of a and B are respectively:
d A (n)＝Asin(θ)，d A (n-1)＝Asin(θ-φ)；
d B (n)＝Bsin(θ+Δθ)，d B (n-1)＝Bsin(θ+Δθ-φ)；
the phase difference measurement results are:
d(Δθ)＝d A (n-1)d B (n)-d B (n-1)d A (n)＝2ABsin(φ)sin(θ)；
design time
Close to 90 degrees, d (Δ θ) ≈ 2AB · θ.
7. The method according to claim 5, wherein the phase difference between the main clock signal and the standby clock signal is a difference between phase differences of the main clock signal and the standby clock signal.
8. The method according to claim 5, wherein the phase difference calculation and the phase difference calculation of the main and standby signals are both performed on a computer.
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