CN115862725A

CN115862725A - Method for detecting reliability and service life of ammeter memory

Info

Publication number: CN115862725A
Application number: CN202211637847.1A
Authority: CN
Inventors: 章恩友; 金波; 蒋卫平; 姚晓峰; 马益平; 李海江; 刘灿; 金宇; 周斌; 毛伟; 李家佳
Original assignee: Ningbo Jianan Electronics Co ltd
Current assignee: Ningbo Jianan Electronics Co ltd
Priority date: 2022-12-20
Filing date: 2022-12-20
Publication date: 2023-03-28

Abstract

The invention relates to a method for detecting the reliability and the service life of an ammeter memory, which mainly comprises the following steps of (1) reading and writing data of a whole EEPPROM1, wherein all traversals are performed for 100 times, so that the time required by a test is shortened under the condition that no interval abnormity exists; (2) And (2) performing read-write test on a part of area of the EEPROM1 repeatedly for 100 ten thousand times, adopting distributed storage test due to large storage space of the EEPROM1 until the EEPROM1 meets the basic requirement after 100 ten thousand times of repeated test, and if 100 read-write abnormity occurs in the test process and 100 ten thousand read-write operations are not completed, indicating that the EEPROM1 does not meet the basic requirement of storage. The invention can realize the rapid detection of the read-write and the service life of the EEPROM, and avoid the problem that the EEPROM can not be detected due to overlong detection time, thereby reducing the probability of repair and reducing the resource waste caused by scrapping.

Description

Method for detecting reliability and service life of ammeter memory

Technical Field

The invention relates to a method for detecting the reliability and the service life of an ammeter memory.

Background

An electrically erasable programmable read-only memory (EEPROM) is generally used to store important user data, i.e., nonvolatile data. The EEPROM is a memory chip which can not lose the stored data after power failure, and is a plug-and-play memory. When the EEPROM is used, a user can erase the existing information on the EEPROM on line and can update the information on the EEPROM in real time. At present, a lot of products record important information or use information of users through an EEPROM, therefore, the EEPROM has an effective read-write function which is an important precondition for using the EEPROM to record data, and the effectiveness of the EEPROM read-write function is directly related to whether the important information of the users corresponding to the products can be normally stored and read.

In the prior art, the read-write function and the storage frequency of the EEPROM need to be tested so as to be put into use. If the problem of the EEPROM is detected in the process of detecting the read-write function of the EEPROM of the finished product or the product facing the market application, the finished product or the product facing the market application needs to be returned to a factory for maintenance or scrapped, the return to the factory for maintenance brings about a large repair cost, the scrapping causes resource waste, and the cost of the product is increased.

At present, an EEPROM generally stores data in a static storage manner, where received data are divided into a plurality of data packets with a size not larger than the capacity of a data block in the EEPROM according to relevance, and the data packets are written into the data block of the EEPROM, respectively. When a new data packet is received, the new data packet is written into the data block stored in the corresponding old data packet, that is, the new data packet overwrites the corresponding old data packet. Therefore, the data packet is updated every time the same corresponding address is erased, the erasing frequency of the data block corresponding to the data packet with the high updating frequency is high, the erasing frequency of the data block is limited, the limit value of the erasing frequency of the current data block is 100 ten thousand times, and after the erasing frequency reaches the limit value, the data block is invalidated, so that the corresponding EEPROM is also invalidated. Therefore, the static storage mode of the EEPROM ensures that the utilization rate of the data block is low and the service life is short. Meanwhile, whether the storage times of the data blocks can reach 100 ten thousand cannot be determined, so that the durability test of the EEPROM is required.

The EEPROM durability refers to the capability of a device for bearing repeated erasing, is a key index for representing the performance of the device, and is an important branch of reliability research and evaluation. Durability trials are very time consuming, sometimes reaching several weeks or even more in a single trial. To give an example of 10 ten thousand trials of a 28CO40 memory, the slice size is 256K, i.e. 1024 pages, the page write time is 10ms, and the slice erase time is 20ms. The time spent erasing and writing is (20 +10 + 1024) × 100000ms =1026 × 1000s, which is about 285 hours. The 'read verify' and other states are not taken into account to show time, and the endurance test process is generally erase-check null-write-read verify, which takes longer if the endurance test is extreme. Therefore, how to save time and improve efficiency and provide a scale for reliability evaluation and product inspection is very significant.

Disclosure of Invention

In order to overcome the defect of long durability test time consumption in the prior art, the invention provides a method for rapidly detecting the read-write function and the service life of an EEPROM.

The invention is realized by the following technical scheme:

a method for detecting reliability and service life of an ammeter memory is characterized in that: the hardware module mainly comprises a CPU, a test memory EEPROM1, a memory EEPROM2, an indicator light LED1, an indicator light LED2 and an indicator light LED3, and mainly comprises the following steps,

(1) Data reading and writing are carried out on the whole EEPPROM1, all traversal is carried out for 100 times, the time required by the test is shortened under the condition that interval abnormity does not exist, when the reading and writing detection of the EEPROM1 is successful, the reading and writing functions of all areas of the EEPROM1 are effective, and the LED1 is lightened after 100 traversal is finished;

(2) After the step (1), performing read-write test on a part of area of the EEPROM1 repeatedly for 100 ten thousand times, detecting the read-write function of the EEPROM1 by adopting a read-write mode of distributed storage because the storage space of the EEPROM1 is large, performing data read-write on a plurality of addresses by the distributed storage, for example, selecting the first 8 bytes and the middle 8 bytes of each page in the EEPROM1 to perform repeated test, and performing a large number of tests until the LED3 is lightened after the repeated test is performed for 100 ten thousand times, which indicates that the EEPROM1 meets the basic requirement;

if 100 times of read-write abnormity occurs in the test process and 100 ten thousand times of read-write operation is not finished, indicating that the EEPROM1 does not meet the basic requirements of storage, simultaneously lightening the LED2 and ending the test;

the data of the EEPROM2 is the test frequency of the EEPROM1, the test takes 1000 times as a period, and the data storage of the EEPROM2 is carried out after the EEPROM1 is continuously read and written for 1000 times, or the data storage of the EEPROM2 is also carried out when the read and write abnormity occurs in the test process;

preferably, the IIC communication protocol is used to perform data read-write test on EEPROM1 and store the test times of EEPROM2, wherein the IIC bus is a communication line formed by data line SDA and clock line SCI, and can be used to transmit and receive data. Which is mainly divided into four signals: idle state, start signal, stop signal, answer signal;

and (3) an idle state: when two signal lines of SDA and SCL of the IIC bus are at high level at the same time, the bus is specified to be in an idle state, at the moment, the field effect tube of the output stage of each device is in a cut-off state, namely, the bus is released, and the level is pulled high by the pull-up resistor of each of the two signal lines;

initial signals: when SCL is high, SDA jumps from high to low, and the starting signal is a level jump timing signal instead of a level signal;

stop signal: when SCL is high, SDA jumps from low to high, and the stop signal is also a level jump timing signal instead of a level signal;

the acknowledgement signal ACK: every time the transmitter sends a byte, the data bus is released during clock pulse 9 and a reply signal is fed back by the receiver. A valid acknowledgement bit (ACK) is defined to indicate that the receiver has successfully received the byte when the acknowledgement signal is low, and a non-acknowledgement bit (NACK) is defined to indicate that the receiver has not successfully received the byte when the acknowledgement signal is high;

the requirement for the feedback valid acknowledge bit ACK is that the receiver pulls the SDA line low during the low level preceding the 9 th clock pulse and ensures a stable low level during the high level of this clock, and if the receiver is the master, after it receives the last byte, it sends an ACK signal to inform the controlled transmitter to end the data transmission and releases the SDA line so that the master receiver sends a stop signal.

Preferably, the CPU is further connected with a 485 communication module, a data reading command for designating an address of the EEPROM2 is added in the CPU, so that the data of the EEPROM2 can be read through the 485 communication module, the designated data reading command is sent through the 485 communication module to read the data in the EEPROM2, meanwhile, a receiving and clearing command is added on the CPU to clear the test times in the EEPROM2, and the EEPROM2 can be conveniently reused.

The invention has the beneficial effects that: the invention can realize the rapid detection of the read-write and the service life of the EEPROM, and avoid that the EEPROM can not be detected due to overlong detection time, and the EEPROM is put into practical application after the read-write function of the EEPROM is verified successfully, thereby avoiding the problems that the storage frequency of the EEPROM is seriously inconsistent with the required storage frequency, the expected efficacy of the product can not be completed, and the product cost is increased due to the repair or scrap when the read-write function of the EEPROM has problems, thereby reducing the probability of repair and reducing the resource waste caused by scrap.

Drawings

Fig. 1 is a schematic diagram of the hardware architecture of the present invention.

FIG. 2 is a communication protocol diagram of the IIC.

Detailed Description

The invention is described in further detail below with reference to the figures and the detailed description.

A method for detecting reliability and service life of an ammeter memory is disclosed, as shown in figure 1, a hardware structure mainly comprises a CPU, a test memory EEPROM1, a storage memory EEPROM2, an indicator light LED1, an indicator light LED2 and an indicator light LED3.

The method mainly comprises the following steps:

(1) And performing data reading and writing on the whole EEPPROM1, and performing all traversals for 100 times, so as to ensure that the time required by the test is shortened under the condition that no interval abnormity exists, when the reading and writing detection of the EEPROM1 is successful, the reading and writing functions of all areas of the EEPROM1 are effective, and the LED1 is lightened after 100 traversals are completed.

After the printed circuit board corresponding to the product is assembled, the read-write function of the EEPROM1 installed on the PCB can be detected. Firstly, write detection is carried out on each storage space on the EEPROM1, and after the write detection is successful, read detection is continuously carried out on the storage space. Meanwhile, considering that the time required by the test is too long when the whole EEPROM1 is traversed in the whole area all the time, all the traversal selections are carried out for 100 times, so that the time required by the test can be greatly shortened under the condition that interval abnormity does not exist.

(2) After the step (1), performing read-write test on a part of area of the EEPROM1 repeatedly for 100 ten thousand times, detecting the read-write function of the EEPROM1 by adopting a read-write mode of distributed storage because the storage space of the EEPROM1 is large, for example, selecting the first 8 bytes and the middle 8 bytes of each page in the EEPROM1 to perform repeated test, and performing a large amount of tests until the test is repeated for 100 ten thousand times, and then lighting the LED3 to show that the EEPROM1 meets the basic requirements; if 100 times of read-write abnormity occurs in the test process and 100 ten thousand times of read-write operation is not finished, the EEPROM1 is indicated to be not in accordance with the basic storage requirement, the LED2 is lightened simultaneously, and the test is finished. In order to avoid excessive time consumption caused by reading and writing data of the EEPROM2 after the data of the EEPROM1 is read and written, the test takes 1000 times as a period, and the data of the EEPROM2 is stored after the EEPROM1 is continuously read and written for 1000 times, or the data of the EEPROM2 is also stored when read and written abnormally in the test process.

The test uses AT24C512, so that 512 pages are contained in the chip, each page has 128 bytes, and the test selects 2 addresses from the 2 addresses and repeatedly tests data of 8 bytes in the 2 addresses, so as to achieve the effect of reducing the time for testing the whole page of addresses, and certainly, the test can be performed in other modes such as middle 8 bytes and last 8 bytes. The EEPROM2 is used for recording the number of times of reading and writing the EEPROM1, and the number of times of reading and writing the EEPROM2 is 1/1000 of that of the EEPROM 1.

The data of the EEPROM2 is the test times of the EEPROM1, the data can be written in without being read all the time, and the data can be read by using a 485 communication module when required.

Meanwhile, the CPU is also connected with a 485 communication module, a data reading command for an appointed address of the EEPROM2 is added in the CPU so as to read the data of the EEPROM2 through the 485 communication module, the appointed data reading command is sent through the 485 communication module to read the data in the EEPROM2, and meanwhile, a receiving and clearing command is added on the CPU to clear the test times in the EEPROM2, so that the EEPROM2 can be conveniently reused.

The IIC communication protocol is used for carrying out data read-write test on the EEPROM1 and storing the test times of the EEPROM2, wherein the IIC bus comprises a communication line consisting of a data line SDA and a clock line SCI and can be used for transmitting data and receiving data. Which is mainly divided into four signals: idle state, start signal, stop signal, reply signal.

An idle state: when two signal lines SDA and SCL of the IIC bus are at high level at the same time, the bus is specified to be in an idle state, at the moment, the field effect transistor of the output stage of each device is in a cut-off state, namely the bus is released, and the level is pulled up by respective pull-up resistors of the two signal lines.

Initial signals: when SCL is high, SDA jumps from high to low, and the starting signal is a level jump timing signal instead of a level signal.

Stop signal: when the SCL is high, the SDA transitions from low to high, and the stop signal is also a level transition timing signal rather than a level signal.

In the process of testing the invention for multiple times, the time for the data of the EEPROM1 to reach 100 ten thousand times is about 50 hours, which is compared with 285 hours, and the time for detection is greatly reduced.

The invention actually carries out 100 times of data read-write test on the whole EEPPROM1 to detect whether the whole area is abnormal or not, and then carries out 100 ten thousand read-write tests on the selective area, thereby ensuring the detection of abnormal conditions and 100 ten thousand detection.

The invention can realize the rapid detection of the read-write and the service life of the EEPROM, and avoid that the EEPROM can not be detected due to overlong detection time, and the EEPROM is put into practical application after the read-write function of the EEPROM is verified successfully, thereby avoiding the problems that the storage frequency of the EEPROM is seriously inconsistent with the required storage frequency, the expected efficacy of the product can not be completed, and the product cost is increased due to the repair or scrap when the read-write function of the EEPROM has problems, thereby reducing the probability of repair and reducing the resource waste caused by scrap.

Claims

1. A method for detecting reliability and service life of an ammeter memory is characterized in that: the hardware module mainly comprises a CPU, a test memory EEPROM1, a memory EEPROM2, an indicator light LED1, an indicator light LED2 and an indicator light LED3, and mainly comprises the following steps,

the data of the EEPROM2 is the test frequency of the EEPROM1, the test takes 1000 times as a period, and the data storage of the EEPROM2 is carried out after the EEPROM1 is continuously read and written for 1000 times, or the data storage of the EEPROM2 is also carried out when the read and write abnormity occurs in the test process.

2. The method of claim 1, wherein the method comprises the following steps: the IIC communication protocol is used for carrying out data read-write test on the EEPROM1 and storing the test times of the EEPROM2, wherein the IIC bus comprises a communication line consisting of a data line SDA and a clock line SCI, and can be used for transmitting data and receiving data, and the IIC bus mainly comprises four signals: idle state, start signal, stop signal, answer signal;

and (3) an idle state: when two signal lines SDA and SCL of the IIC bus are at high level at the same time, the bus is specified to be in an idle state, at the moment, the field effect transistor of the output stage of each device is in a cut-off state, namely, the bus is released, and the level is pulled up by respective pull-up resistors of the two signal lines;

stop signal: when SCL is high, SDA jumps from low to high, and the stop signal is a level jump timing signal instead of a level signal;

the acknowledge signal ACK: each time a byte is transmitted by the transmitter, the data bus is released during clock pulse 9, and an acknowledgement signal is fed back by the receiver, wherein when the acknowledgement signal is low, a valid acknowledgement bit (ACK) is defined to indicate that the byte has been successfully accepted by the receiver, and when the acknowledgement signal is high, a non-acknowledgement bit (NACK) is defined to generally indicate that the byte has not been successfully received by the receiver;

the requirement for the feedback of the valid acknowledge bit ACK is that the receiver pulls the SDA line low during the low level preceding the 9 th clock pulse and ensures a stable low level during the high level of this clock, and if the receiver is the master, after it receives the last byte, it sends an ACK signal to inform the controlled sender to end the data transmission and releases the SDA line for the master receiver to send a stop signal.

3. The method of claim 2, wherein the method comprises the following steps: the CPU is further connected with a 485 communication module, a data reading command for an appointed address of the EEPROM2 is added to the CPU, so that the data of the EEPROM2 can be read through the 485 communication module, the appointed data reading command is sent through the 485 communication module to read the data in the EEPROM2, meanwhile, a receiving and clearing command is added to the CPU to clear the test times in the EEPROM2, and the EEPROM2 can be conveniently reused.