CN115862708A - Operation method of memristor array and data processing device - Google Patents
Operation method of memristor array and data processing device Download PDFInfo
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Abstract
An operation method of a memristor array and a data processing device. The method of operation of the memristor array includes a matrix-vector multiplication operation, the matrix-vector multiplication operation including: applying input voltages respectively corresponding to input data of each row in the memristor array to word lines of each row in the memristor array; respectively applying source line voltage to source lines of all columns in the memristor array to enable transistors in all memristor units of all rows in the memristor array to be conducted and work in a saturation region; applying a first fixed voltage to bit lines of each row in the memristor array; and detecting output current on source lines of all columns in the memristor array to obtain an output result. The operation method can relieve the influence of voltage drop caused by large current in the memristor array on the calculation precision, and reduces the design difficulty of an external circuit.
Description
Technical Field
The embodiment of the disclosure relates to an operation method of a memristor array and a data processing device.
Background
The memristor memory-computation integrated technology is expected to break the bottleneck of the traditional von Neumann architecture, realize the integration of device-level storage and computation, and avoid the data transportation process, thereby greatly saving the time delay and the energy consumption overhead, and being considered as the core of the next-generation intelligent system. However, each memristor cell in the memristor array adopts a 1T1R (1 transistor 1 memristor) basic cell structure, wherein the memristor is connected in series with one pole (for example, the drain) of the transistor, and for example, when a forward calculation is performed, a control voltage is applied to the gate of the transistor to fully turn on (turn on) the transistor so that the transistor is in a linear region, and at this time, the transistor is equivalent to a linear resistance. In operation, the entire memristor array behaves as a resistive network in which there is a severe voltage drop (IR drop). Therefore, when the current sensing quantization output mode is adopted, the above operation mode requires very high precision for the external driver and the quantization circuit (especially, the clamp circuit). This also ultimately leads to limited computational accuracy of traditional memristors, increased difficulty in external circuit design, and their area, power consumption, and speed as system performance bottlenecks.
Therefore, on the basis of 1T1R, a basic structure of a memristor unit of a 2T2R (2 transistor 2 memristor) is also provided, and the structure reduces the accumulated current on the wiring, relieves the problem of voltage drop and improves the calculation precision through local current differential calculation; concepts of using voltage domain or charge domain quantized sensing have also been proposed, but these approaches may sacrifice speed and accuracy while the size of the memristor array is still limited. Therefore, it becomes necessary to propose and verify a new type of array unit to meet the increased array scale and the reduced peripheral circuit under the high computational demand.
Disclosure of Invention
At least one embodiment of the present disclosure provides an operating method for a memristor array, wherein the memristor array comprises a plurality of rows and a plurality of columns of memristor cells, word lines corresponding to the rows in the memristor array, bit lines corresponding to the rows in the memristor array, source lines corresponding to the columns in the memristor array, each memristor cell comprises a transistor and a memristor, a gate of the transistor is connected to the word line corresponding to the row in which the memristor cell is located, a first pole of the transistor is connected to the source line corresponding to the column in which the memristor cell is located, a second pole of the transistor is connected to the first end of the memristor, and a second end of the memristor is connected to the bit line corresponding to the row in which the memristor cell is located. Wherein the method of operation comprises a matrix vector multiplication operation, wherein the matrix vector multiplication operation comprises: applying input voltages respectively corresponding to input data of each row in the memristor array to word lines of each row in the memristor array; respectively applying source line voltage to source lines of all columns in the memristor array to enable transistors in all memristor units of all rows in the memristor array to be conducted and work in a saturation region; applying a first fixed voltage to bit lines of each row in the memristor array; detecting output current on source lines of each column in the memristor array to obtain an output result.
At least one embodiment of the present disclosure provides a data processing apparatus including: the memristor array comprises a plurality of rows and columns of memristor units, word lines corresponding to the rows in the memristor array, bit lines corresponding to the rows in the memristor array, source lines corresponding to the columns in the memristor array, and a memory resistor, wherein each memristor unit comprises a transistor and a memristor, a grid electrode of the transistor is connected to the word line corresponding to the row in which the memristor unit is located, a first electrode of the transistor is connected to the source line corresponding to the column in which the memristor unit is located, a second electrode of the transistor is connected to a first end of the memristor, a second end of the memristor is connected to the bit line corresponding to the row in which the memristor unit is located, the word lines in the rows are coupled to the word line drivers, the source lines in the columns are coupled to the source line processing circuits, and the bit lines in the rows are coupled to the bit line processing circuits. The word line driver is configured to apply input voltages corresponding to the input data of each row in the memristor array to the word lines of each row in the memristor array; the source line driver is configured to apply source line voltages to source lines of all columns in the memristor array respectively so that transistors in all memristor units of all rows in the memristor array are conducted and work in a saturation region; the bit line driver is configured to apply a first fixed voltage to the bit lines of each row in the memristor array; the output processing circuit is configured to detect an output current on a source line of each column in the memristor array to obtain an output result.
Drawings
To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.
FIG. 1A shows a schematic diagram of a memristor cell with a 1T1R structure.
FIG. 1B shows a schematic diagram of a memristor cell having a 2T2R structure.
FIG. 2 shows a schematic diagram of an example memristor array structure.
FIG. 3 illustrates the manner in which a conventional memristor array operates when performing a matrix-vector multiplication operation.
FIG. 4 illustrates a schematic diagram of a buffered memristor cell in accordance with at least one embodiment of the present disclosure.
Fig. 5 illustrates an operating voltage application pattern for a memristor cell of a 1T1R structure in accordance with at least one embodiment of the present disclosure.
Fig. 6 illustrates an operating voltage application pattern for a memristor cell of a 2T2R structure in accordance with at least one embodiment of the present disclosure.
FIG. 7 illustrates a manner of operation of an example memristor array when performing a matrix vector multiplication operation in accordance with this disclosure.
FIG. 8 shows a schematic diagram of a memristor array with global bit lines in accordance with an example of the present disclosure.
FIG. 9 illustrates a manner of operation of an example memristor array in performing a set operation or an initialize operation in a programming operation, according to this disclosure.
FIG. 10 illustrates a manner of operation of an example memristor array in performing a reset operation in a programming operation in accordance with this disclosure.
Fig. 11 shows a schematic view of a processing device according to at least one embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Similarly, the word "comprising" or "comprises", and the like, means that the element or item preceding the word comprises the element or item listed after the word and its equivalent, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
Memristors (e.g., resistive random access memories, phase change memories, conductive bridge memories, etc.) are non-volatile devices whose conduction state can be adjusted by applying an external stimulus. The memristor is a two-terminal device, has the characteristics of adjustable resistance and non-volatilization, and is widely applied to integrated storage and calculation applications, such as forward calculation (reasoning) for an artificial neural network. An array of memristors can be used to perform matrix-vector multiplication (multiply-accumulate) computations in parallel, according to kirchhoff's current law and ohm's law, with both storage and computation occurring in the devices of the array. Based on the computing architecture, the storage and computation integrated computing without a large amount of data movement can be realized.
FIG. 1A shows a schematic diagram of a memristor cell with a 1T1R structure. As shown in fig. 1A, the memristor cell of the 1T1R structure includes one transistor M1 and one memristor R1.
For example, when the transistor M1 is an N-type transistor, its gate is connected to the word line WL, for example, when the word line WL inputs a high level, the transistor M1 is turned on; the first pole of the transistor M1 may be a source and configured to be connected to a source line SL; the second pole of the transistor M1 may be a drain and configured to be connected to a second end of the memristor R1, the first end of the memristor R1 being connected to the bit line BL.
For example, when the transistor M1 is a P-type transistor, its gate is connected to the word line WL, for example, when the word line WL inputs a low level, the transistor M1 is turned on; the first pole of the transistor M1 may be a drain and configured to be connected to a source line SL; the second pole of the transistor M1 may be a source and configured to be connected to a second end of the memristor R1, the first end of the memristor R1 being connected to the bit line BL.
It should be noted that the resistive random access memory structure may also be implemented as another structure, for example, a structure in which a first end of the memristor R1 is connected to the transistor and a second end is connected to the source line SL, which is not limited in this respect by the embodiments of the present disclosure.
The word line WL functions to apply a corresponding voltage to the gate of the transistor M1, thereby controlling the transistor M1 to be turned on or off. When the memristor R1 is operated, for example, a set operation or a reset operation is performed, the transistor M1 needs to be turned on first, that is, a turn-on voltage needs to be applied to the gate of the transistor M1 through the word line WL. After the transistor M1 is turned on, for example, a voltage may be applied to the memristor R1 through the source line SL and the bit line BL to change the resistance state of the memristor R1. For example, a set voltage may be applied through the bit line BL to cause the memristor R1 to be in a low resistance state; for another example, a reset voltage may be applied through the source line SL to cause the memristor R1 to be in a high resistance state. For example, the resistance value in the high resistance state is 100 times or more, for example 1000 times or more, the resistance value in the low resistance state.
In an embodiment of the present disclosure, the operation of the memristor R1 changing from a high resistance state to a low resistance state is referred to as a Set (Set) operation; the operation of the memristor R1 changing from a low resistance state to a high resistance state is referred to as a Reset (Reset) operation. In addition, the initialization process of the memristor means that a higher voltage is applied to the memristor, so that a conductive filament is induced to be formed inside the memristor. By applying a set voltage or a reset voltage between electrodes of the memristor, a conductive filament inside the memristor may be restored or broken. The initialization operation is usually performed only once during the life cycle of the resistive random access memory.
The memristor R1 has a threshold voltage, and when the input voltage amplitude is smaller than the threshold voltage of the memristor R1, the resistance value (or the conductance value) of the memristor R1 is not changed. In this case, the calculation may be performed with the resistance value (or conductance value) of the memristor R1 by inputting a voltage smaller than the threshold voltage; the resistance value (or conductance value) of the memristor R1 may be changed by inputting a voltage greater than a threshold voltage.
Fig. 1B shows a schematic diagram of a memristor cell with a 2T2R structure. As shown in fig. 1B, the memristor cell of the 2T2R structure includes two transistors M1 and M2 and two memristors R1 and R2. The following description will be given taking an example in which both the transistors M1 and M2 are N-type transistors.
The grid of the transistor M1 is connected with a word line WL1, for example, the transistor M1 is conducted when the word line WL1 of the transistor M1 inputs high level, the grid of the transistor M2 is connected with a word line WL2, for example, the transistor M2 is conducted when the word line WL2 of the transistor M2 inputs high level; the first pole of the transistor M1 may be a source and configured to be connected to the source line SL, the first pole of the transistor M2 may be a source and configured to be connected to the source line SL, and the first pole of the transistor M1 is connected to the first pole of the transistor M2 and connected together to the source line SL. A second pole of the transistor M1 may be a drain and configured to be connected to a second pole (e.g., a cathode) of the memristor R1, a first pole (e.g., an anode) of the memristor R1 being connected to the bit line BL 1; the second pole of the transistor M2 may be a drain and configured to be connected to a second pole (e.g., a cathode) of the memristor R2, a first pole (e.g., an anode) of the memristor R2 being connected to the bit line BL 2.
It should be noted that, the transistors M1 and M2 in the memristor unit with the 2T2R structure may also both adopt P-type transistors, or one is a P-type transistor and the other is an N-type transistor, and the control voltages of the transistors of different types are different, so that the control voltages need to be changed accordingly when being applied, and are not described herein again.
FIG. 2 shows a schematic diagram of an example memristor array structure. As shown in fig. 2, the memristor array is made up of memristor cells that make up an array of M rows and N columns, both M and N being positive integers (e.g., greater than 2, which may be 100 or more). Each memristor cell includes a switching element and one or more memristors. In fig. 2, WL <1>, WL <2> \8230: \8230, WL < M > respectively represent the first row, the second row \8230, and the M-th row of word lines, and the control electrodes (for example, the gates of the transistors) of the switching elements in the memristor cell circuits in each row are connected to the corresponding word line in the row; BL <1>, BL <2> \8230, BL < M > respectively represent a first row and a second row \8230, BL < M > respectively represents a bit line of the M row, and the memristor in the memristor unit circuit of each row is connected with the bit line corresponding to the row; SL <1>, SL <2> \8230, SL < N > respectively represent the first column and the second column \8230, SL < N > respectively represent the source lines of the N column, and the source electrodes of the transistors in the memristor unit circuits in each column are connected with the source lines corresponding to the columns.
The memristor cells in the memristor array of fig. 2 may be, for example, 1T1R structures or 2T2R structures. For a 2T2R structure, if the two transistors are of the same type, the gates of the two transistors may be connected to the same word line, while the two memristors connect two different bit lines, i.e., one row in the array has one word line and two bit lines; if the two transistors are of different types, the gates of the two transistors may be connected to different two word lines, while the two memristors connect different two bit lines, i.e., one row in the array has two word lines and two bit lines.
Embodiments of the present disclosure have no limitations on the type, structure, etc. of memristor devices. It should be noted that the transistor used in the embodiment of the present disclosure may be a thin film transistor or a field effect transistor (for example, a MOS transistor). The source and drain of the transistor may be symmetrical in structure, so that the source and drain may be indistinguishable in structure.
For example, a weight matrix of the neural network layer may be mapped to a conductance value matrix of the memristor array, the data to be processed is mapped as an input to an input voltage of the array word line, and the processing result is represented by an output current of the array source line. By inputting a voltage difference less than the threshold voltage of each memristor in the memristor array, a forward calculation (e.g., a matrix vector multiplication) may be performed using the conductance of the memristors.
FIG. 3 illustrates the manner in which a conventional memristor array operates when performing a matrix-vector multiplication operation. As shown in fig. 3, memristor cells of a 1T1R structure in the same row share word lines WL and bit lines BL, and memristor cells in the same column share source lines SL. To perform matrix vector multiplication calculations, first, the values of the matrix elements (e.g., weight values of the neural network) are mapped to the resistance values of the memristors in the corresponding memristor cells in the memristor array; next, each data element of the vector is applied to each bit line as an input voltage after digital-to-analog conversion, a transistor turn-on voltage is applied to each word line so that the transistors are turned on together and operate in a linear region, and a fixed voltage (e.g., ground voltage) is applied to each source line.
Therefore, a voltage difference (i.e., an input voltage applied to the corresponding row of the common bit line BL minus a fixed voltage applied to the corresponding source line SL) is applied to each memristor in the memristor array, so that a current is generated in the memristor, and the currents generated by the memristor cells in a column are collected as an output current on the corresponding source line SL. The matrix vector multiplication calculation is specifically performed as follows. According to kirchhoff's law, the output current of the memristor array can be obtained according to the following formula:
wherein, V i Is an input voltage, G, of BL on a bit line of an ith row in a memristor array ij Conductance value, I, of a memristor in the ith row and jth column of the memristor array j Is an output current, V, on a jth column source line SL of the memristor array sl The fixed voltage applied on the source line SL of the memristor array during the calculation process.
In the above operation, in the case of the memristor cell of 1T1R performing the forward calculation, the gate of the transistor is applied with the gate voltage to make the transistor tube operate in the linear region, so that the on-resistance of the transistor is ignored with respect to the resistance value of the memristor; at this time, a voltage is applied to each of the source line SL and the bit line BL so as to form a voltage difference between the source line SL and the bit line BL, and the voltage difference is directly applied to the memristor so as to generate a current to be output on the source line SL. During this forward calculation, a low resistance load is seen for the driver supplying the source line voltage and the driver of the bit line voltage.
As described above, current computational approaches for implementing a computationally-integrated memristor array inevitably have significant voltage drop (IR drop) effects, thereby causing accuracy problems and resulting in large external circuit overhead under drive capability and accuracy limitations.
In view of the above problems, at least one embodiment of the present disclosure provides an operating method for a memristor array and a corresponding data processing apparatus. The memristor array comprises a plurality of rows and columns of memristor units, word lines corresponding to the rows in the memristor array, bit lines corresponding to the rows in the memristor array, and source lines corresponding to the columns in the memristor array, wherein each memristor unit comprises a transistor and a memristor, the gate of the transistor is connected to the word line corresponding to the row in which the memristor unit is located, the first pole of the transistor is connected to the source line corresponding to the column in which the memristor unit is located, the second pole of the transistor is connected to the first end of the memristor, and the second end of the memristor is connected to the bit line corresponding to the row in which the memristor unit is located.
For example, the method of operation includes performing a matrix vector multiplication operation using a memristor array, or performing a programming operation on memristors of memristor cells in the memristor array, the programming operation including a set operation or a reset operation.
FIG. 4 illustrates a schematic diagram of a novel buffered memristor cell that may be used to store a collective operation, such as a matrix-vector multiplication operation, in accordance with at least one embodiment of the present disclosure. Unlike the 1T1R cell shown in fig. 1A, which applies an operating voltage directly across a memristor, in at least one embodiment of the present disclosure, as shown in fig. 4, an input voltage is reapplied to the memristor through a buffer circuit, and a current flowing through the memristor is also output through a buffer circuit. The input buffer circuit is used for converting low input impedance of the memristor unit into high input impedance, and the output buffer circuit is used for restraining the influence of voltage change at the current output end on the current.
In at least one example, the memristor cells of embodiments of the present disclosure are identical in structural composition to the memristor cells of the 1T1R structure shown in fig. 1A, each including one memristor and one transistor (e.g., MOS transistor). However, in various embodiments of the present disclosure, the operating voltage application manner for the memristor cell of the 1T1R structure is different from that of the current memristor cell as shown in fig. 3, and the embodiments of the present disclosure avoid problems such as voltage drop, accuracy degradation, and the like caused by the current operating voltage application manner based on different operation mechanisms based on making the transistor in different operating states.
Fig. 5 illustrates an operating voltage application pattern for a memristor cell of a 1T1R structure in accordance with at least one embodiment of the present disclosure. As shown in fig. 5, in the operation voltage application manner of the memristor cell of the 1T1R structure, the transistor in the memristor cell is made to operate in the saturation region by controlling the control voltage (word line voltage) applied to the gate of the transistor and the source line voltage applied to the source line SL within a certain range, and grounding the bit line voltage of the bit line BL, for example. A 1T1R memristor cell with a transistor operating in the saturation region may be referred to as a source follower cell. The grid electrode of a transistor in the source follower unit serves as a voltage input end, an input voltage is buffered through the source follower structure and then applied to the memristor, and current passing through the memristor flows through the transistor to reach a source line. In this process, the transistors in the source follower cells act as an input voltage buffer circuit on the one hand so that the input voltage is applied to the gates of the transistors and then buffered to the memristor, thereby increasing the impedance of the voltage input. On the other hand, the transistor also plays a role of an output current buffer, and the transistor works in a saturation region so as to restrain the influence of the change of the source line voltage on the output current.
For the operating voltage application mode shown in fig. 5, the transistor of the source follower cell operates in the saturation region during the forward calculation, and the current passing through the source follower cell substantially satisfies the following formula:
I＝f(V)*g(G)
f(V)＝a(V+b)
g(G)＝G+c
where V is the gate voltage of the source follower unit, G is the conductance of the memristor in the source follower unit, a is the voltage transfer coefficient of the source follower, b, c are coefficients related to the selected gate voltage and the memristor conductance range, which are constants in the calculation process. The above coefficients a, b and c may be obtained by measurement or experience. As shown in the above equation, the current of the source follower unit in the forward calculation process has a linear relationship with the gate voltage of the source follower unit and the conductance of the memristor.
In another example of the present disclosure, a memristor cell (source follower cell) of a 2T2R structure is reconstructed on the basis of the memristor cell of the above 1T1R structure (i.e., the above source follower cell).
Fig. 6 illustrates an operating voltage application pattern for a memristor cell of a 2T2R structure in accordance with at least one embodiment of the present disclosure. As shown in fig. 6, the memristor cell of the exemplary 2T2R structure includes 1 NMOS transistor and one PMOS transistor, the first poles (e.g., drains) of the two transistors being electrically connected to each other and to the corresponding source line SL, the gates of the two transistors being respectively connected to two different word lines; first ends of the two memristors are electrically connected to second poles (e.g., sources) of the two transistors, respectively, and second ends of the two memristors are connected to two different bit lines. The two word line voltages required by the two transistors to be started are different from each other, and the current passing through the NMOS transistor and the current passing through the PMOS transistor are subjected to difference and then are converged on the source line SL, so that the positive and negative weights can be realized, and the working current on the source line SL can be correspondingly reduced.
The following description is given by taking a memristor cell of a 1T1R structure as an example, where transistors in the memristor cell are NMOS transistors. Embodiments of the present disclosure are not limited to this case, and the specific operation manner may be adjusted accordingly according to the type, number, and the like of the transistors.
In an embodiment of the present disclosure, the method of operation for the memristor array described above includes a matrix vector multiplication operation, the matrix vector multiplication operation including: applying input voltages respectively corresponding to input data of each row in the memristor array to word lines of each row in the memristor array; respectively applying source line voltage to source lines of all columns in the memristor array to enable transistors in all memristor units of all rows in the memristor array to be conducted and work in a saturation region; applying a first fixed voltage to bit lines of rows in a memristor array; and detecting output current on source lines of all columns in the memristor array to obtain an output result.
FIG. 7 illustrates a manner of operation of an example memristor array when performing a matrix vector multiplication operation in accordance with this disclosure. For the memristor array of the memristor cells of the 1T1R structure of this example, the memristor cells of the 1T1R structure of the same row share the word line WL and the bit line BL, and the memristor cells of the same column share the source line SL. For matrix vector multiplication calculation, firstly, mapping a matrix unit value (weight value) to the resistance values of memristors in corresponding memristor units in the memristor array; next, each data element of the vector is applied to each word line as an input voltage after digital-to-analog conversion, the input voltage turns on each transistor, a source line voltage is applied to each source line so that each transistor operates in a saturation region, and a fixed voltage (an example of a first fixed voltage, for example, a ground voltage) is applied to each bit line. Current flows through the memristor, and the currents generated by a column of memristor units are converged on the corresponding source line SL to serve as output current.
f(V i )＝a(V i +b)
g(G ij )＝G ij +c
Wherein, V i Is a word line voltage (input voltage) applied on the word line of the ith row in the memristor array, G ij Conductance value, I, of memristor in ith row and jth column of memristor array j The output current on the source line SL of the jth column of the memristor array. In this calculation, the source line voltages applied to each source line SL may be the same as each other, and the voltage level may be selected so that each crystal operates in the saturation region.
In the calculation process, because each row of word lines WL is connected with the gate of the transistor in each memristor unit in the row, no current passes through the word lines WL in the forward calculation process, and no voltage drop (IR drop) is formed between different positions on the word lines WL, so that the word line voltage of each unit does not deviate from the voltage provided by the peripheral word line driver. In addition, for the design of the word line driver, the word line is only taken as a capacitive load (high impedance load) of the word line driver by the voltage input end, so that the design power consumption and the area of the word line driver are also greatly reduced.
In addition, the current of each column of memristor units is converged on the source line SL corresponding to the column to serve as the output current, so that voltage drop exists between different positions on the source line SL due to relatively large current and relatively long routing, and the influence of the voltage drop on the output current is greatly reduced because the transistor works in a saturation region. Likewise, since the transistors in the memristor cell are all operated in the saturation region, the output current of each column is less affected by the fluctuation of the source line voltage applied on the source line SL, and the source line voltage does not need to be clamped accurately, which can reduce the area and power consumption overhead of the external clamp circuit.
In another example, to optimize the memristor array operation, the memristor array may also short all bit lines BL, forming one or more global bit lines GBL that can further reduce the voltage drop on the bit lines BL.
FIG. 8 shows a schematic diagram of a memristor array with global bit lines in accordance with an example of the present disclosure. The memristor array of this structure may also perform matrix vector multiplication calculations (and programming operations to be described later) in the manner shown in fig. 7.
For example, the matrix vector multiplication operation further includes performing digital-to-analog conversion on the input data of each row in the memristor array to obtain a corresponding input voltage.
For example, in the matrix-vector multiplication, the output current of each column in the memristor array is analog-to-digital converted to obtain an output result in a digital form.
As described above, for the embodiment of the present disclosure, to perform matrix vector multiplication calculation using the memristor array, it is necessary to first map the values of the matrix elements (e.g., the weight values of the neural network) to the resistance values of the memristors in the memristor array, i.e., to perform a programming operation on the memristor array.
By inputting an operating voltage greater than the threshold voltage of each memristor in the memristor array, the conductance value of the memristor may be changed such that the conductance value of the memristor corresponds to the weight value that needs to be mapped, which is referred to as a programming operation. The program operation includes a set operation and a reset operation.
For example, the setting operation includes: applying a first control voltage to a word line of a row in which a memristor cell is set to cause a transistor of the set memristor cell to turn on, and applying a second control voltage to other word lines in the memristor array to cause transistors of the memristor cells in other rows to turn off; applying a corresponding set voltage to a bit line of a row in which the set memristor cell is located, and applying a first fixed voltage to other bit lines of the memristor array; the method comprises the steps of applying a first fixed voltage to a source line of a column where the set memristor unit is located, and applying a set voltage to other source lines of the memristor array.
For example, the second control voltage is the same as the first operating voltage, e.g., both are the ground voltage (GND).
FIG. 9 illustrates a manner of operation of an example memristor array when performing a set (set) operation or an initialization (forming) operation in a programming operation, in accordance with the present disclosure. For the memristor array of the memristor cells of the 1T1R structure of this example, the memristor cells of the 1T1R structure of the same row share the word line WL and the bit line BL, and the memristor cells of the same column share the source line SL.
As shown in fig. 9, in the setup/initialization operation, a high level is applied to a word line WL corresponding to a row in which a memristor cell selected for setup/initialization is located, so that a transistor connected to the word line is turned on, a source line SL of a column in which the memristor cell selected for setup/initialization is located is set to a fixed voltage (low level, for example, grounded), and at the same time, a bit line BL or a global bit line in the row in which the memristor cell is located is set to a required operation voltage, the operation voltage being at a high level, for example, corresponding to a value of a setup voltage or an initialization voltage required for the setup/initialization operation, so that the setup/initialization operation for the memristor cell can be realized. In addition, it is also necessary to set the source lines SL of other unselected memristor cells in the row of the selected memristor cell to the same high level as the bit lines BL (so that the voltage difference across the memristors in the memristor cells is 0), and set the word lines WL of other rows in the memristor array to the low level to turn off the transistors connected to the word lines, so that only the selected memristor cell performs the set/initialize operation, and the other memristor cells do not perform the set/initialize operation.
For example, the reset operation includes: applying a first control voltage to a word line of a row in which the memristor cell is set to turn on a transistor of the set memristor cell, applying a second control voltage to other word lines of the memristor array to turn off transistors of the memristor cells in the other rows, applying a first fixed voltage to bit lines of each row in the memristor array; a reset voltage is applied to a source line of a column where the set memristor cells are located, and a first operating voltage is applied to other source lines of the memristor array.
For example, the second control voltage is the same as the first operating voltage, e.g., both are the ground voltage (GND).
FIG. 10 illustrates a manner of operation of an example memristor array in performing a reset operation in a programming operation, according to this disclosure. The memristor array corresponds to the memristor array shown in fig. 8.
As shown in fig. 10, when a reset operation is performed, a word line WL corresponding to a row in which a memristor cell selected for reset is located is set to a high level to turn on a transistor connected to the word line, a source line SL of a column in which the memristor cell selected for reset is located is set to a reset voltage (high level), and at the same time, a bit line or a global bit line in the row in which the memristor cell is located is set to a fixed voltage (low level, for example, ground), thereby implementing the reset operation on the memristor cell. In addition, the source line SL of the column where other unselected memristor cells in the row where the memristor cell selected for resetting is located are set to the same low level (for example, ground) as the bit line BL (so that the voltage difference across the memristors in the memristor cells is 0), and the word line WL of the other rows is set to the low level to turn off the transistors connected to the word lines, so that only the memristor cell selected for resetting is subjected to the resetting operation, and the other memristor cells are not subjected to the resetting operation.
The embodiment of the disclosure also provides a data processing device based on the memristor and the corresponding operation mode.
Fig. 11 illustrates a schematic diagram of a data processing apparatus provided in accordance with at least one embodiment of the present disclosure. As shown in fig. 11, the data processing apparatus includes a word line driver, a source line driver, a bit line driver, an output processing circuit, and a memristor array.
The memristor array may be, for example, the memristor array shown in fig. 7-8. The word line driver is configured to apply input voltages corresponding to input data of each row in the memristor array to the word lines of each row in the memristor array; the source line driver is configured to apply source line voltages to source lines of all columns in the memristor array respectively, so that transistors in all memristor units of all rows in the memristor array are conducted and work in a saturation region; the bit line driver is configured to apply a first fixed voltage to the bit lines corresponding to the rows in the memristor array; the output processing circuit is configured to detect an output current on a source line of each column in the memristor array to obtain an output result.
For example, the data processing apparatus further includes an input circuit, wherein the input circuit is configured to digital-to-analog convert (DAC) input data for each row in the memristor array to obtain a corresponding input voltage, and to provide the corresponding input voltage to the word line driver.
For example, in the data processing apparatus described above, the output processing circuit is further configured to receive the output currents of the columns in the memristor array, and perform analog-to-digital conversion (ADC) on the output currents to obtain the output result in digital form.
The above-described drivers, processing circuits, and input circuits may be implemented by digital circuits, analog circuits, or any combination thereof.
As described above, each memristor cell includes a single transistor and a single memristor, and the transistors and memristors are connected to each other and to corresponding word lines, bit lines, and source lines as described above; or each memristor unit comprises two transistors and two memristors, the two transistors and the two memristors are respectively connected with each other as described above, first poles of the two transistors are electrically connected with each other and with a source line corresponding to a row where the memristor unit is located, gates of the two transistors are respectively connected with two different word lines corresponding to the row where the memristor unit is located, and second ends of the two memristors are electrically connected with two different bit lines corresponding to the row where the memristor unit is located.
The novel memristor-array-based integrated storage and calculation structure provided by at least one embodiment of the disclosure, namely, the memristor-integrated storage and calculation circuit structure based on the buffer type unit structure, can relieve the influence of a voltage drop (IR drop) caused by a large current in the memristor array on the calculation precision, and reduce the design difficulty of an external circuit, thereby eliminating a static current load of a driver during calculation, greatly reducing the clamping precision requirement of a quantization module, and enabling the memristor-integrated storage and calculation system to realize higher energy efficiency and calculation power.
For example, at least one embodiment of the present disclosure further provides an electronic apparatus, where the electronic apparatus includes the data processing apparatus, and the electronic apparatus may be implemented as any device, such as a mobile phone, a tablet computer, a notebook computer, an electronic book, a game machine, a television, a digital photo frame, a navigator, a home appliance, a communication base station, an industrial controller, a server, and the like, or may be a combination of any data processing apparatus and hardware, and the embodiment of the present disclosure is not limited thereto.
For the present disclosure, there are also the following points to be explained:
(1) The drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to the common design.
(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.
The above are merely exemplary embodiments of the present disclosure and are not intended to limit the scope of the present disclosure, which is defined by the appended claims.
Claims (12)
1. An operating method for a memristor array, wherein the memristor array comprises a plurality of rows and a plurality of columns of memristor cells, word lines corresponding to the rows in the memristor array, bit lines corresponding to the rows in the memristor array, source lines corresponding to the columns in the memristor array, each memristor cell comprising a transistor and a memristor, a gate of the transistor is connected to the word line corresponding to the row in which the memristor cell is located, a first pole of the transistor is connected to the source line corresponding to the column in which the memristor cell is located, a second pole of the transistor is connected to a first end of the memristor, and a second end of the memristor is connected to the bit line corresponding to the row in which the memristor cell is located,
the method of operation comprises a matrix vector multiplication operation, wherein the matrix vector multiplication operation comprises:
applying input voltages respectively corresponding to input data of each row in the memristor array to word lines of each row in the memristor array;
respectively applying source line voltage to source lines of all columns in the memristor array to enable transistors in all memristor units of all rows in the memristor array to be conducted and work in a saturation region;
applying a first fixed voltage to bit lines of each row in the memristor array;
detecting output current on source lines of each column in the memristor array to obtain an output result.
2. The method of operation of claim 1, wherein applying the first fixed voltage to the bit lines of each row in the memristor array comprises:
shorting bit lines of rows to each other in the memristor array to apply the first fixed voltage.
3. The method of operation of claim 1, wherein the matrix vector multiplication operation further comprises:
and performing digital-to-analog conversion on the input data of each row in the memristor array to obtain the corresponding input voltage.
4. The method of operation of claim 1, wherein detecting an output current on a source line of each column in the memristor array to obtain the output result comprises:
performing analog-to-digital conversion on the output current of each column in the memristor array to obtain the output result in a digital form.
5. The operating method of claim 1, wherein the operating method further comprises a programming operation, wherein the programming operation comprises a set operation and a reset operation for memristors of the memristor cells being set.
6. The operating method of claim 5, wherein the setting operation comprises:
applying a first control voltage to a word line of the row in which the set memristor cell is located to cause a transistor of the set memristor cell to turn on, and applying a second control voltage to other word lines in the memristor array to cause transistors of the memristor cells in the other rows to turn off;
applying a corresponding set voltage to a bit line of the row in which the set memristor cell is located, applying a first operating voltage to other bit lines of the memristor array;
the first operating voltage is applied to a source line of a column in which the set memristor cells are located, and the set voltage is applied to other source lines of the memristor array.
7. The operating method of claim 5, wherein the reset operation comprises:
applying a first control voltage to a word line of the row in which the set memristor cell is located to cause a transistor of the set memristor cell to turn on, and applying a second control voltage to other word lines of the memristor array to cause transistors of the memristor cells in other rows to turn off;
applying a first operating voltage to bit lines of each row in the memristor array;
applying a reset voltage to a source line of a column in which the set memristor cells are located, and applying the first operating voltage to other source lines of the memristor array.
8. The operating method according to claim 6 or 7, wherein the second control voltage is the same as the first operating voltage.
9. A data processing apparatus comprising:
a word line driver, a source line driver, a bit line driver and an output processing circuit; and
a memristor array, wherein the memristor array comprises a plurality of rows and a plurality of columns of memristor cells, word lines corresponding to rows in the memristor array, bit lines corresponding to rows in the memristor array, source lines corresponding to columns in the memristor array, each memristor cell comprising a transistor and a memristor, a gate of the transistor being connected to the word line corresponding to the row in which the memristor cell is located, a first pole of the transistor being connected to the source line corresponding to the column in which the memristor cell is located, a second pole of the transistor being connected to a first end of the memristor, a second end of the memristor being connected to the bit line corresponding to the row in which the memristor cell is located, the word lines of the rows being coupled to the word line driver, the columns of the memristor being coupled to the source line processing circuit, the bit lines of the rows of the memristor array being coupled to the bit line processing circuit,
wherein the content of the first and second substances,
the word line driver is configured to apply input voltages corresponding to the input data of the rows in the memristor array to the word lines of the rows in the memristor array respectively,
the source line driver is configured to apply source line voltages to source lines of columns in the memristor array respectively so as to enable transistors in memristor units of rows in the memristor array to be conducted and work in a saturation region,
the bit line drivers are configured to apply a first fixed voltage to the bit lines of each row in the memristor array,
the output processing circuit is configured to detect an output current on a source line of each column in the memristor array to obtain an output result.
10. The data processing apparatus of claim 9, further comprising input circuitry, wherein the input circuitry is configured to digital-to-analog convert input data for each row in the memristor array to obtain the corresponding input voltage, and to provide the corresponding input voltage to the wordline driver.
11. The data processing apparatus of claim 9, wherein the output processing circuitry is further configured to receive the output currents of the columns in the memristor array and to analog-to-digital convert the output currents to obtain the output result in digital form.
12. The data processing apparatus of claim 9, wherein each of the memristor cells comprises a single transistor and a single memristor, or,
the first poles of the two transistors are electrically connected with each other and are electrically connected to a source line corresponding to the row where the memristor units are located, the gates of the two transistors are respectively connected to two different word lines corresponding to the row where the memristor units are located, and the second ends of the two memristors are electrically connected to two different bit lines corresponding to the row where the memristor units are located.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211477580.4A CN115862708A (en) | 2022-11-23 | 2022-11-23 | Operation method of memristor array and data processing device |
| PCT/CN2023/132237 WO2024109644A1 (en) | 2022-11-23 | 2023-11-17 | Method for operating memristor array, and data processing apparatus |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211477580.4A CN115862708A (en) | 2022-11-23 | 2022-11-23 | Operation method of memristor array and data processing device |
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| CN115862708A true CN115862708A (en) | 2023-03-28 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116151344A (en) * | 2023-04-18 | 2023-05-23 | 中国人民解放军国防科技大学 | Current compensation method and device for memristor array access resistor |
-
2022
- 2022-11-23 CN CN202211477580.4A patent/CN115862708A/en active Pending
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- 2023-11-17 WO PCT/CN2023/132237 patent/WO2024109644A1/en unknown
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116151344A (en) * | 2023-04-18 | 2023-05-23 | 中国人民解放军国防科技大学 | Current compensation method and device for memristor array access resistor |
| CN116151344B (en) * | 2023-04-18 | 2023-06-30 | 中国人民解放军国防科技大学 | Current compensation method and device for memristor array access resistor |
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| WO2024109644A1 (en) | 2024-05-30 |
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