CN115862561A - Signal transmission method and device, source driver and electronic equipment - Google Patents

Abstract

The disclosure relates to a signal transmission method, a signal transmission device, a source driver and an electronic device. The signal transmission method is applied to a source driver, the source driver is in communication connection with a controller through a low-voltage differential signal interface mode, and the method comprises the following steps: acquiring a clock signal and a correction signal provided by a controller; determining a timing offset value between the clock signal and the correction signal according to the clock signal and the correction signal; and adjusting a timing relationship between the clock signal and the correction signal using a delay unit based on the timing offset value, wherein the delay unit is disposed in a clock path of the clock signal or in a data path of the correction signal. The signal transmission method can relieve the time delay between the clock signal and the data signal in the process of transmitting the data signal between the controller and the source driver, ensure the accurate transmission of the data signal and is beneficial to improving the communication frequency between the source driver and the controller.

Description

Signal transmission method and device, source driver and electronic equipment

Technical Field

Embodiments of the present disclosure relate to a signal transmission method, apparatus, source driver, and electronic device.

Background

In the field of display technology, for example, a pixel array of a liquid crystal display panel or an Organic Light Emitting Diode (OLED) display panel generally includes a plurality of rows of gate lines and a plurality of columns of data lines arranged to cross the gate lines. A timing controller (T-con) of the display panel needs to supply gate signals and data signals to a plurality of rows of gate lines and a plurality of columns of data lines through a gate driving circuit and a source driving circuit, respectively, so as to form gray voltages required for each gray scale required for displaying an image in pixel units of each row in a line-by-line scanning manner, for example, and further display one frame of image.

Disclosure of Invention

At least one embodiment of the present disclosure provides a signal transmission method, applied to a source driver, where the source driver is communicatively connected to a controller through a low voltage differential signal interface, and the method includes: acquiring a clock signal and a correction signal provided by the controller; determining a timing offset value between the clock signal and the correction signal according to the clock signal and the correction signal; and adjusting a timing relationship between the clock signal and the correction signal using a delay unit based on the timing offset value, wherein the delay unit is disposed in a clock path of the clock signal or a data path of the correction signal.

At least one embodiment of the present disclosure provides a signal transmission apparatus, configured to communicatively connect a source driver and a controller via a low voltage differential signal interface, where the signal transmission apparatus includes: an acquisition unit configured to acquire a clock signal and a correction signal provided by the controller; a determination unit configured to determine a timing offset value between the clock signal and the correction signal according to the clock signal and the correction signal; and an adjusting unit configured to adjust a timing relationship between the clock signal and the correction signal using a delay unit disposed in a clock path of the clock signal or a data path of the correction signal based on the timing offset value.

At least one embodiment of the present disclosure provides a source driver for communicatively coupling with a controller via a low voltage differential signaling interface, the source driver comprising: a processing circuit configured to obtain a clock signal and a correction signal provided by the controller, and determine a timing offset value between the clock signal and the correction signal according to the clock signal and the correction signal; and a delay circuit, disposed in a clock path of the clock signal or in a data path of the correction signal, configured to adjust a timing relationship between the clock signal and the correction signal based on the timing offset value.

At least one embodiment of the present disclosure provides an electronic device including: any embodiment of the present disclosure provides a source driver, a controller and a display panel. A controller configured to provide a display signal to the source driver; the display panel is connected with the source driver to receive the driving signal provided by the source driver, and the driving signal is generated based on the display signal.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

FIG. 1A is a schematic diagram of a circuit driving system of a display panel;

fig. 1B shows a system architecture diagram of the timing controller TCON and source driver connections;

FIG. 1C is a diagram illustrating a source driver acquiring a data signal via a mini-LVDS interface;

FIG. 1D illustrates a timing diagram of a data signal and a clock signal;

fig. 2A illustrates a flow chart of a signal transmission method provided by at least one embodiment of the present disclosure;

FIG. 2B is a schematic diagram of another source driver acquiring data signals through the mini-LVDS interface;

fig. 3A illustrates a flowchart of a method of step S20 in fig. 2A according to at least one embodiment of the present disclosure;

FIG. 3B illustrates a timing diagram between a clock signal and a correction signal provided by at least one embodiment of the present disclosure;

fig. 4A illustrates a flowchart of a method of step S30 in fig. 2A according to at least one embodiment of the present disclosure;

fig. 4B is a schematic diagram illustrating another source driver provided by at least one embodiment of the present disclosure acquiring a data signal through a mini-LVDS interface;

fig. 5A and 5B are schematic diagrams illustrating a signal format of a display signal provided by a controller to a source driver according to at least one embodiment of the present disclosure;

fig. 6A illustrates a timing diagram of a trigger signal PSI according to at least one embodiment of the present disclosure;

fig. 6B illustrates a timing diagram of a single mode indication signal according to at least one embodiment of the disclosure;

FIG. 7 is a timing diagram of display sub-signals transmitted in a calibration configuration mode according to at least one embodiment of the present disclosure;

fig. 8 illustrates a schematic block diagram of a signal transmission apparatus provided in at least one embodiment of the present disclosure;

fig. 9 illustrates a schematic block diagram of a source driver provided by at least one embodiment of the present disclosure; and

fig. 10 illustrates a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

Various driving circuits for the display panel generally include a scan driving integrated circuit (also referred to as a gate driver or a G-IC), a data driving integrated circuit (also referred to as a source driver or an SD-IC), a controller, and the like. The controller is mainly used to convert image data signals, control signals, clock signals, and the like received from the outside (e.g., a signal source such as a storage device, a network modem, and the like) into image data signals, gate signals, control signals, clock signals, and the like suitable for a source driver and a gate driver, so as to implement image display driving of the display panel. For example, the Controller may be a Timing Controller (TCON). The source driver is mainly used for receiving the digital signals (display signals or image signals) and control signals and the like provided by the controller, converting the digital signals into corresponding analog gray scale voltage signals through digital-to-analog conversion, and inputting the analog gray scale voltage signals into each row of pixel units of the pixel array of the display panel. The gate driver is mainly used for starting pixel units of each row of the pixel array line by line (or interlaced line), for example, and is matched with the source driver under the action of the control signal, and the required image data signal is input into the corresponding pixel unit for the started pixel unit line, so that the pixel unit can display according to the image data signal.

In the display process of the display panel, the video and the animation are formed by combining a plurality of pictures which are sequentially displayed according to time sequence (for example, the frame rate is 60Hz or 120Hz, and the like), each picture is a frame, namely, one frame of image refers to a complete picture displayed by the display panel. During the display of one frame of image, the gate driver turns on each row of pixel units in the pixel array in turn from the first row to the last row for scanning, and during the scanning, the source driver inputs image data signals required by each row of pixel units into the turned-on pixel units, thereby completing the scanning and display required by one frame of picture. For example, due to the process of the pixel units of the display panel, the display screen needs to be continuously refreshed to obtain a clear and complete display effect with good quality, each time the display screen needs to display one frame of image, and the multiple frames of continuously displayed images form a static screen or a dynamic screen in visual effect.

FIG. 1A is a schematic diagram of a circuit driving system of a display panel. As shown in FIG. 1A, the circuit driving system architecture includes a timing controller TCON, a gate driver G-IC, a source driver SD-IC, and a display panel. The circuit driving system architecture further includes a power management integrated circuit PMIC, a Gamma (Gamma) circuit, a common electrode voltage (Vcom) circuit, and the like.

The input terminal voltage Vin of the power management integrated circuit is, for example, 5V or 12V, and the output voltages include a digital operating voltage DVDD supplied to each IC, an analog voltage AVDD supplied to the Gamma circuit and the Vcom circuit, a gate-on voltage VGH supplied to the gate driver G-IC, a gate-off voltage VGL, and the like. A common electrode voltage (Vcom) circuit is used to supply a common voltage to the pixel array.

The control signals output from the timing controller TCON include control signals supplied to the gate driver G-IC and control signals supplied to the source driver SD-IC. For example, the control signals supplied to the source driver SD-IC include a Start Horizontal (STH) signal at which data transfer starts, a line Clock (CPH) signal, a data transfer control signal Load, and a data polarity inversion signal POL. For example, the control signals supplied to the gate driver G-IC include a frame Start Signal (STV) representing scan on of one frame, a scan Clock signal (CPV), an Enable signal (Enable), and the like.

For example, the input digital interface type of the timing controller TCON may be, for example, a Low-Voltage Differential Signaling (LVDS), an Embedded Display signal (eDP) interface, a V-by-One (Vx 1) interface, and the like. The type of digital interface at the output of the timing controller TCON may be mini-LVDS, for example, for communicating with the source driver SD-IC.

The LVDS interface transmits signals in the form of a pair of lines including a clock line pair and several signal line pairs. For example, the LVDS signal line pair includes three control signals: a field sync signal, a line sync signal, and an enable signal. The mini-LVDS interface is similar to the LVDS interface, and is used for transmitting signals through a differential signal wire pair; unlike the LVDS signal line pair, the signal transmitted by the mini-LVDS signal line pair of the mini-LVDS interface does not contain control signals, which are transmitted through a signal line or a signal differential pair independent of the mini-LVDS signal line pair.

Embodiments are illustrated in this disclosure by taking the example where the source driver and controller communicate over a mini-LVDS interface.

Fig. 1B shows a system architecture diagram of the connection of the timing controller TCON and the source driver.

As shown in fig. 1B, the system architecture includes a timing controller TCON and a plurality of source drivers. The plurality of source drivers includes, for example, a source driver SD #1, a source driver SD #2, and the like, the number of source drivers is related to the physical resolution of the display panel, and may need tens or even hundreds for one display panel. For example, each source driver is connected through a clock signal line pair for transmitting a clock signal, a mini-LVDS signal line pair for transmitting an image data signal, and a control signal line for transmitting a plurality of control signals. The mini-LVDS signal line pair may be 3 pairs of signal lines or 6 pairs of signal lines. The control signal lines may or may not be differential signal pairs. The mini-LVDS signal line and the plurality of control signal lines are independent of each other.

For example, the timing controller TCON is connected to each source driver (e.g., source driver SD #1, SD #2 \8230;) through a LOAD control signal line transmitting a data transfer control signal LOAD, a POL control signal line transmitting a control signal POL, a POL2 control signal line transmitting a control signal POL2, etc., in addition to being connected through a mini-LVDS signal line pair.

Other control signal lines, such as a horizontal DOT inversion (H2 DOT) control signal line, a bias voltage (PWRC) control signal line, a POLC control signal line, etc., may also be included between each source driver and the TCON.

Fig. 1C shows a schematic diagram of a source driver acquiring a data signal through a mini-LVDS interface.

As shown in fig. 1C, the source driver 110 includes a mini-LVDS interface 111. The mini-LVDS interface 111 is connected to a mini-LVDS interface (not shown) of the controller via a plurality of low voltage differential signal line pairs to receive data signals provided by the controller. In embodiments of the present disclosure, the data signal is any signal transmitted over a low voltage differential signal line pair. For example, the data signal may be an image data signal or a configuration data signal.

For example, as shown in fig. 1C, the mini-LVDS interface 111 is connected to a mini-LVDS interface (not shown) of the controller through 3 low-voltage differential signal line pairs, which respectively include a low-voltage differential signal line pair LV0, a low-voltage differential signal line pair LV1, and a low-voltage differential signal line pair LV2.

As shown in fig. 1C, the source driver 110 includes a clock signal interface 112 in addition to the mini-LVDS interface 111. The clock signal interface 112 may also transmit a clock signal through a low voltage differential signal line, for example, the clock signal interface 112 may transmit a clock signal through a clock signal line pair CLK.

As shown in fig. 1C, the source driver 110 further includes a plurality of samplers, such as sampler 0, sampler 1, and sampler 2. The clock signal interface 112 is connected to the plurality of samplers in a one-to-one correspondence via a plurality of clock signal lines, respectively. For example, a clock signal line iCLK0 is connected to the sampler 0 to supply a clock signal to the sampler 0, a clock signal line iCLK1 is connected to the sampler 1 to supply a clock signal to the sampler 1, and a clock signal line iCLK2 is connected to the sampler 2 to supply a clock signal to the sampler 2.

As shown in fig. 1C, the mini-LVDS interface 111 includes a plurality of data channels, which are connected with a plurality of samplers in a one-to-one correspondence. For example, data channel iLV0, data channel iLV1, and data channel iLV2 are connected to sampler 0, sampler 1, and sampler 2, respectively. Each data channel corresponds to one low-voltage differential signal line pair to output data signals on the low-voltage differential signal line pair to the sampler.

Each sampler samples according to a clock signal to obtain a data signal in each data channel. Each sampler outputs a data signal after sampling the data channel. For example, sampler 0 samples data channel iLV0 according to clock signal iCLK0 and outputs data signal iData0[ n:0], sampler 1 samples data channel iLV1 according to clock signal iCLK1 and outputs data signal iData1[ n:0], and sampler 2 samples data channel iLV2 according to clock signal iCLK2 and outputs data signal iData2[ n:0].

As shown in fig. 1C, a resistor, for example, a line resistor, is further included in the transmission path of each clock signal. For example, a resistor R1 is included in a transmission path of the clock signal iCLK0, a resistor R2 is included in a transmission path of the clock signal iCLK1, and a resistor R3 is included in a transmission path of the clock signal iCLK2. In the present disclosure, iCLK0, iCLK1 and iCLK2 represent both the clock signal lines and the clock signals transmitted by the clock signal lines.

As shown in fig. 1C, each sampler is connected to the same clock signal interface 112, and due to the different positions of the samplers and the like in the circuit, the lengths of the clock signal line iCLK0, the clock signal line iCLK1 and the clock signal line iCLK2 are different, which results in different delays of the clock signal reaching each sampler.

FIG. 1D shows a timing diagram of a data signal and a clock signal.

Assuming that the lengths of the signal lines of the data channels are the same, that is, the lengths of the signal lines of the data channels iLV0, iLV1 and iLV2 are the same, the delays of the data signals transmitted by the channels reaching the samplers are the same, so that the time sequences of the data signals sampled by the samplers for the data channels are the same. In fig. 1D, timings of data signals sampled for the data channels iLV0, iLV1, and iLV2 are collectively represented by iLVx.

In the examples of fig. 1C and 1D, the length of the clock signal line iCLK0 is smaller than the length of the clock signal line iCLK1, and the length of the clock signal line iCLK1 is smaller than the length of the clock signal line iCLK2. Therefore, with respect to the data signal iLVx, which is normally transmitted for each data, the delay of the clock signal iCLK0 received by the sampler 0 is smaller than the delay of the clock signal iCLK1 received by the sampler 1, and the delay of the clock signal iCLK1 received by the sampler 1 is smaller than the delay of the clock signal iCLK2 received by the sampler 2.

It should be noted that, although the present disclosure takes 3 low voltage differential signal line pairs, 3 data lanes and 3 samplers as an example, the present disclosure does not limit the number of low voltage differential signal line pairs, the number of data lanes and the number of samplers, and may also be, for example, 6 low voltage differential signal line pairs, 6 data lanes and 6 samplers.

As shown in fig. 1D, there is a timing delay between the clock signal and the data signal, which causes transmission of the image data signal or the configuration data signal to be unstable, and it is difficult to increase the transmission frequency of the low voltage differential signal interface.

To this end, an embodiment of the present disclosure provides a signal transmission method, which is applied to a source driver, where the source driver is communicatively connected to a controller through a low voltage differential signal interface, and the method includes: acquiring a clock signal and a correction signal provided by a controller; determining a timing offset value between the clock signal and the correction signal according to the clock signal and the correction signal; and adjusting a timing relationship between the clock signal and the correction signal based on the timing offset value using a delay unit disposed in a clock path of the clock signal or in a data path of the correction signal. According to the signal transmission method, the time sequence relation between the clock signal and the correction signal is adjusted through the delay unit, in the process of transmitting the data signal (such as an image data signal) between the controller and the source driver, the delay between the clock signal and the data signal is relieved, the data signal is ensured to be transmitted accurately, and the communication frequency between the source driver and the controller is improved. The correction signal is, for example, a configuration data signal for correcting the clock signal and the data signal.

Fig. 2A illustrates a flow chart of a signal transmission method according to at least one embodiment of the present disclosure.

As shown in fig. 2A, the signal transmission method includes steps S10 to S30. The signal transmission method is performed by the source driver 110 shown in fig. 1C, for example.

Step S10: the clock signal and the correction signal provided by the controller are acquired.

Step S20: a timing offset value between the clock signal and the correction signal is determined based on the clock signal and the correction signal.

Step S30: and adjusting the timing relation between the clock signal and the correction signal by using a delay unit based on the timing offset value, wherein the delay unit is arranged in a clock path of the clock signal or a data path of the correction signal.

In the display apparatus, the signal transmission method may be performed, for example, before the controller supplies the image data signal for display to the source driver. The signal transmission method enables the data signal to be stably transmitted between the controller and the source driver and is beneficial to improving the frequency of data signal transmission between the controller and the source driver by correcting the timing relation between the clock signal and the correction signal in advance.

For step S10, for example, in the example of fig. 1C, the respective samplers in the source driver 110 acquire the clock signal and the correction signal, respectively.

The clock signal is, for example, a clock signal supplied from a clock source by the controller to the clock signal interface 112 of the source driver through the clock signal line pair, and is supplied from the clock signal interface 112 to the respective samplers via the respective clock signal lines (the clock signal line iCLK0, the clock signal line iCLK1, and the clock signal line iCLK 2), respectively. Due to the delays of the clock signals on the clock signal line iCLK0, the clock signal line iCLK1 and the clock signal line iCLK2, the sampler 0, the sampler 1 and the sampler 2 respectively obtain the clock signal iCLK0, the clock signal iCLK1 and the clock signal iCLK2 shown in fig. 1D.

The correction signal is a signal for delay correction of the clock signal, and the correction signal may be in any form. For example, the correction signal may be a signal different from the image data. The correction signal may be, for example, a signal in which 0 and 1 alternate. For example, "0" indicates a low level signal, and "1" indicates a high level signal.

For example, in the example of fig. 1C, iLVx is a correction signal. For example, the mini-LVDS interface 111 receives the 0 and 1 alternating correction signals provided by the controller, and the mini-LVDS interface 111 provides the correction signals to the respective samplers through, for example, 3 data channels. Each sampler samples each data channel to obtain a correction signal, where the correction signal may be any one of a signal obtained by sampling the data channel iLV0 by the sampler 0, a signal obtained by sampling the data channel iLV1 by the sampler 1, and a signal obtained by sampling the data channel iLV2 by the sampler 2. For step S20, the timing offset value is, for example, a relative concept. For example, the timing offset value may be a delay of the clock signal relative to the correction signal, or a delay of the correction signal relative to the clock signal.

For example, the timing offset value is an offset value between the sampling instant of the clock signal and a reference instant of the correction signal during the first signal.

For example, the correction signal is a signal in which a first signal, which may be, for example, a high-level signal to represent a digital signal "1", and a second signal, which may be, for example, a low-level signal to represent a digital signal "0", are alternated. The first signal period is, for example, a period in which the correction signal is at a high level.

The sampling instant of the clock signal may be a rising or falling edge of the clock signal. In the present disclosure, the sampling time is taken as the rising edge of the clock signal as an example to explain the embodiment.

The reference time instant may be any time instant during the first signal. For example, the reference time is an intermediate time of the first signal period. By using the middle time of the first signal as a reference time to align the sampling time (e.g. rising edge) of the clock signal with this time, it is possible to guarantee sufficient setup time and hold time, and thus guarantee sampling stability.

In step S20, in some embodiments of the present disclosure, for example, a time length of a time corresponding to a rising edge of the clock signal from the reference time may be calculated, and a multiple of the time length and 2 may be used as the timing offset value.

For example, in the timing diagram shown in fig. 1D, with the middle time of the first signal period as the reference time, the delays between the reference time T and the times corresponding to the rising edges of the clock signals iCLK0, iCLK1 and iCLK2 are respectively the time length Δ T1, the time length Δ T2 and the time length Δ T3, and then the time lengths Δ T1/2, Δ T2/2 and Δ T3/2 are respectively used as the timing offset values of the clock signals iCLK0, iCLK1 and iCLK2 relative to the correction signal. In the example of fig. 1D, the time length Δ t1 is equal to 0.

The rising edge of the clock signal may correspond to a time that is earlier or later than the reference time. In the disclosure, for example, if the time corresponding to the rising edge of the clock signal is earlier than the reference time, the delay time is a positive value, that is, the timing deviation value is a positive value; if the time corresponding to the rising edge of the clock signal is later than the reference time, the delay is a negative value, that is, the timing deviation value is a negative value.

Fig. 3A and 3B below illustrate another embodiment of determining timing offset values, please refer to the description of fig. 3A and 3B below.

For step S30, the delay between the clock signal and the correction signal is reduced by a delay unit, for example, based on the timing offset value.

In the embodiments of the present disclosure, for example, a delay unit is disposed in the clock path of the source driver to adjust the timing of the clock signal relative to the correction signal, so as to alleviate the delay of the clock signal relative to the correction signal. For another example, a delay unit is disposed in the data path of the source driver to adjust the timing of the clock signal relative to the correction signal, so as to alleviate the delay between the clock signal and the correction signal.

In some embodiments of the present disclosure, the delay unit may be, for example, a delay circuit designed by those skilled in the art to delay a signal for a period of time. For example, the delay circuit includes a capacitor, a resistor, a buffer, and the like.

For example, P (P is an integer greater than 0) delay units are preset in each clock path, and if the timing offset value is a negative value, which indicates that the time corresponding to the rising edge of the clock signal is later than the reference time, the number of the delay units is appropriately reduced, for example, the number of the delay units is reduced to P-1 (in this case, P is an integer greater than 1, for example); if the timing deviation value is a positive value, it indicates that the time corresponding to the rising edge of the clock signal is earlier than the reference time, and the number of the delay units is appropriately increased, for example, the number of the delay units is decreased to P + 1.

The number of the delay units to be increased or decreased can be determined by those skilled in the art according to the delay effect of the delay units and the timing offset value.

For example, the delay time length of a single delay unit is determined, and thus the ratio of the timing offset value to the delay time length is used as the number of delay units.

For another example, the number of delay cells may be increased or decreased one by one until the number of delay cells with the minimum timing offset value is found.

Fig. 2B is a schematic diagram illustrating a source driver acquiring a data signal through a mini-LVDS interface according to at least one embodiment of the disclosure.

As shown in fig. 2B, the source driver 120 includes a plurality of delay cells, e.g., 2 or more delay cells, on each clock path. The number of delay units used in each clock path is adjusted according to the timing offset value, thereby adjusting the timing relationship of the clock signal and the correction signal.

In the example of fig. 2B, except that a plurality of delay units are added to each clock path, other structures are similar to the structure of fig. 1C and are not described again. In some embodiments of the present disclosure, the number of delay elements in the plurality of clock paths may or may not be the same.

Fig. 3A illustrates a flowchart of a method of step S20 in fig. 2A according to at least one embodiment of the present disclosure.

As shown in fig. 3A, the method includes steps S21 to S22.

Step S21: a first time length from the sampling time to a first transition edge and a second time length to a second transition edge of the correction signal are obtained.

Step S22: a timing offset value between the clock signal and the correction signal is determined based on the first length of time and the second length of time.

In this embodiment, the first transition edge is a transition edge where the correction signal transitions from the second signal to the first signal, and the second transition edge is a transition edge where the correction signal transitions from the first signal to the second signal.

According to the method, the timing deviation value is obtained by taking the first jumping edge and the second jumping edge as references, and the accuracy of the timing deviation value can be improved.

The method of FIG. 3A described above is described below in conjunction with FIG. 3B. Fig. 3B illustrates a timing diagram between a clock signal and a correction signal according to at least one embodiment of the disclosure.

As shown in fig. 3B, the timing diagram includes a clock signal iCLK0 and a correction signal iLV0. For example, the correction signal iLV0 is at the middle timing of the digital signal "1" as the reference timing.

The transition edge Y1 is an example of a first transition edge, and the transition edge Y1 is a transition edge where the correction signal changes from "0" to "1"; transition edge Y2 is an example of a second transition edge, and transition edge Y2 is a transition edge where the correction signal transitions from "1" to "0". That is, the transition edge Y1 is a rising edge of the correction signal, and the transition edge Y2 is a falling edge of the correction signal.

In step S21, the sampling timing is, for example, a timing corresponding to a rising edge Y3 of the clock signal iCLK 0. And acquiring a first time length between the time corresponding to the rising edge Y3 and the jump edge Y1 and a second time length between the time corresponding to the jump edge Y2.

In some embodiments of the present disclosure, the correction signal is counted positive, for example from the sampling instant, to the second transition edge, the second length of time being represented by a positive count; the correction signal is counted down from the sampling instant to a first transition edge, the first time length being represented by the count down. The method for acquiring the first time length and the second time length is easy to implement, efficient and high in accuracy.

For example, in the example of fig. 3B, counting the correction signal positive from the rising edge Y3 to the transition edge Y2 yields a positive count of +3, and the second time length is denoted by + 3; the correction signal is counted down from the rising edge Y3 to the transition edge Y1 to get a count-5 to represent the first time duration-5.

In this embodiment, step S22 takes, for example, the average of the up count and the down count as the timing offset value. For example, [ +3+ (-5) ]/2= -1, and therefore-1 is used as the timing offset value between the clock signal iCLK0 and the reference instant of the correction signal iLV0.

In other embodiments of the present disclosure, one skilled in the art may assign corresponding weights to the positive and negative counts as needed, thereby taking a weighted average of the positive and negative counts as the timing offset value.

Fig. 4A illustrates a flowchart of a method of step S30 in fig. 2A according to at least one embodiment of the present disclosure.

As shown in fig. 4A, the method may include steps S31 to S32.

Step S31: and determining the number of delay units according to the time sequence offset value.

Step S32: the number of delay units in the clock path is adjusted or the number of delay units in the data path is adjusted.

For step S31, the number of delay units is determined, for example, by looking up a correspondence table between the timing offset value and the number of delay units.

In other embodiments of the present disclosure, the number of delay units may be determined, for example, by increasing or decreasing the delay units according to a preset gradient based on the currently used delay units according to the timing offset value.

For example, when the clock path includes 5 delay cells, the timing offset value between the clock signal and the correction signal is a negative value, and the number of delay cells is appropriately reduced. For example, the predetermined gradient is 1 delay unit, and if the timing offset value is-1, the delay units are reduced by 1, so that the number of delay units is adjusted to 4. Similarly, if the timing offset value between the clock signal and the correction signal is a positive value, the number of delay units is increased appropriately.

For step S32, for example, if the number of delay units is adjusted to 4, 4 delay units are selected from 5 delay units to be used in the clock path.

In some embodiments of the present disclosure, the delay time lengths of the plurality of delay units may be the same or different. If the delay time lengths of the delay units are different, a proper delay unit can be selected to be used in the clock path according to the time sequence deviation value. For example, if the timing offset value is large, the delay unit with a large delay time length may be selected in the clock path, and if the timing offset value is small, the delay unit with a small delay time length may be selected in the clock path. Also, a plurality of delay units of different delay time lengths can be freely combined to minimize the timing offset value.

The embodiment flexibly and conveniently compensates for the timing deviation by adjusting the number of the delay units, thereby obtaining the optimal sampling time.

In other embodiments of the present disclosure, a delay unit may be disposed in the data path.

Fig. 4B is a schematic diagram illustrating another source driver provided by at least one embodiment of the present disclosure acquiring a data signal through a mini-LVDS interface.

As shown in fig. 4B, compared to the source driver 120 in fig. 2B, except that the plurality of delay units are respectively disposed in the data path instead of the clock path, the source driver 130 is the same as the source driver 120, and is not repeated.

As shown in fig. 4B, a plurality of delay units are respectively provided at each data path. For example, a plurality of delay units are respectively disposed in the data paths between the respective low voltage differential signal pairs and the respective samplers. For example, a plurality of delay units 401 are disposed in the data channel iLV0 between the low voltage differential signal pair LV0 and the sampler 0.

The number of the plurality of delay units 401, the plurality of delay units 402 and the plurality of delay units 403 may be the same or different.

For example, the number of delay cells in the data path is determined based on the timing offset value. For example, if the timing offset value is a positive value, the number of delay units in the data path is decreased; if the timing deviation value is negative, the number of delay units is increased. For example, if the timing offset values of the correction signal iLV1 and the clock signal iCLK1 on the data channel iLV1 are positive values, the number of delay units in the plurality of delay units 402 is decreased. If the timing offset values of the correction signal on the data path iLV2 and the clock signal iCLK2 are positive values, the number of delay units in the plurality of delay units 403 is decreased.

The method for determining the number of delay units in each data path is similar to the method for determining the number of delay units in the clock path, and is not described again.

In other embodiments of the disclosure, delay units may be disposed in both the data path and the clock path, and the number of delay units in the data path or the number of delay units in the clock path may be adjusted according to the timing offset value.

As shown in fig. 1B, the mini-LVDS signal line pair is used only for transmitting image data signals and is not used for transmitting control signals such as polarity inversion configuration information, data transmission control information, and the like. Therefore, there are a plurality of signal lines and a plurality of signal line interfaces between the timing controller and the source drivers, which results in occupying a large signal routing space in the display panel, and this problem is more pronounced particularly when the number of source drivers is large. Some commonly used control functions cannot be flexibly embedded in the source driver if the available signal routing space in the display panel is not sufficient to accommodate the plurality of data lines.

In other system architectures of the present disclosure, the connection between the timing controller TCON and the source driver may be made only through the mini-LVDS signal line pair, the clock signal line pair, the LOAD control signal line and the POL control signal line. In the system architecture, the mini-LVDS transmits a configuration data signal, such as a control signal POL2, a horizontal dot inversion control signal, a bias voltage control signal, etc., which controls the source driver, in addition to the image data signal. The system architecture can multiplex low voltage differential signal interfaces for providing both image data and configuration data to the source driver, thereby reducing the number of interfaces for signal transmission, saving cost, and ensuring that multiple control functions can be flexibly embedded in the source driver. The image data signal is a signal for image display, and includes, for example, RGB (red, green, and blue) data. The configuration data signal is used to configure the source driver. In the system architecture, the controller and the source driver can transmit the display signal through at least two modes.

In some embodiments of the present disclosure, the controller provides the display signal according to at least two modes, the display signal including a plurality of display sub-signals, the at least two modes respectively providing a plurality of display sub-signals, each display sub-signal including a mode identification signal. In this embodiment, step S20 in fig. 2A includes: in response to the pattern recognition signal being a correction pattern signal, determining that the controller provides the display sub-signal in the correction configuration mode and that the display sub-signal comprises the correction signal; and determining a timing offset value between the clock signal and the correction signal based on the clock signal and the correction signal.

In an embodiment of the present disclosure, the controller may be a Timing Controller (TCON). This embodiment is applied to the system architecture in which the timing controller TCON and the source driver may be connected only through the mini-LVDS signal line pair, the clock signal line pair, the LOAD control signal line, and the POL control signal line as described above. That is, the mini-LVDS transmits a configuration data signal, such as a control signal POL2, a horizontal dot inversion control signal, a bias voltage control signal, etc., which controls the source driver, in addition to the image data signal. The system architecture can multiplex low voltage differential signal interfaces for providing both image data signals and configuration data signals to the source driver, thereby reducing the number of interfaces for signal transmission, saving cost, and ensuring that multiple control functions can be flexibly embedded in the source driver.

In some embodiments of the present disclosure, the at least two modes include a correction configuration mode. The at least two modes may include a frame configuration mode or a row configuration mode in addition to the correction configuration mode. Each mode provides at least one display sub-signal. Each display sub-signal includes a pattern recognition signal to indicate the pattern to which the display sub-signal belongs. The pattern recognition signal is used to distinguish whether the display sub-signal is provided by the controller in the row configuration mode, the frame configuration mode, or the correction configuration mode. For example, the pattern recognition signal of the row arrangement pattern is a pattern recognition signal a, the pattern recognition signal of the frame arrangement pattern is a pattern recognition signal B, and the pattern recognition signal of the correction arrangement pattern is a pattern recognition signal C (i.e., a correction pattern signal).

The display sub-signal provided by the correction configuration mode comprises the correction signal besides the correction mode signal. The correction signal is, for example, a signal in which "0" and "1" are alternated as described above.

For example, the source driver first receives the pattern recognition signal, determines that the controller provides the display sub-signal in the correction configuration mode if the pattern recognition signal is the pattern recognition signal C, and determines that a signal received after correcting the pattern signal is a correction signal.

The display signals may include, for example, image data signals and configuration data signals. For example, the configuration data signal may be generated by a timing control block in the timing controller. The configuration data signal is used to configure the source driver such that the source driver processes the image data signal according to the configuration data signal. The configuration data signal includes a display sub-signal provided by the correction configuration mode, and may further include a row configuration data provided by the row configuration mode or a display sub-signal provided by the frame configuration mode.

The display sub-signal provided by the row configuration mode comprises the row configuration data and the row image data. The row configuration mode configures the source drivers for display of image data for a row of pixels. The line image data is, for example, RGB data corresponding to the line in the pixel array. The row configuration data is used to configure the source driver so that the source driver outputs the row image data and timing control signals, etc. to the row of pixels in response to the row configuration data.

The display sub-signals provided by the frame configuration mode are used to configure the source driver for the display of a frame of image. The frame configuration data is used, for example, to configure the source driver so that the source driver outputs a control signal for the frame image. The frame configuration data may include, for example, a Gamma (Gamma) setting signal, an Amplification (AMP) offset control signal, a shift direction selection signal, and the like.

Fig. 5A and 5B are schematic signal formats of a display signal provided by a controller to a source driver according to at least one embodiment of the present disclosure.

As shown in fig. 5A, in one frame display period (including an image display period and a vertical blanking period), the display signal includes a plurality of display sub-signals 301 supplied in a line configuration mode, a display sub-signal 302 supplied in a frame configuration mode, and a display sub-signal 303 supplied in a correction configuration mode.

In some embodiments of the present disclosure, the frame configuration mode and the correction configuration mode are during vertical blanking. The frame configuration mode and the correction configuration mode enable the source driver to perform frame configuration and timing correction in the vertical blanking period to prepare for display of the next image frame during the vertical blanking period, and the frame configuration and timing correction are performed during the vertical blanking period, so that time is saved and display efficiency is improved.

For example, the plurality of display sub-signals 301 are provided in a row configuration mode during image display, the display sub-signals 302 are provided in a frame configuration mode during vertical blanking and the display sub-signals 303 are provided in a correction configuration mode.

As shown in fig. 5A, providing display signals to the source driver in at least two modes through the low voltage differential signal interface during one frame display period includes: and sequentially providing the display signals to the source driver in at least two modes by using the low voltage differential signal interface in one frame display period, and sequentially providing one or more display sub-signals to the source driver by using the low voltage differential signal interface for each mode.

For example, in the example of fig. 5A, the plurality of display sub-signals 301 are provided to the source driver in the row configuration mode, the display sub-signals 302 are provided to the source driver in the frame configuration mode, and the display sub-signals 303 are provided to the source driver in the correction configuration mode using the low voltage differential signaling interface. For example, for a row configuration mode comprising a plurality of display sub-signals 301, the plurality of display sub-signals 301 are provided to the source driver in sequence using a low voltage differential signal interface. That is, in the example of fig. 5A, the plurality of display sub-signals 301 are provided to the source driver by using the low voltage differential signal interface, the display sub-signals 302 are provided to the source driver by using the low voltage differential signal interface, and the display sub-signals 303 are provided to the source driver by using the low voltage differential signal interface.

As shown in fig. 5A, each display sub-signal 301 provided in the line arrangement mode includes line data LPC and image data (e.g., RGB data). As shown in fig. 5B, the line data LPC includes a pattern recognition signal a and line configuration data. For example, the mode identification signal a includes a RESET signal RESET and a row mode Start signal LPC Start. For example, the row mode start signal may be a logic inactive level, e.g., "000". For the pattern identification signal and the row configuration data of the row configuration pattern, refer to the above description.

As shown in fig. 5A, each display sub-signal 302 provided in the frame configuration mode includes frame data FPC and invalid data IDLE0 and IDLE1. In an embodiment of the present disclosure, IDLE0 and IDLE1 are both logic inactive levels, for example. As shown in fig. 5B, the frame data FPC includes a pattern recognition signal B and frame configuration data. For example, the pattern recognition signal B of the frame data FPC is a RESET signal RESET and a frame pattern Start signal FPC Start. For example, the frame mode start signal may be different from the row mode start signal, e.g., a logic active level such as "111", to distinguish between the frame configuration mode and the row configuration mode. For the pattern recognition signal and the frame configuration data of the frame configuration pattern, refer to the above description.

As shown in fig. 5A, the frame configuration mode includes a power consumption control sub-mode. The display sub-signal 302 provided in the frame configuration mode includes a low power consumption signal 312 provided to the source driver in the power consumption control sub-mode, and the low power consumption signal 312 includes, for example, invalid data IDLE0 and invalid data IDLE1. During the period that the controller provides the invalid data IDLE0 and the invalid data IDLE1 to the source driver in the power consumption control sub-mode, at least part of the circuit modules in the source driver are in a power-down state to save power consumption. In the example of fig. 5A, before the invalid data IDLE0 is supplied to the source driver in the power consumption control sub-mode, the controller supplies the trigger signal PSI to the source driver again to instruct the source driver to enter the low power consumption operation state.

As shown in fig. 5A, each display sub-signal 303 provided in the correction configuration mode includes correction data ASC. As shown in fig. 5B, the correction data ASC includes a pattern recognition signal C and a correction signal. The pattern recognition signal C may be, for example, a logic inactive level. For the calibration parameters, refer to the above description.

As shown in fig. 5A, after the display signal for one frame display period is transmitted to the source driver, the transmission of the display signal for the next frame display period to the source driver is continued.

As shown in fig. 5A, the display sub-signals provided by each mode further include a trigger signal for instructing the source driver to perform a transmission operation according to the at least two modes. For example, before each display sub-signal is supplied to the source driver, a trigger signal is supplied to the source driver to inform the source driver to perform a transmission operation for at least two modes.

In some embodiments of the present disclosure, the setting of the timing relationship between the data transfer control signal and the data polarity inversion control signal comprises: the first transition edge of the data polarity inversion control signal is later than the second transition edge of the data transmission control signal, and a first transition state of the data polarity inversion control signal after the first transition edge is at least partially time coincident with a second transition state of the data transmission control signal after the second transition edge.

The data polarity inversion control signal controls the polarity inversion of the data signal output by the source driver through the switching of high and low levels so as to realize the alternating current driving of the liquid crystal. The data transfer control signal is used to latch data and a data polarity inversion signal input to the source driver at a rising edge, and the falling edge controls the release of the data to the panel.

In some embodiments of the present disclosure, the controller may transmit the display signal to the source driver through a single mode in addition to transmitting the display signal to the source driver in at least two modes. In this embodiment, by notifying the source driver of the at least two modes of the transfer operation performed by the trigger signal, compatibility of the source driver and the controller with other transfer operations than the at least two modes of the transfer operation is facilitated, providing compatibility. For example, a single mode transfer operation may be compatibly performed between the controller and the source driver in addition to the transfer operation through at least two modes. For example, the display signals that may be transmitted in at least two modes conform to a first signaling protocol, and the display signals that may also be transmitted to the source driver in a single mode conform to a second signaling protocol. If the controller and the source driver execute the transmission operation of at least two modes, the controller firstly provides a trigger signal to the source driver as an indication signal of the transmission operation of at least two modes; if the controller and the source driver execute the single-mode transmission operation, the controller firstly provides a single-mode indication signal different from the trigger signal to the source driver. The second signal transmission protocol may be some other protocol than the first signal transmission protocol, for example, some transmission protocols in the related art. The signal line multiplexing can be realized by setting the trigger signal, so that the chip has multiple functions, and the difficulty of popularization of the first signal transmission protocol is reduced.

Fig. 6A illustrates a timing diagram of a trigger signal PSI according to at least one embodiment of the present disclosure.

As shown in fig. 6A, the trigger signal PSI includes the data transmission control signal LOAD and the data polarity inversion control signal POL, and a first transition edge (e.g., a rising edge) of the data polarity inversion control signal POL is later than a second transition edge (e.g., a rising edge) of the data transmission control signal LOAD, and a first transition state (e.g., a high state) of the data polarity inversion control signal POL after the first transition edge is at least partially time-coincident with a second transition state (e.g., a high state) of the data transmission control signal LOAD after the second transition edge.

In some embodiments of the present disclosure, for example, the driver program in the controller may be adjusted such that the data polarity inversion control signal POL is later than the data transmission control signal LOAD by a time length tS2 in the same period of the data transmission control signal LOAD and the data polarity inversion control signal POL, so that the rising edge of the data polarity inversion control signal POL is later than the rising edge of the data transmission control signal LOAD. The data polarity inversion control signal POL and the data transmission control signal LOAD are simultaneously in a high state for a time length tH2 after the rising edge.

Fig. 6B illustrates a timing diagram of a single mode indication signal according to at least one embodiment of the disclosure.

As shown in fig. 6B, the single mode indication signal includes the data transmission control signal LOAD 'and the data polarity inversion control signal POL', and a first transition edge (e.g., a rising edge) of the data polarity inversion control signal POL 'is earlier than a second transition edge (e.g., a rising edge) of the data transmission control signal LOAD', and a first transition state (e.g., a high state) of the data polarity inversion control signal POL 'after the first transition edge is at least partially time-coincident with a second transition state (e.g., a high state) of the data transmission control signal LOAD' after the second transition edge.

In some embodiments of the present disclosure, for example, the driver program in the controller may be adjusted such that the data polarity inversion control signal POL 'is earlier than the data transmission control signal LOAD' by the time length tS1 in the same period of the data transmission control signal LOAD 'and the data polarity inversion control signal POL', so that the rising edge of the data polarity inversion control signal POL 'is earlier than the rising edge of the data transmission control signal LOAD'.

The embodiment of fig. 6A and 6B can distinguish between the single mode transmission operation and the at least two modes of transmission operation by the data transmission control signal and the data polarity inversion control signal, and is easy to implement without modifying the hardware circuit of the interface. In this way, the same set of controller and source driver can selectively implement the first signaling protocol or the second signaling protocol as needed without providing a set of controller and source driver for the first signaling protocol and the second signaling protocol, respectively, and thus the cost of design, development, manufacturing, and management can be reduced for the supplier.

The controller and the source driver may be connected through a mini-LVDS signal line, a POL signal line and a LOAD signal line, and thus other lines such as a POL2 control signal line and a POLC control signal line, a horizontal DOT inversion (H2 DOT) control signal line, a bias voltage (PWRC) control signal line, etc. may be omitted entirely or partially. Therefore, this example can not only reduce the number of signal lines between the controller and the source driver, but also inform the source driver which kind of transfer operation is performed to be compatible with the transfer operation of the single mode.

Fig. 7 is a timing diagram of display sub-signals transmitted in a correct configuration mode according to at least one embodiment of the present disclosure.

As shown in fig. 7, the data polarity inversion control signal POL and the data transmission control signal LOAD are included in the timing diagram, and a first transition edge (e.g., rising edge) of the data polarity inversion control signal POL is later than a second transition edge (e.g., rising edge) of the data transmission control signal LOAD, and a first transition state (e.g., high state) of the data polarity inversion control signal POL after the first transition edge coincides at least partially with a second transition state (e.g., high state) of the data transmission control signal LOAD after the second transition edge, so that the controller provides a trigger signal to the source driver. In this embodiment, the controller provides two trigger signals to the source driver in succession, and providing the trigger signals multiple times can at least partially avoid noise interference, improving the accuracy of the source driver in identifying the transmission mode.

In this embodiment, the source driver determines to perform at least two modes of transmission operation in response to receiving two trigger signals. After the source driver receives the two trigger signals, it continues to receive the data signal, determines that the controller provides the data signal in the calibration configuration mode if the data signal is a calibration mode signal tASC (e.g., a logic inactive level "0"), and determines that the data signal received after the calibration mode signal is the calibration signal.

In this embodiment, a power supply (e.g., voltage source) VDD supplies power to the source driver.

In some embodiments of the present disclosure, the controller provides the display signals to the source driver through the low voltage differential signal interface in a row configuration mode, a frame configuration mode, and a correction configuration mode in sequence.

In some embodiments of the present disclosure, for example, the signal transmission method is applied to a display device. After the display device enters an operating state, the controller provides a plurality of display sub-signals to the source driver in sequence according to a row configuration mode, a frame configuration mode, and a correction configuration mode. In the process of starting up the display device, the controller provides the display sub-signals and the display sub-signals provided by the frame configuration mode in sequence according to the correction configuration mode.

During the startup of the display device, the controller provides the source driver with a correction signal to determine the number of delay units in the clock path, and then provides the source driver with frame configuration data to prepare the controller for image display in advance. During the power-on of the display device, no image display is performed, and thus it is not necessary to provide the display sub-signals to the source driver in the row configuration mode. After the source driver is configured according to the correction parameters and configured according to the frame configuration data, the display apparatus enters an operating state.

For example, in an operating state of the display device, the controller first configures data and line image data to the source driver lines in a line configuration mode so that the display device sequentially displays image data for each line to display a complete image for one frame. After the display device displays a complete image of one frame, a vertical blank period is entered. During the vertical blanking period, the controller first provides frame configuration data to the source driver in a frame configuration mode, so that the source driver performs frame configuration. For example, the source driver enters a low power consumption state according to the frame configuration data. Thereafter, the controller provides the display sub-signals to the source driver in the correction configuration mode.

Fig. 8 illustrates a schematic block diagram of a signal transmission apparatus 800 according to at least one embodiment of the present disclosure. The signal transmission apparatus 800 is applied to a source driver, and the source driver is communicatively connected to a controller by a low voltage differential signal interface.

For example, as shown in fig. 8, the signal transmission apparatus 800 includes an acquisition unit 810, a determination unit 820, and an adjustment unit 830.

The acquisition unit 810 is configured to acquire a clock signal and a correction signal provided by the controller.

The acquisition unit 810 may perform, for example, step S10 described in fig. 2A.

The determining unit 820 is configured to determine a timing offset value between the clock signal and the correction signal according to the clock signal and the correction signal.

The determination unit 820 may perform, for example, step S20 described in fig. 2A.

The adjusting unit 830 is configured to adjust a timing relationship between the clock signal and the correction signal based on the timing offset value by using a delay unit, wherein the delay unit is disposed in a clock path of the clock signal or a data path of the correction signal.

The adjusting unit 830 may, for example, perform step S30 described in fig. 2A.

The apparatus 800 can alleviate the delay between the clock signal and the image data signal in the process of transmitting the image data signal between the controller and the source driver, ensure the accurate transmission of the image data signal, and is beneficial to improving the communication frequency between the source driver and the controller.

Fig. 9 illustrates a schematic block diagram of a source driver 900 provided in at least one embodiment of the present disclosure. The source driver 900 is communicatively coupled to the controller by way of a low voltage differential signaling interface.

For example, as shown in fig. 9, the source driver 900 includes a processing circuit 910 and a delay circuit 920.

The processing circuit 910 is configured to obtain a clock signal and a correction signal provided by the controller, and determine a timing offset value between the clock signal and the correction signal according to the clock signal and the correction signal.

The processing circuit 910 may, for example, perform steps S10 and S20 described in fig. 2A.

The delay circuit 920 is disposed in a clock path of the clock signal or a data path of the correction signal and configured to adjust a timing relationship between the clock signal and the correction signal based on the timing offset value.

The delay circuit 920 may, for example, perform step S30 described in fig. 2A.

The source driver 900 can alleviate the delay between the clock signal and the image data signal in the process of transmitting the data signal between the controller and the source driver, ensure the accurate transmission of the image data signal, and is beneficial to improving the communication frequency between the source driver and the controller.

For example, the obtaining unit 810, the determining unit 820 and the adjusting unit 830 may be hardware, software, firmware and any feasible combination thereof. For example, the obtaining unit 810, the determining unit 820 and the adjusting unit 830 may be dedicated or general circuits, chips or devices, and may also be a combination of a processor and a memory. The embodiments of the present disclosure are not limited in this regard to the specific implementation forms of the above units.

For example, the processing circuit 910 and the delay circuit 920 may be hardware or firmware, and any feasible combination thereof. The processing circuit 910 and the delay circuit 920 may be dedicated or general circuits, chips. The embodiments of the present disclosure are not limited in this regard to the specific implementation forms of the above units.

It should be noted that, in the embodiment of the present disclosure, each unit of the signal transmission apparatus 800 and the source driver 900 corresponds to each step of the foregoing signal transmission method, and for specific functions of the signal transmission apparatus 800 and the source driver 900, reference may be made to the related description about the signal transmission method, and details are not repeated here. The components and structures of the signal transmission apparatus 800 shown in fig. 8 and the source driver 900 shown in fig. 9 are merely exemplary and not restrictive, and the signal transmission apparatus 800 and the source driver 900 may further include other components and structures as necessary.

Fig. 10 illustrates a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure.

As shown in fig. 10, the electronic device 1000 includes a controller 1010, a source driver 1020, and a display panel 1030.

The controller 1010 is configured to provide a display signal to the source driver 1020. For an introduction of the display signal, reference is made to the above description.

The source driver 1020, for example, performs the signaling method described above in fig. 2A. The source driver 1020 and the controller 1010 are connected through a low voltage differential signal interface to receive a clock signal, a display signal, and the like. The display panel 1030 is, for example, a liquid crystal display panel, and receives a driving signal (i.e., a gray scale voltage signal) provided from the source driver 1020 to display an image, the driving signal being generated by the source driver based on the display signal.

The electronic device 1000 may be various electronic devices with an image display function, including but not limited to a smart phone, a tablet computer, a notebook computer, a display, a television, and the like.

The electronic device 1000 is used for alleviating the time delay between the clock signal and the data signal in the process of transmitting the data signal between the controller and the source driver, ensuring the accurate transmission of the data signal, and being beneficial to improving the communication frequency between the source driver and the controller.

Although as mentioned above, there are several points to be explained:

(1) The drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to common designs.

(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be subject to the scope of the claims.

Claims (16)

1. A signal transmission method is applied to a source driver, wherein the source driver is in communication connection with a controller through a low-voltage differential signal interface mode, and the method comprises the following steps:

acquiring a clock signal and a correction signal provided by the controller;

determining a timing offset value between the clock signal and the correction signal according to the clock signal and the correction signal; and

and adjusting the timing relation between the clock signal and the correction signal by using a delay unit based on the timing deviation value, wherein the delay unit is arranged in a clock path of the clock signal or a data path of the correction signal.

2. The method of claim 1, wherein the timing offset value is an offset value between a sampling instant of the clock signal and a reference instant of the correction signal during the first signal.

3. The method of claim 1 or 2, wherein determining the timing offset value between the clock signal and the correction signal from the clock signal and the correction signal comprises:

acquiring a first time length from the sampling time to a first transition edge of the correction signal and a second time length from the sampling time to a second transition edge of the correction signal; and

determining the timing offset value between the clock signal and the correction signal based on the first length of time and the second length of time,

wherein the first transition edge is a transition edge where the correction signal transitions from the second signal to the first signal, and the second transition edge is a transition edge where the correction signal transitions from the first signal to the second signal.

4. The method of claim 3, wherein obtaining the first length of time from the sampling instant to the first transition edge and the second length of time to the second transition edge of the correction signal comprises:

counting the correction signal from the sampling time to the second transition edge, wherein the second time length is represented by the positive count;

counting down the correction signal from the sampling instant to the first transition edge, the first length of time being represented by the count down.

5. The method of claim 4, wherein determining the timing offset value between the clock signal and the correction signal based on the first length of time and the second length of time comprises:

taking an average of the positive count and the negative count as the timing offset value.

6. The method of claim 1, wherein adjusting the timing relationship between the clock signal and the correction signal with a delay unit based on the timing offset value comprises:

determining the number of delay units according to the time sequence deviation value; and

adjusting the number of delay units in the clock path or adjusting the number of delay units in the data path.

7. The method of claim 1, wherein the controller provides a display signal in at least two modes, the display signal comprising a plurality of display sub-signals, the at least two modes providing the plurality of display sub-signals, respectively, each display sub-signal comprising a mode identification signal,

determining a timing offset value between the clock signal and the correction signal based on the clock signal and the correction signal, comprising:

in response to the pattern recognition signal being a correction pattern signal, determining that the display sub-signal is provided by the controller in a correction configuration mode and that the display sub-signal comprises the correction signal; and

determining a timing offset value between the clock signal and the correction signal based on the clock signal and the correction signal.

8. The method of claim 7, wherein the signal following the correction pattern signal is the correction signal.

9. The method of claim 7, wherein the display sub-signal provided by each mode further comprises a trigger signal for instructing the source driver to perform a transfer operation in the at least two modes.

10. The method of claim 9, wherein the trigger signal comprises a data transfer control signal and a data polarity inversion control signal,

wherein a first transition edge of the data polarity inversion control signal is later than a second transition edge of the data transmission control signal, and a first transition state of the data polarity inversion control signal after the first transition edge is at least partially time coincident with a second transition state of the data transmission control signal after the second transition edge.

11. The method of claim 7, wherein the at least two modes further comprise: a row configuration mode or a frame configuration mode,

wherein the display sub-signals provided in the row configuration mode are used to configure the source driver for display of a row of pixels,

the frame configuration mode provides display sub-signals for configuring the source drivers for display of a frame of pixels.

12. The method of claim 11, wherein the controller provides the display signals to the source driver in the row configuration mode, the frame configuration mode, and the correction configuration mode in sequence through the low voltage differential signaling interface.

13. The method of claim 11, wherein the frame configuration mode and the correction configuration mode are during vertical blanking.

14. A signal transmission device is applied to a source driver, wherein the source driver is in communication connection with a controller through a low-voltage differential signal interface mode, and the signal transmission device comprises:

an acquisition unit configured to acquire a clock signal and a correction signal provided by the controller;

a determination unit configured to determine a timing offset value between the clock signal and the correction signal according to the clock signal and the correction signal; and

and the adjusting unit is configured to adjust the timing relation between the clock signal and the correction signal by using a delay unit based on the timing offset value, wherein the delay unit is arranged in a clock path of the clock signal or a data path of the correction signal.

15. A source driver for communicatively coupling with a controller via a low voltage differential signal interface, the source driver comprising:

a processing circuit configured to obtain a clock signal and a correction signal provided by the controller, and determine a timing offset value between the clock signal and the correction signal according to the clock signal and the correction signal; and

a delay circuit disposed in a clock path of the clock signal or in a data path of the correction signal, configured to adjust a timing relationship between the clock signal and the correction signal based on the timing offset value.

16. An electronic device, comprising:

the source driver of claim 15;

a controller, wherein the controller is configured to provide a display signal to the source driver; and

a display panel connected with the source driver to receive a driving signal provided by the source driver, wherein the driving signal is generated based on the display signal.

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