CN115857869A

CN115857869A - Partial product summation module design method and system based on hybrid full adder

Info

Publication number: CN115857869A
Application number: CN202211462443.3A
Authority: CN
Inventors: 谢翔; 黄焘; 闰闰; 李国林; 胡毅; 尹立
Original assignee: Tsinghua University
Current assignee: Tsinghua University
Priority date: 2022-11-21
Filing date: 2022-11-21
Publication date: 2023-03-28

Abstract

The invention provides a design method and a system of a partial product summation module based on a hybrid full adder, wherein the design method comprises the following steps: acquiring input data of a full adder, and calculating the turnover rate of a partial product summation array; setting the node with low turnover rate as a low-burr full adder according to the numerical value of the turnover rate of the partial product summation array; setting the node with high turnover rate as a low-energy-consumption full adder according to the numerical value of the turnover rate of the partial product summation array; and carrying out partial product summation through the low-spur full adder and the low-power consumption full adder. The invention solves the problems of large energy consumption and more burrs of a partial product summation module in the existing multiplier.

Description

Partial product summation module design method and system based on hybrid full adder

Technical Field

The invention relates to the technical field of chip design, in particular to a partial product summation module design method and system based on a hybrid full adder.

Background

The multiplier is an important computing unit in a digital integrated chip and is used for realizing binary multiplication. The method is widely applied to the fields of digital signal processing, information encryption, scientific calculation and the like. The partial product summing module in the multiplier consumes most energy consumption, and the partial product summing module is composed of a plurality of full adders, so the low-energy consumption full adder is one of the key points for realizing high-energy-efficiency calculation. The Wallace tree full adder array and the Dadda tree full adder array are the most common summing module structures, and a large number of full adders are required to realize the summing function.

A full adder is a digital logic unit that sums three input bits. It comprises three input terminals (A, B, CI) and two output terminals (CO, S), wherein the logic expressions of carry output terminal CO and sum output terminal S are shown as follows

In order to implement the above two logics, the adopted methods can be divided into static and dynamic methods. The static method can output results after a period of time delay after the input end level is turned over without using a clock, and the dynamic method can output results after a plurality of clocks. Static implementations require a greater number of transistors than dynamic implementations, but consume less power, so static implementations are more suitable for applications that seek energy efficiency. The static implementation method can be implemented by different design logics, and the most common methods are as follows: complementary Metal Oxide Semiconductor (CMOS), complementary pass transistor logic (CPL), transmission gate logic (TGA), etc.

The complementary CMOS logic has the advantage of high robustness, but has the disadvantage of high input capacitance loading and the additional use of an inverter at the output. The most common CMOS full adder is the mirror full adder proposed in 1985, and the most important feature is the complete symmetry of the pull-down N-pipe PUN and pull-up P-pipe PDN topologies, making it very easy to balance the pull-up and pull-down resistances. The CPL logic is characterized over complementary CMOS logic in that the source terminals of the transistors are no longer connected to the power supply, but rather to the input terminals. The advantage is low input load and less transistor number, and the biggest disadvantage is threshold loss of voltage. Because the NMOS transistor transmits strong 0 and weak 1, and the PMOS transistor transmits strong 1 and weak 0, the TGA logic using the pass transistor can solve the problem of threshold loss of the CPL logic, but the pass transistor has no active driving capability. Most current full adder research is hybrid logic (hybrid logic) that attempts to combine the advantages of all logical styles together. The existing TGA adder has low energy consumption and has the defect that more inverters are used, so that the node power consumption in the circuit is increased. The number of the inverters is reduced after improvement, the driving capability of the output end reaches the available degree by optimizing the size of the tube, and the main contribution is that the performance and the energy consumption performance of the inverter are completely evaluated; however, the path from the CI end to the CO end of the full adder has only one transmission gate, that is, the whole carry chain in the application of cascade connection of the carry ends of the full adder is formed by only transmission gates. The transmission gate can be regarded as a resistor with parasitic capacitance at both ends. Under the well-known Elmore delay model, a carry chain consisting of only transmission gates is a long RC circuit and has very high delay.

Full adders optimized for glitches have been proposed later. The exclusive-or gate of the module 1 is implemented by using a 4-transistor hybrid logic unit, and the exclusive-or gate of the module 2 and the selector of the module 3 are implemented by using transmission gates. The burr reduction means of this work includes two: firstly, the delay unit is utilized to balance the delay from each input to each output, so that the delay from the CI to the output end is the same as the delay from the A or B to the output end; and secondly, a delay unit is used for eliminating the small burr. In the application of cascade connection of carry terminals of a plurality of full adders, the carry output terminal CO is connected to the carry input terminal CI of the next full adder to form a carry chain. Reducing the glitch by extending the carry chain delay in this case does not significantly reduce the glitch and degrades the delay.

Disclosure of Invention

The invention provides a design method and a system of a partial product summation module based on a hybrid full adder, which are used for solving the problems of high energy consumption and more burrs of the partial product summation module in the existing multiplier.

The invention provides a design method of a partial product summation module based on a hybrid full adder, which comprises the following steps:

acquiring input data of a full adder, and calculating the turnover rate of a partial product summation array;

setting the node with low turnover rate as a low-burr full adder according to the numerical value of the turnover rate of the partial product summation array;

setting the node with high turnover rate as a low-energy consumption full adder according to the numerical value of the turnover rate of the partial product summation array;

performing partial product summation with the low-spur full adder and the low-power full adder, comprising:

according to the design method of the partial product summation module based on the hybrid full adder, provided by the invention, the input data of the full adder is obtained, and the turnover rate of the partial product summation array is calculated, and the method specifically comprises the following steps:

acquiring data of an input end and an output end of a full adder;

comparing the output data with the input data, and determining that the turnover rate of the partial product summation array increases along with the increase of the hierarchy.

According to the design method of the partial product summation module based on the hybrid full adder, provided by the invention, according to the numerical value of the turnover rate of the partial product summation array, a node with a low turnover rate is set as a low-spur full adder, and the method specifically comprises the following steps:

forming a delay unit through a specific transistor of the low-glitch full adder;

the time from input to output of the appointed carry is controlled by the delay unit, and the probability of burr occurrence is reduced.

According to the design method of the partial product summation module based on the hybrid full adder, provided by the invention, according to the numerical value of the turnover rate of the partial product summation array, a node with a high turnover rate is set as a low-energy consumption full adder, and the design method specifically comprises the following steps:

inserting an inverter into a carry chain of the low-energy-consumption full adder;

after the phase inverter is inserted into the carry output end of the low-energy-consumption full adder, the carry input of the next-stage full adder is reverse input, and the full adders with two polarities are alternately used, so that the energy consumption is reduced.

According to the design method of the partial product summation module based on the hybrid full adder provided by the invention, the partial product summation is carried out through the low-spur full adder and the low-power consumption full adder, and the design method specifically comprises the following steps:

performing a partial product summation through 8-bit basis and 16-bit basis multipliers;

and the low-burr full adder is used at the level with low turnover rate, and the low-energy-consumption full adder is used at the level with high turnover rate.

According to the design method of the partial product summation module based on the hybrid full adder, the 16-bit-based multiplier carries out partial product summation and uses a seven-line full adder, and the inversion rate of the seven-line full adder is increased step by step from top to bottom;

the full adders in each column are connected into a binary tree, low-spur full adders are used at leaf nodes of the binary tree, and low-energy-consumption full adders are used at other nodes.

The invention also provides a partial product summation module design system based on the hybrid full adder, which comprises the following components:

the turnover rate calculation module is used for acquiring input data of the full adder and calculating the turnover rate of the partial product summation array;

the low-burr setting module is used for setting a node with a low turnover rate as a low-burr full adder according to the numerical value of the turnover rate of the partial product summation array;

the low energy consumption setting module is used for setting the node with high turnover rate as a low energy consumption full adder according to the numerical value of the turnover rate of the partial product summation array;

and the partial product summing module is used for carrying out partial product summing through the low-spur full adder and the low-power consumption full adder.

The invention also provides an electronic device, which comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein the processor executes the program to realize the design method of the partial product summation module based on the hybrid full adder.

The present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a hybrid full-adder based partial product summation module design method as described in any of the above.

The present invention also provides a computer program product comprising a computer program, which when executed by a processor implements the method for designing a partial product sum module based on a hybrid full adder as described in any one of the above.

According to the design method and system of the partial product summation module based on the hybrid full adder, the full adder in the partial product generation module in the multiplier is subjected to turnover rate analysis, and a low-burr full adder is used for a node with a low front stage turnover rate, so that generated burrs are reduced; and for nodes with higher backward stage turnover rate, a low-energy-consumption full adder is used, so that the energy consumption is reduced. By providing two corresponding full adders, wherein the low-energy-consumption full adder uses the mixed logic of complementary CMOS logic and TGA logic and combines the characteristics of high robustness and low energy consumption; the low-glitch full adder uses the delay unit to reduce glitches, and realizes reduction of energy consumption of a partial product summing module in the multiplier and reduction of glitches.

Drawings

In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic flow chart of a design method of a partial product summing module based on a hybrid full adder according to the present invention;

FIG. 2 is a second schematic flow chart of a design method of a partial product sum module based on a hybrid full adder according to the present invention;

FIG. 3 is a second schematic flow chart of a design method of a partial product sum module based on a hybrid full adder according to the present invention;

FIG. 4 is a fourth schematic flowchart of a design method of a partial product sum module based on a hybrid full adder according to the present invention;

FIG. 5 is a block diagram of a design system for a partial product sum block based on a hybrid full adder according to the present invention;

FIG. 6 is a schematic structural diagram of an electronic device provided by the present invention;

FIG. 7 is a schematic diagram of a prior art full adder provided by the present invention;

FIG. 8 is a graph of the full adder slew rate statistics for the partial and sum arrays provided by the present invention;

FIG. 9 is a schematic diagram and layout of a low energy consumption full adder provided by the present invention;

FIG. 10 is a graph comparing the glitch resistance of the delay cell provided by the present invention with that of a conventional inverter;

FIG. 11 is a schematic diagram and layout of a low glitch full adder provided in the present invention;

FIG. 12 is a schematic diagram of a partial product summing module of an 8-bit based 4Booth multiplier provided by the present invention;

FIG. 13 is a partial product array diagram of an 8-bit based 4Booth multiplier provided by the present invention;

FIG. 14 is a graph of flip rate statistics under alexnet input provided by the present invention;

FIG. 15 is a graph of the roll-over rate statistics for other networks provided by the present invention;

FIG. 16 is a schematic diagram of an 8-bit based 4Booth multiplier partial product summing module provided by the present invention;

FIG. 17 is a schematic diagram of a partial product summing module of a 16-bit based 4Booth multiplier provided by the present invention;

FIG. 18 is a schematic diagram of a 16-bit based 4Booth multiplier partial product summing module provided by the present invention;

FIG. 19 is a graph comparing delay, area and power consumption of the multiplier provided by the present invention.

Reference numerals are as follows:

110: a turnover rate calculation module; 120: a low burr setting module; 130: a low energy consumption setting module; 140: a partial product summing module;

610: a processor; 620: a communication interface; 630: a memory; 640: a communication bus.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without inventive step based on the embodiments of the present invention, are within the scope of protection of the present invention.

The following describes a design method of a partial product summation module based on a hybrid full adder in conjunction with fig. 1 to 4, including:

s100, acquiring input data of a full adder, and calculating the turnover rate of a partial product summation array;

s200, setting a node with a low turnover rate as a low-burr full adder according to the numerical value of the turnover rate of the partial product summation array;

s300, setting a node with a high turnover rate as a low-energy-consumption full adder according to the numerical value of the turnover rate of the partial product summation array;

and S400, carrying out partial product summation through the low-spur full adder and the low-power consumption full adder.

Aiming at a digital integrated chip computing unit in the existing multiplier, a full adder is used for operation. The invention adopts two kinds of fully-customized full adders, namely a low-energy-consumption full adder and a low-burr full adder. The parallel multiplier includes a partial product generation module and a partial product summation module, wherein the partial product summation module generally sums partial products using a plurality of full adders forming an array. According to the invention, through analyzing the turnover rate of each full adder in the partial product summation module, a low-energy-consumption full adder is used at a backward-stage high turnover rate node in the summation array, and a low-burr full adder is used at a forward-stage low turnover rate node. The design method and the full-custom full adder provided by the invention reduce the area and energy consumption of the partial product summing module, thereby reducing the area and energy consumption of the multiplier.

Acquiring input data of a full adder, and calculating a partial product summation array turnover rate, wherein the method specifically comprises the following steps:

s101, acquiring data of an input end and an output end of a full adder;

s102, comparing the output end data with the input end data, and determining that the turnover rate of the partial product summation array is increased along with the increase of the hierarchy.

In the invention, the energy consumption of the partial product summation module in the multiplier is higher than that of the partial product generation module, which is the key for reducing the energy consumption of the multiplier. In a partial product summing module formed by combining full adders, the turnover rate of each circuit node has certain characteristics, and the dynamic energy consumption of the partial product summing module can be reduced by utilizing the characteristics.

It can be demonstrated that the flip rates of the sum bit output ends S of the full adders in the same column in the partial product summation module increase with the increase of the number of stages, i.e. the flip rate of the S end of the full adder at the rear stage is higher than that at the front stage. It is first demonstrated that in an xor gate, the output slew rate is higher than the input slew rate. The input end of the exclusive-or gate is A, B, the output end is C, and the truth table is shown in table 1.

TABLE 1 truth table

A	B	C
			0	0	0
0	1	1
			1	0	1
1	1	0

For a certain point X, with X _0→1 Representing the probability of the node flipping from 0 to 1, then

C _0→1 ＝A _0→1 B _0→0 +A _0→0 B _0→1 +A _1→0 B _1→1 +A _1→1 B _1→0

When the total number of flips of a certain node X is large enough, it should be:

X _0→1 ＝X _1→0

X _0→0 ＝P(X＝0)-X _0→1

X _1→1 ＝1-P(X＝0)-X _1→0

therefore it has the advantages of

＝A _0→1 (B _0→0 +B _1→1 )+B _0→1 (A _0→0 +A _1→1 )

＝A _0→1 (1-2B _0→1 )+B _0→1 (1-A _1→1 )

＝A _0→1 +B _0→1 (1-4A _0→1 )

This formula when (1-4A) _0→1 ) > 0, i.e. A _0→1 If < 0.25, XORGate output end turnover rate C _0→1 >A _0→1 . In other words, when the probability that two adjacent inputs of a are different is less than 0.5, the turnover rate of C is greater than a.

In the case of random number input, the probability of the difference between two adjacent inputs is 0.5. In most applications, no matter digital signal processing or neural network calculation, correlation exists between adjacent ones, so that the probability that the partial product bit is different between two adjacent inputs is less than 0.5. In this case, the output of the exclusive or gate has a higher slew rate than either of the two inputs.

Since the sum bit output S of the full adder is an exclusive or of the three inputs, the above discussion of the exclusive or gate can be extended to the S of the full adder, i.e., the full adder S has a higher slew rate than any of the three inputs.

For a second stage full adder, its input is the output of the first stage full adder. If the output of the first-stage full adder still meets the condition that the probability of the difference between two adjacent inputs is less than 0.5, the second-stage full adder also meets the condition that the turnover rate of the output end is higher than any one of the three input ends. In practice, even at the final output of the multiplier, the flip-flop ratio is not higher than the random number bit, so this theory holds true at each full-adder in the multiplier. Of course, the complexity of the burr and the like which must exist in practice is not considered here, but is merely a theoretical explanation. In summary, it can be concluded that the larger the number of stages, or the closer to the full adder at the output of the multiplication result, the higher the slew rate. Statistical results also support this conclusion, as shown with reference to the 8-bit multiplier partial product sum array of fig. 8, the higher the full-adder flip rate at later stages.

According to the numerical value of the turnover rate of the partial product summation array, setting the node with low turnover rate as a low-spur full adder, specifically comprising:

s201, forming a delay unit through a specific transistor of the low-burr full adder;

s202, the time from input to output of the appointed carry is controlled through the delay unit, and the probability of burr occurrence is reduced.

The invention provides a full adder for reducing burrs at a sum output end. The dynamic energy consumption is higher than that of the low-energy full adder, but less burrs can be generated. It is suitable for the front stage in the summation array because the glitch generated by the front stage can be accumulated to the rear stage and the turnover rate of the front stage full adder is low.

Glitches result from delay path mismatches. Taking the example of an exclusive-or gate, the exclusive-or output should not be toggled when two inputs are toggled from 0, 1 to 1, 0 simultaneously. However, if the two inputs are not inverted simultaneously, the xor output will be inverted from 1 to 0 and then back to 1, resulting in two useless inversions. The same problem exists with full adders. Of the three inputs A, B, C of a full adder, the carry input C to output delay is typically shorter than A, B, which results in glitches. The largest effect of the glitches is their cumulative effect. Invalid flips generated by adders in the previous stages of the partial product sum array in the multiplier may again cause the next stages to flip with them. Referring to fig. 7, the prior art method of eliminating glitches in a full adder introduces a delay at the carry input, as shown by the M1 and M4 transistors in the circuit diagram. If the proper delay is introduced by controlling the size of the M1 and M4 pipes, it can be guaranteed that all paths of the full adder have the same delay. But this method is not applicable in the case of full-adder carry-end cascading. The condition is that the input ends arrive at the same time, so that the output ends can output at the same time. However, in the case of cascade carry terminals, three inputs in the carry chain except the first full adder cannot arrive at the same time, which makes this method useless. In addition, the delay of the multiplier is increased by the method of extending the delay of the carry chain path. The invention utilizes a delay unit formed by M1 and M4 tubes. In the case where the M2 and M3 tubes have taken a minimum size, the M1 and M4 tubes can introduce more resistance. Compared with the method of inserting delay of a plurality of cascaded inverters, the method does not introduce grid load capacitance, and reduces energy consumption. The delay cell also has the function of eliminating glitches, as shown in fig. 7, and the output end of the delay cell has larger turnover time when driving the same load capacitor compared with the common inverter.

The present invention eliminates two inverters and shifts the delay cell to the sum bit output to eliminate a portion of the glitch of the sum bit output. The circuit diagram and layout are shown in fig. 8. In the case of carry-side concatenation, the shorter the delay of the carry chain, the better. And the sum bit output end does not have too great influence on the integral time delay of the multiplier even on a critical path. In order to reduce the use of the inverter, the carry output end is processed in the same way as the previous part of the low-energy full adder, and two polarities are required to be alternately used.

According to the numerical value of the turnover rate of the partial product summation array, setting the node with high turnover rate as a low-energy consumption full adder, and specifically comprising the following steps:

s301, inserting an inverter into a carry chain of the low-energy-consumption full adder;

s302, after the phase inverter is inserted into the carry output end of the low-energy-consumption full adder, the carry input of the next-stage full adder is reverse input, and the full adders with two polarities are alternately used, so that energy consumption is reduced.

According to the theory and statistics, the last-stage full adders of the partial product summation array have higher turnover rate, and the full adders are suitable for optimizing energy consumption.

The invention provides an 18-tube full adder with alternately used positive and negative electrodes. It applies to the last stage in the adder array. Compared with the traditional full adder, the 16-tube full adder provided in the prior work has the advantages that three phase inverters are reduced, the grid capacitance load of the internal node of the circuit is greatly reduced, and the energy consumption of the circuit is further reduced. However, such a full adder is not suitable for adder arrays with long carry chains, because the carry output CO of a full adder is connected to the carry input CI of another full adder. For this 16T full adder, this means that the entire carry propagation chain is a transmission gate.

The full adder provided by the invention inserts an inverter into a carry chain. After the phase inverter is inserted into the carry output end, the carry input of the next full adder is reverse input, so that the full adders of two polarities are required to be alternately used. The carry input end CI of the positive full adder is a forward signal, and the output end CO is a reverse signal; the negative full adder requires the carry input terminal C to be a reverse signal and the output CO to be restored to a forward signal. This is ensured by an inverter inserted at the carry output, but the negative full adder needs to generate the correct sum bit output S with an inverted carry input, where circuit modifications are required. Since the full adder can be divided into three modules: two exclusive or gates and a selector, so that outputting the positive S bit can be realized by modifying the exclusive or gate of the input S. This exclusive or gate implements exclusive or of the XOR node with the carry input, requiring the XOR signal to be inverted if the carry input is inverted. Since the inverting node XNR of the XOR is present in the circuit, no additional inverter is needed here. The final circuit diagram and layout are shown in fig. 9.

And carrying out partial product summation through the low-spur full adder and the low-power consumption full adder, and specifically comprising the following steps:

In one specific example, an 8-bit based 4Booth multiplier partial product summing module, such as that shown in FIG. 12, is used to compress the partial product array shown in FIG. 13

The dynamic energy consumption of the full adder is approximately measured according to the turn rate of the sum output end S of the full adder.

The multiplier is used for calculation of the neural network, and network data such as AlexNet, resNet18, vgg16 and the like are input.

For the full-adder array of the partial-sum module, the flip-flop rate of the sum bit output S of each full-adder can be obtained, and the statistical results are shown in fig. 14 and fig. 15.

It can be seen that the full adder array of the summing module has three rows, where the first two rows have a lower slew rate and the last row has a significantly higher slew rate. Therefore, the first two rows use the low-burr full adder in the invention; the last row uses the low-power full adder of the present invention. The design results are shown in fig. 16.

In a 16-bit basis 4Booth multiplier partial product summing module, the full adder array of the original partial product summing module is shown in fig. 17.

The 16-bit multiplier partial product summing module in this example uses a 7-line full adder, and the 7-line full adder has a similar characteristic in that the flip rate gradually increases from top to bottom as in embodiment 1. Since the full adders in each column are connected into a binary tree, low-spur full adders can be used at the leaf nodes of the binary tree, and low-power full adders can be used at other nodes, as shown in fig. 18.

The invention discloses a design method of a partial product summation module based on a hybrid full adder, which comprises the steps of carrying out turnover rate analysis on a full adder in a partial product generation module in a multiplier, using a low-burr full adder for a node with a lower turnover rate at a preceding stage, and reducing generated burrs; and for nodes with higher backward stage turnover rate, a low-energy-consumption full adder is used, so that the energy consumption is reduced. The invention provides two corresponding full adders, wherein the low-energy-consumption full adder uses the mixed logic of complementary CMOS logic and TGA logic and combines the characteristics of high robustness and low energy consumption; wherein the low-glitch full adder uses a delay unit to reduce the glitch.

The results of the latter simulation using a 40 nm CMOS process are shown in fig. 19. The original multiplier uses a traditional 28-tube mirror image full adder, and after the partial product summation module design method provided by the invention is utilized, the energy consumption of the 8-bit multiplier is reduced by 26.9% -31.5%, the energy consumption of the 16-bit multiplier is reduced by 35.8% -37.5%, the delay is not greatly influenced, and the area is reduced. The 8-bit and 16-bit multipliers are just examples of commonly used multipliers, and the method and the two full-adder designs provided by the invention are suitable for multipliers with various precisions.

Referring to fig. 5, the present invention also discloses a partial product summation module design system based on a hybrid full adder, including:

a turnover rate calculation module 110, configured to obtain input data of the full adder, and calculate a turnover rate of the partial product summation array;

a low-spur setting module 120, configured to set a node with a low slew rate as a low-spur full adder according to the value of the slew rate of the partial product summation array;

a low energy consumption setting module 130, configured to set a node with a high turnover rate as a low energy consumption full adder according to the value of the turnover rate of the partial product summation array;

and a partial product summing module 140 for performing a partial product summation by the low spur full adder and the low power consumption full adder.

The turnover rate calculating module 110 obtains data of an input end and an output end of the full adder;

A low-glitch setting module 120 for forming a delay unit through a specific transistor of the low-glitch full adder;

the time from the input to the output of the appointed carry is controlled by the delay unit, and the occurrence probability of burrs is reduced.

A low energy consumption setting module 130, inserting an inverter into the carry chain of the low energy consumption full adder;

A partial product summing module 140 for performing a partial product summation through 8-bit basis and 16-bit basis multipliers;

and a low-burr full adder is used at a level with low turnover rate, and a low-energy-consumption full adder is used at a level with high turnover rate.

According to the design system of the partial product summation module based on the hybrid full adder, disclosed by the invention, the low-burr full adder is used for a node with a lower front stage turnover rate by analyzing the turnover rate of the full adder in the partial product generation module in the multiplier, so that the generated burrs are reduced; and for nodes with higher backward stage turnover rate, a low-energy-consumption full adder is used, so that the energy consumption is reduced. By providing two corresponding full adders, wherein the low-energy-consumption full adder uses the mixed logic of complementary CMOS logic and TGA logic and combines the characteristics of high robustness and low energy consumption; the low-glitch full adder uses the delay unit to reduce glitches, and realizes reduction of energy consumption of a partial product summing module in the multiplier and reduction of glitches.

Fig. 6 illustrates a physical structure diagram of an electronic device, which may include, as shown in fig. 6: a processor (processor) 610, a communication Interface (Communications Interface) 620, a memory (memory) 630 and a communication bus 640, wherein the processor 610, the communication Interface 620 and the memory 630 communicate with each other via the communication bus 640. Processor 610 may invoke logic instructions in memory 630 to perform a method for designing a partial product sum module based on a hybrid full adder, the method comprising: acquiring input data of a full adder, and calculating the turnover rate of a partial product summation array;

setting the node with high turnover rate as a low-energy-consumption full adder according to the numerical value of the turnover rate of the partial product summation array;

and carrying out partial product summation through the low-spur full adder and the low-power consumption full adder.

In addition, the logic instructions in the memory 630 may be implemented in software functional units and stored in a computer readable storage medium when the logic instructions are sold or used as independent products. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

In another aspect, the present invention further provides a computer program product, the computer program product including a computer program, the computer program being stored on a non-transitory computer-readable storage medium, wherein when the computer program is executed by a processor, the computer is capable of executing a method for designing a partial product sum module based on a hybrid full adder, the method including: acquiring input data of a full adder, and calculating the turnover rate of a partial product summation array;

In still another aspect, the present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored, where the computer program is implemented by a processor to perform the method for designing a partial product sum module based on a hybrid full adder provided by the above methods, where the method includes: acquiring input data of a full adder, and calculating the turnover rate of a partial product summation array;

The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.

Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.

Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims

1. A design method of a partial product summation module based on a hybrid full adder is characterized by comprising the following steps:

and carrying out partial product summation through the low-burr full adder and the low-power consumption full adder.

2. The design method of the partial product summation module based on the hybrid full adder according to claim 1, wherein the obtaining input data of the full adder and calculating the turnover rate of the partial product summation array specifically comprises:

acquiring data of an input end and an output end of a full adder;

3. The design method of the partial product summation module based on the hybrid full adder according to claim 1, wherein the step of setting a node with a low slew rate as the low spur full adder according to the value of the slew rate of the partial product summation array comprises:

4. The design method of the partial product summation module based on the hybrid full adder according to claim 1, wherein the step of setting the node with high slew rate as the low power consumption full adder according to the value of the slew rate of the partial product summation array specifically comprises:

5. The design method of the partial product summation module based on the hybrid full adder according to claim 1, wherein the performing partial product summation by the low-spur full adder and the low-power consumption full adder specifically comprises:

6. The design method of the partial product summation module based on the hybrid full adder according to claim 5, wherein the 16-bit base multiplier performs partial product summation by using seven lines of full adders, and the inversion rate of the seven lines of full adders is increased from top to bottom;

7. A system for designing a partial product summation module based on a hybrid full adder, comprising:

and the partial product summation module is used for carrying out partial product summation through the low-spur full adder and the low-power consumption full adder.

8. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the hybrid full-adder-based partial product summation module design method of any one of claims 1 to 6 when executing the program.

9. A non-transitory computer readable storage medium having stored thereon a computer program, which when executed by a processor implements the hybrid full-adder based partial product summation module design method of any one of claims 1 to 6.

10. A computer program product comprising a computer program, wherein the computer program, when executed by a processor, implements the method for designing a hybrid full-adder based partial product summation module according to any of claims 1 to 6.