CN115834326A

CN115834326A - Multi-node network serial communication system and method with automatically configurable IP address

Info

Publication number: CN115834326A
Application number: CN202310023215.4A
Authority: CN
Inventors: 程大军; 张奕; 李帅; 鲁朝正
Original assignee: Zhejiang Lab
Current assignee: Zhejiang Lab
Priority date: 2023-01-09
Filing date: 2023-01-09
Publication date: 2023-03-21

Abstract

The invention discloses a multi-node network serial communication system and a method with automatically configurable IP addresses, wherein the system comprises an upper computer and a plurality of nodes connected in series; the hardware platform of each node comprises a HEAD PHY chip, a TAIL PHY chip and an FPGA chip; the net port of the HEAD PHY chip of the HEAD node is connected with an upper computer, the net port of the TAIL PHY chip of the TAIL node is suspended, and the net port of the HEAD PHY chip of the middle node is connected with the net port of the TAIL PHY chip of the previous node to complete the network communication between the middle node and the previous node; the network port of the TAIL PHY chip of the intermediate node is connected with the network port of the HEAD PHY chip of the next node to finish the network communication between the intermediate node and the next node; the FPGA chip completes the realization of a network protocol stack, the automatic configuration of a node IP address, the configuration of a node working state and the collection and sending of node data, and ensures the normal communication of a network. The invention does not need additional router equipment, realizes the simple and convenient multi-node serial communication method and has strong applicability.

Description

Multi-node network serial communication system and method with automatically configurable IP address

Technical Field

The invention relates to the field of network communication, in particular to a multi-node network serial communication system and a method capable of automatically configuring an IP address.

Background

With the development of network technology, the application field of network communication is also expanding. For a scene that a plurality of nodes are far away and the communication data volume of a single node is large, network communication is basically selected. The scheme adopted at present is that single nodes are respectively connected to a router, and then the router is connected to an upper computer, so that the equipment and use cost of a one-stage or multi-stage router are increased; meanwhile, the IP of each node needs to be manually configured, and the IP of each node needs to be ensured not to be repeated, otherwise, network conflict is caused.

Disclosure of Invention

The invention aims to provide a multi-node network serial communication system and a method capable of automatically configuring an IP address, which can automatically complete IP configuration and network routing work in a node.

The purpose of the invention is realized by the following technical scheme:

a multi-node network serial communication system with automatically configurable IP address comprises an upper computer and a plurality of nodes connected in series; the hardware platform of each node comprises a HEAD PHY chip, a TAIL PHY chip and an FPGA chip;

the net port of the HEAD PHY chip of the HEAD node is connected with an upper computer, the net port of the TAIL PHY chip of the TAIL node is suspended, and the net port of the HEAD PHY chip of the middle node is connected with the net port of the TAIL PHY chip of the previous node to complete the network communication between the middle node and the previous node; the network port of the TAIL PHY chip of the intermediate node is connected with the network port of the HEAD PHY chip of the next node to finish the network communication between the intermediate node and the next node; the FPGA chip completes the functions of realizing a network protocol stack, automatically configuring a node IP address, configuring a node working state and acquiring and sending node data, and ensures the normal communication of a network.

Furthermore, a plurality of nodes are connected in series through a network cable.

A multi-node network serial communication method with automatically configurable IP address is realized based on a multi-node network serial communication system;

on the basis of a network communication protocol of the FPGA chip, the upper computer completes automatic configuration of an IP address of each node; then, the upper computer inquires, matches and forwards through the first node and all nodes behind the first node to configure the working state of the designated node, or configures the working states of all nodes in a broadcast forwarding mode; the upper computer obtains the data of the designated node independently or obtains the data of all the nodes simultaneously, and finally multi-node network serial communication is achieved.

Further, the mode that the upper computer independently acquires the data of the designated node is as follows: the upper computer sends a data request packet of the designated node, all nodes in front of the designated node sequentially forward the data request packet of the designated node, and the data of the designated node is forwarded through all nodes in front of the designated node and finally sent to the upper computer.

Further, the mode that the upper computer simultaneously acquires the data of all the nodes is as follows: the upper computer sends data request packets of all the nodes, after each node receives the data request packet, data acquisition is started, a data acquisition packet is created by a tail node, and is packed and forwarded sequentially through the nodes in front of the data acquisition packet, and finally the data acquisition packet is sent to the upper computer, so that the upper computer can simultaneously acquire the data of all the nodes.

Further, the automated configuration of the IP address of each node is achieved by the following sub-steps:

(1) The method comprises the steps that an upper computer sends an initialization broadcast packet, wherein the content of the initialization broadcast packet comprises an initialization instruction and a source IP address of the upper computer, and the source IP address is recorded as IP0;

(2) After the HEAD PHY chip of the node receives the initialization broadcast packet of the upper computer, whether the net mouth of the TAIL PHY chip of the current node is suspended is judged:

if not, the FPGA chip of the node analyzes a source IP address IP0 in the initialization broadcast packet; setting IP0 as the destination IP address of the HEAD PHY chip of the current node; adding 1 to the IP0 address, recording as IP1, and setting as the source IP addresses of the HEAD PHY chip and the TAIL PHY chip of the current node; adding 2 to the IP0 address, recording as IP2, and setting as the target IP address of the TAIL PHY chip of the current node; then, updating the initialization broadcast packet to enable the initialization broadcast packet to comprise an initialization instruction and the source IP address of the current node; then, the node sends an initialization broadcast packet to the next node through the TAIL PHY chip; by analogy, the IP address updating operation of each node is completed;

when the network port of the TAIL PHY chip of the current node is judged to be empty, the current node is a TAIL node, and at the moment, the same IP address updating operation as the step (2) is executed, but only the source IP address and the destination IP address of the HEAD PHY chip of the current node are updated, so that the IP address configuration of the TAIL node is completed;

(3) After the tail node completes the IP address configuration, an initialization completion packet is constructed, and the initialization completion packet comprises an initialization completion instruction and the source IP address of the current node; sending the initialization completion packet to a TAIL PHY chip of the node next to the last through the HEAD PHY chip of the TAIL node;

(4) After the TAIL PHY chip of the penultimate node receives the initialization completion packet sent by the TAIL node, the source IP address of the node is added into the initialization completion packet and sent to the TAIL PHY chip of the penultimate node through the HEAD PHY chip of the node;

and by analogy, the initialization completion packet is sent to the upper computer by the HEAD node through the HEAD PHY chip, the IP addresses of all the nodes and the positions of the nodes can be obtained after the upper computer analyzes the initialization completion packet, and initialization configuration is completed.

Further, the upper computer configures the working state of the designated node by inquiring, matching and forwarding the first node and all the nodes behind the first node, and the method is realized by the following steps:

(1) The upper computer sends a node configuration packet, wherein the content of the node configuration packet comprises a node configuration instruction, a source IP address of a node to be configured and node configuration content;

(2) After the HEAD PHY chip of the node receives the configuration packet of the upper computer, the FPGA chip of the node compares the source IP address of the configuration node in the configuration packet with the source IP address of the current node, and if the source IP address of the configuration node is consistent with the source IP address of the current node, the configuration content in the packet is analyzed to complete the configuration of the working state of the current node; if not, forwarding the configuration packet to the next node through the TAIL PHY chip of the node;

repeating the steps until a node with the source IP address consistent with the source IP address in the configuration packet is found, analyzing the configuration content, and completing the configuration of the working state of the node;

(3) After the working state of the node is configured, constructing a node configuration completion packet, wherein the content of the node configuration completion packet comprises a node configuration completion instruction and a source IP address of the node; sending the configuration completion packet to a TAIL PHY chip of a node before the configuration completion packet through the HEAD PHY chip of the current node;

(4) After receiving a configuration completion packet sent by the next node, the TAIL PHY chip of the node directly sends the configuration completion packet to the TAIL PHY chip of the previous node through the HEAD PHY chip of the node;

and by analogy, the upper computer completes the working state configuration of the designated node until the HEAD node sends the configuration completion packet to the upper computer through the HEAD PHY chip of the HEAD node.

Further, the upper computer configures the working states of all nodes in a broadcast forwarding mode, and the method is realized by the following steps:

(1) The upper computer sends a node configuration packet, wherein the content of the node configuration packet comprises a node configuration instruction, a broadcast IP address and node configuration content;

(2) After the HEAD PHY chip of the node receives the configuration packet of the upper computer, whether the net mouth of the TAIL PHY chip of the current node is suspended is judged:

if not, the FPGA chip of the node analyzes the broadcast IP address and the configuration content in the packet to complete the configuration of the current node working state; the configuration packet is forwarded to the next node through a TAIL PHY chip of the node; by parity of reasoning, the configuration of the working states of all the nodes is completed;

when the network port of the TAIL PHY chip of the current node is judged to be empty, the current node is a TAIL node, and at the moment, the FPGA chip of the TAIL node analyzes the configuration content in the packet to complete the configuration of the working state of the current node;

(3) After the working state of the tail node is configured, constructing a node configuration completion packet, wherein the content of the node configuration completion packet comprises a node configuration completion instruction and a source IP address of the node; sending the configuration completion packet to a TAIL PHY chip of a previous node through the HEAD PHY chip of the current node;

(4) After receiving a configuration completion packet sent by a next node, the TAIL PHY chip of the node adds a source IP address of the node into the configuration completion packet and sends the configuration completion packet to the TAIL PHY chip of the previous node of the current node through the HEAD PHY chip of the node;

and by analogy, the configuration completion packet is sent to the upper computer until the HEAD node sends the configuration completion packet to the upper computer through the HEAD PHY chip, and all nodes with the completed working state configuration can be obtained after the upper computer analyzes the configuration completion packet.

Further, the step of separately acquiring the data of the designated node by the upper computer specifically includes the following substeps:

(1) The method comprises the steps that an upper computer sends a data request packet of a node, wherein the content of the node data request packet comprises a node data request instruction and a source IP address of a data node needing to be obtained;

(2) After the HEAD PHY chip of the node receives a data request packet of an upper computer, the FPGA chip of the node compares a source IP address in the packet with a source IP address of the current node, and if the source IP address in the packet is consistent with the source IP address of the current node, the collection of the data of the current node is completed; if not, the data request packet is forwarded to the next node through the TAIL PHY chip of the node;

repeating the steps until a node with the source IP address consistent with the source IP address in the data request packet is found, and finishing the acquisition of the data of the designated node;

(3) After the data of the designated node is acquired, constructing a data acquisition packet of the designated node, wherein the content of the data acquisition packet comprises a node data acquisition completion instruction, a source IP address of the designated node, data length and acquired data; sending the data acquisition packet to a TAIL PHY chip of a previous node through the HEAD PHY chip of the current node;

(4) After receiving a data acquisition packet sent by a next node, the TAIL PHY chip of the node directly sends the data acquisition packet to the TAIL PHY chip of the previous node of the current node through the HEAD PHY chip of the node;

and by analogy, the upper computer finishes the acquisition of the data of the designated node until the HEAD node sends the data acquisition packet to the upper computer through the HEAD PHY chip of the HEAD node.

Further, the upper computer simultaneously acquires data of all nodes, and specifically includes the following substeps:

(1) The upper computer sends data request packets of all the nodes, wherein the content of the node data request packets comprises node data request instructions and broadcast IP addresses;

(2) After the HEAD PHY chip of the node receives a data request packet of an upper computer, whether the net mouth of the TAIL PHY chip of the current node is suspended is judged:

if not, the FPGA chip of the node analyzes the broadcast IP address in the packet and then finishes the acquisition of the current node data; meanwhile, the configuration packet is forwarded to the next node through the TAIL PHY chip of the node;

when the network port of the TAIL PHY chip of the current node is judged to be empty, the current node is a TAIL node, and at the moment, the FPGA chip of the TAIL node analyzes the broadcast address in the packet to complete the acquisition of the data of the current node;

(3) After the tail node finishes data acquisition, constructing a current node data acquisition packet, wherein the content of the data acquisition packet comprises a node data acquisition instruction, a current node source IP address, data length and acquired data; sending the data acquisition packet to a TAIL PHY chip of a previous node through a HEAD PHY chip of a current node;

(4) After receiving a data acquisition packet sent by a node behind the node, a TAIL PHY chip of the node adds a source IP address, a data length and acquired data of the current node into the data acquisition packet and sends the data acquisition packet to a TAIL PHY chip of a node before the current node through a HEAD PHY chip of the node;

and by analogy, the upper computer finishes the acquisition of all node data until the HEAD node sends the data acquisition packet to the upper computer through the HEAD PHY chip of the HEAD node.

The invention has the beneficial effects that:

in the multi-node network serial communication system and the method, the multi-node networking is simple, the configuration of IP and the network routing work are automatically completed in the nodes, the realization and debugging cost is reduced, and the realization method is simple and convenient, the means is flexible, and the applicability is strong. The method is particularly suitable for the scene that multiple nodes need to be serialized, and the nodes can be increased and decreased at any position.

Drawings

Fig. 1 is a flow diagram of an IP address auto-configuration according to an example embodiment thereof.

Fig. 2 is a data flow diagram illustrating IP address autoconfiguration for three-node communications.

FIG. 3 is a flow diagram of a specified node configuration in one illustrative embodiment.

FIG. 4 is a flow chart of an all nodes configuration of an exemplary embodiment.

FIG. 5 is a flow diagram of designated node data collection in an exemplary embodiment.

FIG. 6 is a flow chart of all node data collection in one exemplary embodiment.

Detailed Description

The present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments, and the objects and effects of the present invention will become more apparent, it being understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

The multi-node network serial communication system with the automatically configurable IP address comprises an upper computer and a plurality of nodes connected in series; each node hardware platform comprises two network port PHY chips, namely a HEAD PHY chip, a TAIL PHY chip and an FPGA chip;

the plurality of nodes are connected in series, the net port of the HEAD node HEAD PHY chip is connected with an upper computer, the net port of the TAIL node TAIL PHY chip is suspended, and the net port of the middle node HEAD PHY chip is connected with the net port of the last node TAIL PHY chip to complete the network communication between the middle node and the last node; the network port of the TAIL PHY chip of the intermediate node is connected with the network port of the HEAD PHY chip of the next node to finish the network communication between the intermediate node and the next node; the FPGA chip completes the functions of realizing a network protocol stack, automatically configuring a node IP address, configuring the working state of the node and acquiring and sending node data, and ensures the normal communication of the network. As one implementation mode, a plurality of nodes are connected in series through a network cable.

The multi-node network serial communication method with the automatically configurable IP address is realized based on the multi-node network serial communication system; on the basis of a network communication protocol of the FPGA chip, the upper computer completes automatic configuration of an IP address of each node; then, the upper computer inquires, matches and forwards through the first node and all nodes behind the first node to configure the working state of the designated node, or configures the working states of all nodes in a broadcast forwarding mode; the upper computer acquires data of the designated node independently or acquires data of all nodes simultaneously, and finally multi-node network serial communication is realized;

the mode of independently acquiring the data of the designated node by the upper computer is as follows: the upper computer sends a data request packet of a designated node, all nodes in front of the designated node sequentially forward the data request packet of the designated node, and the data of the designated node is forwarded through all nodes in front of the designated node and finally sent to the upper computer;

the mode that the host computer acquires the data of all the nodes simultaneously is as follows: the upper computer sends data request packets of all the nodes, after each node receives the data request packet, data acquisition is started, a data acquisition packet is created by a tail node, and is packed and forwarded sequentially through the nodes in front of the data acquisition packet, and finally the data acquisition packet is sent to the upper computer, so that the upper computer can simultaneously acquire the data of all the nodes.

1. Automated configuration of IP addresses

The automatic configuration of the IP address is the core of the invention, and the specific configuration flow is shown in FIG. 1. Fig. 2 illustrates an automatic configuration process described by way of example of three-node communication. In fig. 2, node 1 is the head node, node 2 is the intermediate node, and node 3 is the tail node. The destination IP address of each node HEAD PHY chip is F0 as a default, the source IP address is F1 as a default, the destination address of the TAIL PHY chip is F2 as a default, and the source IP address is F1 as a default. After initialization, each node can automatically configure the source IP address and the destination IP address of the HEAD PHY chip and the TAIL PHY chip, and the specific steps are as follows:

(1) The host computer sends the initialized broadcast packet

The host computer is connected with the network port of the HEAD PHY chip of the node 0 (the first node), and the source IP address of the HEAD PHY chip of the node 0 is unknown. And the upper computer sends an initialization broadcast packet, wherein the broadcast packet comprises an initialization instruction recorded as cmd0 and a source IP address recorded as 02 of the upper computer.

(2) Initial configuration of head node

The HEAD PHY chip of a first node, namely the node 0, receives an initialization broadcast packet of an upper computer, firstly judges whether a net port of a TAIL PHY chip of the current node is suspended, because the net port of the TAIL PHY chip of the first node is not suspended, an FPGA chip of the first node analyzes a source IP address 02 of the upper computer according to an initialization instruction cmd0, sets a target IP address of the HEAD PHY chip of the first node as the source IP address of the upper computer, namely 02, and sets the source IP addresses of the HEAD PHY chip and the TAIL PHY chip of the first node as the source IP address of the upper computer plus 1, namely 03; and setting the destination IP address of the TAIL PHY chip of the first node as the source IP address of the upper computer plus 2 to obtain 04. Updating the initialization broadcast packet to enable the initialization broadcast packet to comprise an initialization command cmd0 and a source IP address 03 of the current node; then, node 0 sends an initialization broadcast packet to the next node through its TAIL PHY chip;

(3) Intermediate node initialization configuration

After the intermediate node, i.e. node 1, receives the initialization broadcast packet through its HEAD PHY chip, it first determines whether the portal of the TAIL PHY chip of the current node is suspended: if not, executing the same IP address updating operation as the node 0: the destination IP address of the HEAD PHY chip of the node is set to 03, the source IP addresses of the HEAD PHY chip and the TALIL PHY chip are set to 04, and the destination IP address of the TAIL PHY chip is set to 05. Then, updating the initialization broadcast packet to enable the initialization broadcast packet to comprise an initialization instruction and the source IP address of the current node; the node 1 sends an initialization broadcast packet to the next node through the TAIL PHY chip; by parity of reasoning, the IP address updating operation of each intermediate node is completed; and when the TAIL PHY chip of the current node is judged to be empty, the current node is the TAIL node.

(4) Tail node initialization configuration

The net port of the TAIL PHY chip of the node 2 is suspended, and the FPGA chip of the node 2 determines that the node is the TAIL node by reading the state bit of the PHY. As shown in FIG. 2, the node performs the same initialization configuration as node 0, the destination IP address of the HEAD PHY chip is set to 04, the source IP addresses of the HEAD PHY chip and the TAIL PHY chip are set to 05, and the destination IP address of the TAIL PHY chip remains unchanged.

(5) Tail node initialization response

After the TAIL node, namely the node 2, completes the IP address configuration, an initialization completion packet is constructed, the initialization completion packet comprises an initialization completion instruction cmd1 and a source IP address 05 of the node, and the initialization completion packet is sent to the node which is the next to last node, namely a TAIL PHY chip of the node 1 through the HEAD PHY chip of the TAIL node;

(6) Intermediate node initialization response

After the TAIL PHY chip of the penultimate node, namely the node 1, receives the initialization completion packet sent by the TAIL node, the source IP address of the node is added into the initialization completion packet and is sent to the penultimate node, namely the TAIL PHY chip of the node 0, through the HEAD PHY chip; the contents of the initialization completion packet include an initialization completion instruction cmd1, the source IP address 05 of the tail node, and the source IP address 04 of the own node. And so on.

(7) Head node initialization response

After the TAIL PHY chip of the first node, namely the node 0, receives the initialization completion packet sent by the intermediate node, the source IP address of the node is added into the initialization response packet and is sent to the upper computer through the HEAD PHY chip of the node; the contents of the response packet include an initialization completion instruction cmd1, the source IP address 05 of the tail node, the source IP address 04 of the intermediate node, and the source IP address 03 of the own node. The initialization configuration is complete. As shown in table 1, an initialization broadcast packet and initialization completion packet data contents are transmitted for each node.

Table 1 each node transmits an initialization broadcast packet and initialization completion packet data contents

2. Working state of upper computer configuration designated node

The upper computer configures the working state of the designated node by inquiring, matching and forwarding the first node and all nodes behind the first node, and fig. 3 is a flow chart of the configuration of the designated node. This embodiment is described with an example of a configuration in which the host computer completes the operation state of the node 1.

(1) The upper computer sends a configuration packet of the designated node

The upper computer sends a configuration packet of the designated node, the configuration packet comprises a configuration instruction which is recorded as cmd2, the source IP address of the node to be configured, in the example, the node 1 is configured, so the source IP address is 04, and the working state is achieved.

(2) The head node receives the configuration packet of the designated node

The HEAD PHY chip of the first node, namely the node 0, receives the configuration packet of the appointed node of the upper computer, the FPGA chip of the first node analyzes the source IP address 04 of the node to be configured according to the configuration instruction cmd2, the source IP address 04 does not pass through the comparison with the source IP address 03 of the node, and the configuration packet of the appointed node is sent to the next node through the TAIL PHY chip of the node.

(3) The intermediate node receives the configuration packet of the appointed node

The intermediate node, namely the node 1, receives the configuration packet of the designated node through the HEAD PHY chip thereof, the FPGA chip of the intermediate node resolves the source IP address 04 of the node to be configured according to the configuration instruction cmd2, the comparison is passed with the source IP address 04 of the node, and the FPGA chip of the intermediate node resolves the content of the working state to configure the working state of the node.

(4) Intermediate node configuration response

After the intermediate node, i.e., the node 1, completes the node configuration, a configuration complete packet is constructed, the configuration complete packet includes a configuration complete instruction cmd3 and the source IP address 04 of the node, and the initialization complete packet is sent to the TAIL PHY chip of the HEAD node through the HEAD PHY chip of the intermediate node.

(5) Head node configuration response

After receiving the node configuration completion packet sent by the intermediate node, the TAIL PHY chip of the first node, namely the node 0, directly forwards the packet to the upper computer through the HEAD PHY chip of the first node. The configuration of the designated node is completed. Table 2 is data contents of the designated node configuration packet and the node configuration completion packet.

Table 2 specifies the data contents of the node configuration packet and the node configuration completion packet

3. The upper computer configures the working states of all the nodes

The upper computer configures the working states of all the nodes in a broadcast forwarding manner, and as shown in fig. 4, the upper computer completes a flow chart for configuring the working states of all the nodes. This embodiment is still described with 3 nodes as an example.

(1) The upper computer sends all node configuration packets

And the upper computer sends all node configuration packets, wherein the configuration packets comprise configuration instructions, and the configuration instructions are recorded as cmd2, broadcast addresses ff and working states.

(2) The head node receives all node configuration packets

The HEAD node, namely the HEAD PHY chip of the node 0, receives a specified node configuration packet of an upper computer, and firstly judges whether the net port of the TAIL PHY chip of the current node is suspended, and the FPGA chip of the HEAD node configures the working state of the node according to a configuration instruction cmd2 and a broadcast address ff because the net port of the TAIL PHY chip of the HEAD node is not suspended; and simultaneously, all the node configuration packets are sent to the intermediate node, namely the node 1, through the TAIL PHY chip of the first node.

(3) The intermediate node receives all the node configuration packets

The HEAD PHY chip of the intermediate node, namely the node 1, receives the appointed node configuration packet sent by the TAIL PHY chip of the first node, firstly judges whether the network port of the TAIL PHY chip of the current node is suspended, and because the network port of the TAIL PHY chip of the intermediate node is not suspended, the intermediate node executes the same operation as the first node and sends all the node configuration packets to the TAIL node, namely the node 2.

(4) The tail node receives all node configuration packets

The TAIL node, i.e. the HEAD PHY chip of the node 2, receives the configuration packet of the designated node of the upper computer, and first determines whether the net port of the TAIL PHY chip of the current node is suspended, and since the net port of the TAIL PHY chip of the node 2 is suspended, the node 2 is the TAIL node. The tail node performs the same working state configuration as node 0.

(5) Tail node configuration response

And after the TAIL node, namely the node 2 completes the node configuration, constructing a configuration completion packet, wherein the configuration completion packet comprises a configuration completion instruction cmd3 and the source IP address 05 of the node, and sending the configuration completion packet to the TAIL PHY chip of the intermediate node through the HEAD PHY chip of the TAIL node.

(6) Intermediate node configuration response

After receiving the configuration completion packet from the node 2, the intermediate node, i.e., the node 1, adds the source IP address 04 of the node to the configuration completion packet and transmits the configuration completion packet to the TAIL PHY chip of the HEAD node through the HEAD PHY chip of the intermediate node.

(7) Head node configuration response

After receiving the configuration completion packet sent by the node 1, the first node, namely the node 0, adds the source IP address 03 of the node into the configuration completion packet, and sends the configuration completion packet to the upper computer through the HEAD PHY chip of the first node. The content of the upper computer receiving the configuration completion response packet includes a configuration response instruction cmd3, the source IP address 05 of the tail node, the source IP address 04 of the intermediate node, and the source IP address 03 of the local node. And completing the configuration of all nodes. The data contents of all the node configuration packets and the node configuration completion packet are shown in table 3.

Table 3 data contents of all node configuration packets and node configuration completion packets

4. The upper computer independently obtains the data of the designated node

The upper computer obtains data of the designated node independently, the specific flow is shown in fig. 5, and the upper computer finishes collecting the data of the node 1.

(1) The upper computer sends a data request packet of a designated node

The upper computer sends a data request packet of the designated node, wherein the data request packet comprises a request instruction which is recorded as cmd4, and the source IP address of the node to be acquired is the node 1 in the example, so the source IP address is 04.

(2) The head node receives the data request packet of the designated node

The HEAD PHY chip of the first node, namely the node 0, receives a data request packet of the appointed node of the upper computer, the FPGA chip of the first node analyzes the source IP address 04 of the data node to be acquired according to the configuration instruction cmd4, the comparison between the source IP address 04 of the data node and the source IP address 03 of the node is not passed, and the data request packet of the appointed node is sent to the next node through the TAIL PHY chip of the node.

(3) The intermediate node receives the data request packet of the designated node

The intermediate node, namely the node 1, receives the data request packet of the designated node through the HEAD PHY chip thereof, the FPGA chip of the intermediate node analyzes the source IP address 04 of the node to be configured according to the configuration instruction cmd4, the comparison with the source IP address 04 of the node is passed, and the intermediate node finishes the data acquisition.

(4) Intermediate node data acquisition response

After the intermediate node, i.e., the node 1, finishes the node data acquisition, a data acquisition packet is constructed, the data acquisition packet comprises a data acquisition completion instruction cmd5, the source IP address 04 of the node, the data length of the node and the data acquired by the node, and the data acquisition packet is sent to the TAIL PHY chip of the HEAD node through the HEAD PHY chip of the intermediate node.

(5) First-node data collection response

After receiving the data acquisition packet sent by the intermediate node, the TAIL PHY chip of the HEAD node, namely the node 0, directly forwards the data acquisition packet to the upper computer through the HEAD PHY chip of the HEAD node. The content of the data acquisition packet received by the upper computer includes the node 1 source IP address 04, the node 1 data length and the node 1 data, and the upper computer completes the acquisition of the node 1 data as shown in table 4.

Table 4 specifies the data content of node data request packets and data acquisition packets

5. The upper computer acquires data of all nodes

The upper computer obtains data of all the nodes, and the specific flow is shown in fig. 6. In the following, the upper computer is still described by taking three nodes as an example to complete the collection of data of all the nodes.

(1) The upper computer sends a data request packet of all nodes

And the upper computer sends all node data request packets, wherein the data request packets comprise data request instructions and are recorded as cmd4 and broadcast addresses ff.

(2) The first node receives all node data request packets

The HEAD PHY chip of a first node, namely a node 0, receives all node data request packets of an upper computer, firstly judges whether the net mouth of the TAIL PHY chip of the current node is suspended, and the FPGA chip of the first node collects the data of the node according to a data request instruction cmd4 and a broadcast address ff because the net mouth of the TAIL PHY chip of the first node is not suspended; and simultaneously, all node data request packets are sent to the intermediate node, namely the node 1, through the TAIL PHY chip of the first node.

(3) The intermediate node receives all node data request packets

The HEAD PHY chip of the intermediate node, i.e., node 1, receives all node data request packets sent by the TAIL PHY chip of the HEAD node, and first determines whether the network port of the TAIL PHY chip of the current node is suspended, and since the network port of the TAIL PHY chip of the intermediate node is not suspended, the intermediate node performs the same operation as the HEAD node and sends all the node data request packets to the TAIL node, i.e., node 2.

(4) The tail node receives all node configuration packets

The TAIL node, i.e. the HEAD PHY chip of the node 2, receives the configuration packet of the designated node of the upper computer, and first determines whether the net port of the TAIL PHY chip of the current node is suspended, and since the net port of the TAIL PHY chip of the node 2 is suspended, the node 2 is the TAIL node. The tail node performs the same data collection operation as node 0.

(5) Tail node data acquisition response

And after the TAIL node, namely the node 2 finishes data acquisition, constructing a data acquisition packet, wherein the data acquisition packet comprises a data acquisition response instruction cmd5, the source IP address 05 of the node, the data length of the node and the data acquired by the node, and sending the data acquisition packet to the TAIL PHY chip of the intermediate node through the HEAD PHY chip of the TAIL node.

(6) Intermediate node data acquisition response

After receiving the data acquisition packet sent from the node 2, the intermediate node, i.e., the node 1, adds the source IP address 04 of the node, the data length of the node and the data acquired by the node to the data acquisition packet and sends the data acquisition packet to the TAIL PHY chip of the HEAD node through the HEAD PHY chip of the intermediate node.

(7) First-node data collection response

After the first node, i.e., the node 0, receives the data acquisition packet sent by the node 1, the source IP address 03 of the node, the data length of the node and the data acquired by the node are added to the data acquisition packet, and the data acquisition packet is sent to the upper computer through the HEAD PHY chip of the first node. The content of the data acquisition packet received by the upper computer includes a data acquisition response command cmd5, the source IP address 05 of the end node, the data length of the end node, the data of the end node, the source IP address 04 of the intermediate node, the data length of the intermediate node, the data of the intermediate node, the source IP address 03 of the head node, the data length of the head node and the data of the head node, and as shown in table 5, data acquisition of all the nodes is completed.

TABLE 5 data content of all node data request and data acquisition packets

It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and although the invention has been described in detail with reference to the foregoing examples, it will be apparent to those skilled in the art that various changes in the form and details of the embodiments may be made and equivalents may be substituted for elements thereof. All modifications, equivalents and the like which come within the spirit and principle of the invention are intended to be included within the scope of the invention.

Claims

1. A multi-node network serial communication system with automatically configurable IP address is characterized in that the system comprises an upper computer and a plurality of nodes connected in series; the hardware platform of each node comprises a HEAD PHY chip, a TAIL PHY chip and an FPGA chip;

2. The multi-node network serial communication system according to claim 1, wherein the plurality of nodes are connected in series via a network cable.

3. A multi-node network serial communication method in which an IP address is automatically configurable, the method being implemented based on the multi-node network serial communication system of claim 1;

4. The multi-node network serial communication method capable of automatically configuring the IP address according to claim 3, wherein the mode for the upper computer to separately acquire the data of the designated node is as follows: the upper computer sends a data request packet of the designated node, all nodes in front of the designated node sequentially forward the data request packet of the designated node, and the data of the designated node is forwarded through all nodes in front of the designated node and finally sent to the upper computer.

5. The multi-node network serial communication method capable of automatically configuring the IP address according to claim 3, wherein the mode for the upper computer to simultaneously acquire the data of all the nodes is as follows: the upper computer sends data request packets of all the nodes, after each node receives the data request packet, data acquisition is started, a data acquisition packet is created by a tail node, and is packed and forwarded sequentially through the nodes in front of the data acquisition packet, and finally the data acquisition packet is sent to the upper computer, so that the upper computer can simultaneously acquire the data of all the nodes.

6. The method of claim 3, wherein the automatic configuration of the IP address of each node is achieved by the following sub-steps:

(2) After the HEAD PHY chip of the node receives the initialization broadcast packet of the upper computer, whether the net gape of the TAIL PHY chip of the current node is suspended is judged:

if not, the FPGA chip of the node analyzes a source IP address IP0 in the initialization broadcast packet; setting IP0 as the destination IP address of the HEAD PHY chip of the current node; adding 1 to the IP0 address, recording as IP1, and setting the IP address as the source IP address of the HEAD PHY chip and the TAIL PHY chip of the current node; adding 2 to the IP0 address, recording as IP2, and setting as the target IP address of the TAIL PHY chip of the current node; then, updating the initialization broadcast packet to enable the initialization broadcast packet to comprise an initialization instruction and the source IP address of the current node; then, the node sends an initialization broadcast packet to the next node through the TAIL PHY chip; by analogy, the IP address updating operation of each node is completed;

(3) After the tail node completes the IP address configuration, an initialization completion packet is constructed, and the initialization completion packet comprises an initialization completion instruction and the source IP address of the current node; sending the initialization completion packet to a TAIL PHY chip of the next to last node through the HEAD PHY chip of the TAIL node;

(4) After the TAIL PHY chip of the node which is last but one receives the initialization completion packet sent by the TAIL node, the source IP address of the node is added into the initialization completion packet and is sent to the TAIL PHY chip of the node which is last but one through the HEAD PHY chip of the node;

and by analogy, the initialization completion package is sent to the upper computer by the HEAD node through the HEAD PHY chip, the IP addresses of all the nodes and the positions of the nodes can be obtained after the upper computer analyzes the initialization completion package, and the initialization configuration is completed.

7. The multi-node network serial communication method capable of automatically configuring the IP address according to claim 3, wherein the upper computer configures the working state of the designated node by inquiring, matching and forwarding the first node and all the following nodes, and the method is implemented by the following steps:

(2) After the HEAD PHY chip of the node receives the configuration packet of the upper computer, the FPGA chip of the node compares the source IP address of the configuration node in the configuration packet with the source IP address of the current node, and if the source IP address of the configuration node is consistent with the source IP address of the current node, the configuration content in the packet is analyzed to complete the configuration of the working state of the current node; if not, the configuration packet is forwarded to the next node through the TAIL PHY chip of the node;

(4) After receiving the configuration completion packet sent by the next node, the TAIL PHY chip of the node directly sends the configuration completion packet to the TAIL PHY chip of the previous node through the HEAD PHY chip of the node;

8. The multi-node network serial communication method capable of automatically configuring the IP address according to claim 3, wherein the upper computer configures the working states of all the nodes in a broadcast forwarding manner, and the method is implemented by the following steps:

if not, the FPGA chip of the node analyzes the broadcast IP address and the configuration content in the packet to complete the configuration of the current node working state; the configuration packet is forwarded to the next node through the TAIL PHY chip of the node; by analogy, the configuration of the working states of all the nodes is completed;

and by analogy, the configuration completion packet is sent to the upper computer by the HEAD node through the HEAD PHY chip, and all the nodes with the working state configuration completed can be obtained after the upper computer analyzes the configuration completion packet.

9. The multi-node network serial communication method capable of automatically configuring an IP address according to claim 3, wherein the upper computer separately obtains data of a designated node, and specifically comprises the following sub-steps:

(1) The upper computer sends a data request packet of a node, wherein the content of the node data request packet comprises a node data request instruction and a source IP address of a data node to be acquired;

(4) After receiving a data acquisition packet sent by a next node, the TAIL PHY chip of the node directly sends the data acquisition packet to the TAIL PHY chip of a previous node of the current node through the HEAD PHY chip of the node;

10. The multi-node network serial communication method capable of automatically configuring an IP address according to claim 3, wherein the upper computer obtains data of all nodes simultaneously, and specifically comprises the following sub-steps:

if not, the FPGA chip of the node analyzes the broadcast IP address in the packet and then completes the acquisition of the current node data; meanwhile, the configuration packet is forwarded to the next node through the TAIL PHY chip of the node;

(3) After the tail node finishes data acquisition, constructing a current node data acquisition packet, wherein the content of the data acquisition packet comprises a node data acquisition instruction, a current node source IP address, data length and acquired data; sending the data acquisition packet to a TAIL PHY chip of a previous node through the HEAD PHY chip of the current node;

(4) After receiving a data acquisition packet sent by a node behind the node, a TAIL PHY chip of the node adds a source IP address, data length and acquired data of the current node into the data acquisition packet and sends the data acquisition packet to a TAIL PHY chip of a node before the current node through a HEAD PHY chip of the node;