CN115833544A - SHEPWM controller and application thereof - Google Patents
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Abstract
The invention belongs to the technical field of SHEPWM modulation, and particularly relates to a SHEPWM controller and application thereof, wherein the SHEPWM controller comprises a DSP chip and an FPGA chip which are electrically connected, and the DSP chip comprises: CPU1: the device is used for realizing system sampling, control and switching angle table look-up; the CPU2: the CPU1 is electrically connected and used for phase locking, SHEPWM modulation and PWM comparison output of the system; PWM comparison is output to the FPGA chip; shared memory (shared memory): the CPU1 and the CPU2 are electrically connected and used for exchanging data between the CPU1 and the CPU2, wherein the data comprises phase-locked loop output instantaneous phase, three-phase shift angle and three-phase switch angle data; the FPGA chip is used for adding dead zones to the PWM signals; the data reading speed is high, and the calculation error is greatly reduced; the requirement of the logic unit is small, the timing design is simpler.
Description
Technical Field
The invention belongs to SHEPWM the field of modulation technology, and is characterized by that, in particular to a SHEPWM controller and application thereof.
Background
One important reason for the wide application of conventional SPWM modulation is that it implements the output of the PWM signal through a hardware comparator. In the existing references, the controller design based on SHEPWM is usually realized by a DSP chip and an FPGA chip together. Wherein, the DSP realizes the sampling filtering and control algorithm of the signal, the FPGA realizes SHEPWM modulation and PWM signal generation and shaping.
According to different storage modes of the switching angle data, the traditional SHEPWM controller can be divided into two structures, one structure is that the switching angle data is stored in an off-chip nonvolatile memory such as a parallel FLASH, a serial FLASH, an SD card and the like, and the structure is shown in figure 1. The structure is mainly characterized in that an off-chip memory is used, so that the structure has the characteristics of large storage capacity, low price and less FPGA resource consumption; but the reading of the switch angle data under this structure is often realized by serial communication, the reading speed is slow.
The second controller structure is shown in fig. 2, and the system under the structure stores the switching angle data in an FPGA configuration chip, and loads the switching angle data into an internal logic unit of the FPGA to operate online during power-on operation. Utilize FPGA's parallel arithmetic capability under this kind of structural style, accelerated the table look-up and the comparative speed of switch angle greatly, be suitable for however, under this structure, because SHEPWM realizes the particularity, need a large amount of IO interfaces to communicate between MCU and the FPGA, mainly include: 1) Three-phase modulation ratio signals and three-phase shift angle signals, wherein each signal usually needs more than 10 bits of IO port to ensure sufficient accuracy; 2) Control signals such as a switching angle update signal, a phase synchronization signal, and the like; 3) A system frequency signal to generate a real-time phase. The communication signals between the MCU and the FPGA occupy a large amount of IO resources, and detailed time sequence and length design is required to ensure sufficient communication precision and speed. In addition, a large number of RAM units are required for storing switching angle data and a large number of logic units are required for realizing comparison logic of PWM signals, and the requirements are rapidly increased along with the increase of the number of switching angles.
Disclosure of Invention
The invention discloses a SHEPWM controller and application thereof, and mainly solves the problems that the reading speed of the traditional SHEPWM controller is low, and the requirements of an IO port and a logic unit are high.
[ the present invention provides a SHEPWM controller ]
The utility model provides a SHEPWM controller, includes electric connection's DSP chip and FPGA chip, the DSP chip includes:
CPU1: the device is used for realizing system sampling, control and switching angle table look-up;
the CPU2: the CPU1 is electrically connected and used for phase locking, SHEPWM modulation and PWM comparison output of the system; PWM comparison is output to the FPGA chip;
shared memory (shared memory): the CPU1 and the CPU2 are electrically connected and used for exchanging data between the CPU1 and the CPU2, wherein the data comprises phase-locked loop output instantaneous phase, three-phase shift angle and three-phase switch angle data;
the FPGA chip is used for adding dead zones for PWM signals.
Preferably, the power supply further comprises an SPI FLASH chip electrically connected to the CPU1, and the SPI FLASH chip is used to store the three-phase switching angle data.
Preferably, the three-phase switching angle data is loaded into an internal storage module (RAM) in the CPU1 chip through SPI serial communication.
Preferably, the internal memory module (RAM) in the CPU1 is a display look-up table (LUT).
Preferably, a phase-locked loop (PLL) for system phase locking is provided in the CPU 2.
Preferably, the step of adding the dead zone signal to the PWM signal by the FPGA chip is as follows:
s1, an FPGA inputs an original PWM signal and synchronizes with a clock signal to obtain a CPTR signal;
s2, after the CPTR rising edge is detected, setting a rising edge flag bit RFLP signal, and setting a START signal by the RFLP signal;
s3, when the START signal is at a high level, the 16-bit counter STARTs to accumulate and count, when the designed dead time is reached, the timer automatically clears, and meanwhile, the START signal is reset;
s4, inverting the START signal to obtain a correction signal CMP;
and S5, the CMP low level stage represents dead time, the PWM signal is turned off at the moment, and the CMP signal and the PWM signal are logically AND-ed to obtain the DPWM signal after the dead time is added.
The invention also provides the application of the SHEPWM controller in the SHEPWM modulation system
When the SHEPWM controller is applied to a SHEPWM modulation system, when the modulation frequency is 80 kHz, the output harmonic performance of the system is already high, and the THD (total harmonic distortion) is reduced to be below 3.7%.
The technical scheme provided by the invention at least has the following technical effects:
the control algorithm and the SHEPWM modulation algorithm are both completed in the CPU1 and the CPU2 of the DSP chip, data exchange realizes conversion between data through an on-chip shared memory, sampling frequency updating of switching angle data is easy to realize, data reading speed is high, and calculation errors are greatly reduced.
Only 12 paths of IO interfaces are occupied between the DSP chip and the FPGA chip to realize the transmission of PWM signals, the complexity of system design is reduced, and the PCB manufacturing process is simplified; in the traditional structure, 30 modulation ratio signals (10-bit precision of each three-phase modulation ratio), 1 high-speed clock signal and a plurality of control synchronous signals are occupied between the DSP chip and the FPGA chip, and the system is more complex.
The FPGA chip only realizes the dead zone adding function, and the logic unit requirement is low; in the traditional structure, the FPGA needs to realize complex functions of switching angle table look-up, switching angle data table look-up, synchronous updating of system frequency and phase, PWM signal comparison logic, dead time addition and the like, the logic unit requirement is high, and the logic unit requirement is increased sharply along with the increase of the number of the switching angles. And the time sequence design is more complex, and certain calculation error and control delay are inevitably generated.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
FIG. 1 is a schematic structural diagram of a SHEPWM controller according to the first background art of the present invention;
FIG. 2 is a schematic structural diagram of a second SHEPWM controller according to the background art of the present invention;
FIG. 3 is a schematic structural diagram of the SHEPWM controller according to embodiment 1 of the present invention;
fig. 4 is a circuit diagram of a dead zone generating signal in embodiment 1 of the present invention;
FIG. 5 is a diagram showing a dead zone waveform in embodiment 1 of the present invention;
fig. 6 is a flowchart of dead zone signal addition in embodiment 2 of the present invention;
FIG. 7 is a diagram of FPGA sequential logic design when adding a dead zone signal in embodiment 2 of the present invention;
fig. 8 is a block diagram of the SHEPWM modulation system according to embodiment 3 of the present invention;
fig. 9 is a waveform diagram of the voltage and current of the power grid during the SHEPWM modulation process in embodiment 3 of the present invention;
fig. 10 is an analysis diagram of the grid-connected current THD after SHEPWM modulation in embodiment 3 of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary and intended to be illustrative of the embodiments of the present invention, and should not be construed as limiting the invention.
In the description of the embodiments of the present invention, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the embodiments of the present invention and simplifying the description, but do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the embodiments of the present invention, "a plurality" means two or more unless specifically limited otherwise.
Example 1: a SHEPWM controller.
Referring to fig. 3, the embodiment discloses a controller structure which adopts a dual-core DSP TMS320F28377D (dual-core processor) and additionally a small-scale FPGA to realize the system control and the SHEPWM modulation functions. The system comprises a DSP chip and an FPGA chip which are electrically connected, wherein the DSP chip comprises a CPU1, a CPU2 electrically connected with the CPU1 and a shared memory (shared memory) electrically connected with the CPU1 and the CPU 2; the system comprises a CPU (central processing unit) 1, a FPGA chip, a phase-locked loop (PLL) and an FPGA chip, wherein all the processes of sampling, controlling, modulating, PWM generating and PWM shaping are realized by a dual-core DSP, the CPU1 realizes system sampling, controlling and switching angle table look-up, the CPU2 realizes phase locking, SHEPWM modulating and PWM comparison output of the system, the PWM comparison output is transmitted to the FPGA chip, the CPU2 is internally provided with the PLL (phase locked loop) for system phase locking, and the FPGA realizes the function of adding dead zones of PWM signals. In addition, the switch angle data is stored in the off-chip SPI FLASH chip (electrically connected with the CPU 1). When the system is powered on and operated, the switch angle data preloads into a memory module (RAM) of the CPU1 chip through SPI serial communication, and the memory module (RAM) in the CPU1 chip is a display look-up table (LUT) so as to realize the function of high-speed look-up table. Data exchange is realized between the CPU1 and the CPU2 through a shared memory (shared memory), and the main data comprises: the phase-locked loop outputs an instantaneous phase (ω t), three phase shift angles (θ a, b, c), and three phase switching angle data (α 1 to α N).
Specifically, referring to fig. 3, the spi FLASH chip loads the switching angle data preloads into a display look-up table (LUT, which is essentially a RAM, after data is written into the RAM in advance, whenever a signal is input, the data is equivalent to inputting an address to look up a table, finding out contents corresponding to the address, and then outputting the contents to the CPU2 for SHEPWM modulation (specific harmonic elimination pulse width modulation, that is, PWM is generated by optimal selection of switching time to eliminate selected low harmonics); and then output to the driving circuit. The control algorithm and the SHEPWM modulation algorithm are both completed in the CPU1 and the CPU2 of the DSP chip, data exchange realizes conversion between data through shared memory in a chip, sampling frequency updating of switching angle data is easy to realize, data reading speed is high, calculation errors are greatly reduced, the FPGA chip only realizes a dead zone adding function, and the requirement of a logic unit is low.
In the inverse view of fig. 1 and fig. 2, a single MCU is adopted, not only SHEPWM modulation is completed in an FPGA chip, but also the addition of dead zone signals (dead zone logic) and a display look-up table (LUT) are completed in the FPGA chip, the FPGA needs to realize complex functions of switch angle look-up table, switch angle data look-up table, synchronous update of system frequency and phase, PWM signal comparison logic, dead zone time addition and the like, and the logic unit has large requirements; and rises sharply as the number of switching angles increases. And the time sequence design is more complex, and certain calculation error and control delay are inevitably generated. And conversion of data (CTL-control track signal, CLK-clock signal, m) a,b,c The three-phase abc modulation signals) are converted between the MCU and the FPGA, so that 30 modulation ratio signals (10-bit precision of each three-phase modulation ratio), 1 high-speed clock signal and a plurality of control synchronous signals are occupied between the DSP chip (MCU) and the FPGA chip, and the system is more complex; and the DSP chip and the FPGA chip only occupy 12 paths of IO interfaces to realize the transmission of PWM signals, thereby reducing the complexity of system design and simplifying the PCB manufacturing process.
According to the SHEPWM controller structure, a hardware design period is simplified, the FPGA resource requirement is reduced, and a fast SHEPWM algorithm for updating a sampling period is easy to realize. The CPU1 realizes the sampling and control of the system, and the working frequency of the system is Ts, which is called as the control frequency; the CPU2 realizes the generation of PLL phase lock (phase lock loop or phase lock loop for integrating clock signal uniformly to make high-frequency device work normally) and PWM of the system, and the working frequency is Tm, which is called as modulation frequency; the SHEPWM controller structure not only meets the real-time requirement of fast dynamic response SHEPWM, but also simplifies the complexity of early-stage time sequence design of the system, reduces the consumption of a logic unit of an FPGA chip, reduces the system cost and is beneficial to the engineering realization of SHEPWM.
Example 2: and the FPGA chip adds a dead zone signal to the PWM signal.
Referring to fig. 6, this embodiment discloses a step of adding a dead zone signal to a PWM signal by an FPGA chip on the basis of embodiment 1,
s1, an FPGA inputs an original PWM signal and synchronizes with a clock signal to obtain a CPTR signal;
s2, after the CPTR rising edge is detected, setting a rising edge flag bit RFLP signal, and setting a START signal by the RFLP signal;
s3, when the START signal is at a high level, the 16-bit counter STARTs to accumulate and count, when the designed dead time is reached, the timer automatically clears, and meanwhile, the START signal is reset;
s4, obtaining a correction signal CMP after inverting the START signal;
s5: the CMP low level stage represents dead time, at the moment, the PWM signal is closed, and the CMP signal and the PWM signal are subjected to logical AND to obtain a DPWM signal added with the dead time; referring to fig. 4 and 5, it can be seen from the circuit diagrams and waveform diagrams of the dead zone signal generation that the PWM signal adds the dead zone time (T) d ) And then outputs a PWM signal (also called DPWN signal).
Referring to fig. 7, the FPGA timing logic design diagram when the dead zone signal is added is shown, in which the numbers 0 to N represent one counting period, and the timing signal is explained with reference to the following table:
TABLE 1 FPGA timing Signal interpretation
| Signal | Explanation of the invention |
| PWM | Pulse width modulation signal |
| CLK | Clock signal input by FPGA |
| CPTR | PWM is identical to clock signalSynchronization signal of step |
| RFLG | CPTR rising edge flag signal |
| START | Counter start signal |
| CNTR | 16 bit counter |
| CMP | Modified signal after inversion of START signal |
| DPWM | PWM signal after FPGA outputs and adds dead zone |
Example 3: use of a SHEPWM controller in a SHEPWM modulation system.
Referring to fig. 8, the present embodiment discloses an application of a SHEPWM controller in a SHEPWM modulation system, the SHEPWM modulation system includes an inverter, a filter, a SHEPWM controller, and a sampler, the inverter is a three-level NPC inverter, the three-level NPC inverter is connected to a dc side, the filter is an LCL filter, the LCL filter is electrically connected to a grid, the grid is connected to a load, the sampler is electrically connected to the SHEPWM controller, the three-level NPC inverter, and the LCL filter, the SHEPWM controller is the SHEPWM controller in embodiment 1, and the SHEPWM controller performs modulation, and during the modulation process of the SHEPWM modulation system, referring to fig. 9 and 10, when the modulation frequency is 80 kHz, the system output harmonic performance is already high, and THD (total harmonic distortion: harmonic distortion is a harmonic component that an output signal has more than an input signal.
The present invention is not limited to the above preferred embodiments, and any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. The utility model provides a SHEPWM controller, includes electric connection's DSP chip and FPGA chip, its characterized in that, the DSP chip includes:
CPU1: the device is used for realizing system sampling, control and switching angle table look-up;
the CPU2: the CPU1 is electrically connected and used for phase locking, SHEPWM modulation and PWM comparison output of the system; PWM comparison is output to the FPGA chip;
sharing the memory: the CPU1 and the CPU2 are electrically connected and used for exchanging data between the CPU1 and the CPU2, wherein the data comprises phase-locked loop output instantaneous phase, three-phase shift angle and three-phase switch angle data;
the FPGA chip is used for adding dead zones to PWM signals.
2. The SHEPWM controller of claim 1, further comprising an SPI FLASH chip electrically connected to the CPU1, the SPI FLASH chip for storing three-phase switching angle data.
3. The SHEPWM controller of claim 2, wherein the three-phase switching angle data is loaded into an internal memory module within CPU1 chip via SPI serial communication.
4. The SHEPWM controller of claim 3, wherein the internal memory module within CPU1 chip is a display look-up table.
5. The SHEPWM controller of claim 1, wherein a phase-locked loop for system phase locking is provided within the CPU 2.
6. The SHEPWM controller of claim 1, wherein the FPGA chip adds a dead-band signal to the PWM signal as follows:
s1, an FPGA inputs an original PWM signal and synchronizes with a clock signal to obtain a CPTR signal;
s2, after the CPTR rising edge is detected, setting a rising edge flag bit RFLP signal, and setting a START signal by the RFLP signal;
s3, when the START signal is in a high level, the 16-bit counter STARTs to accumulate and count, when the designed dead time is reached, the timer automatically resets, and meanwhile, the START signal is reset;
s4, obtaining a correction signal CMP after inverting the START signal;
and S5, the CMP low level stage represents dead time, the PWM signal is turned off at the moment, and the DPWM signal after the dead time is added is obtained after the CMP signal and the PWM signal are subjected to logical AND.
7. Use of a SHEPWM modulation system, characterized in that a SHEPWM controller according to any of claims 1-6 is used in a SHEPWM modulation system.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101295935A (en) * | 2007-12-10 | 2008-10-29 | 西北工业大学 | Optimizing PWM modulation method capable of restraining harmonic wave |
| CN102983768A (en) * | 2012-11-14 | 2013-03-20 | 国网智能电网研究院 | Optimization control method based on selective harmonic elimination pulse width modulation (SHEPWM) |
| CN104022667A (en) * | 2014-06-19 | 2014-09-03 | 安徽大学 | SHEPWM method for three-level inverter |
| WO2021031685A1 (en) * | 2019-08-21 | 2021-02-25 | 中车永济电机有限公司 | Control modulation method for high power direct drive permanent magnet synchronous motor |
-
2023
- 2023-02-24 CN CN202310159273.XA patent/CN115833544A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101295935A (en) * | 2007-12-10 | 2008-10-29 | 西北工业大学 | Optimizing PWM modulation method capable of restraining harmonic wave |
| CN102983768A (en) * | 2012-11-14 | 2013-03-20 | 国网智能电网研究院 | Optimization control method based on selective harmonic elimination pulse width modulation (SHEPWM) |
| CN104022667A (en) * | 2014-06-19 | 2014-09-03 | 安徽大学 | SHEPWM method for three-level inverter |
| WO2021031685A1 (en) * | 2019-08-21 | 2021-02-25 | 中车永济电机有限公司 | Control modulation method for high power direct drive permanent magnet synchronous motor |
Non-Patent Citations (1)
| Title |
|---|
| 程竟陵: "改进 SHEPWM技术及其在大功率并网逆变器的应用", 中国博士学位论文全文数据库（电子期刊）工程科技II辑, no. 3, pages 109 - 118 * |
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