CN115831722B - Method for preparing semiconductor structure - Google Patents
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- CN115831722B CN115831722B CN202310023923.8A CN202310023923A CN115831722B CN 115831722 B CN115831722 B CN 115831722B CN 202310023923 A CN202310023923 A CN 202310023923A CN 115831722 B CN115831722 B CN 115831722B
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Abstract
The invention relates to a preparation method of a semiconductor structure. The method comprises the following steps: providing a substrate; forming a shallow trench isolation structure in the substrate, wherein the shallow trench isolation structure isolates a plurality of active areas which are arranged at intervals in the substrate; an edge groove is arranged between the top edge of the shallow trench isolation structure and the active region; forming a first dielectric layer on the upper surface of the active region; forming a hard mask layer on the upper surface of the first dielectric layer and the upper surface of the shallow trench isolation structure; the hard mask layer fills the edge groove; forming a second dielectric layer on the upper surface of the hard mask layer; etching the second dielectric layer and the hard mask layer to obtain a patterned dielectric layer and a patterned hard mask layer, wherein openings are formed in the patterned dielectric layer and the patterned hard mask layer, and the openings expose part of the upper surface of the first dielectric layer, part of the shallow trench isolation structure and part of the side trench; the exposed side groove is internally provided with a residual hard mask layer; and removing the residual hard mask layer. The method can save cost.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a method for manufacturing a semiconductor structure.
Background
With the development of semiconductor technology, in the conventional technology, a Hard Mask (HM) is usually removed before the gate dielectric layer grows, however, due to the problem of step height (step height) of the active region and the side trench (divot) phenomenon of the shallow trench isolation structure during the formation process, the Hard Mask layer is easy to have small particles remained in the side trench. In the subsequent wet removal process, the dielectric layer is removed, so that the hard mask layer of the small particles remained in the edge groove falls into the cleaning groove, and a cleaning solution in the cleaning groove is filled with a large amount of small particle residues of the hard mask layer. The cleaning solution in the cleaning tank is usually required to be reused, so that small particle residues are randomly attached to the surface of the wafer to be cleaned, and if the cleaning solution in the cleaning tank is frequently replaced, the problem of high cost exists.
Disclosure of Invention
Based on this, it is necessary to provide a method for manufacturing a semiconductor structure against the problem of high cost of frequent replacement of cleaning liquid in the conventional technology.
In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor structure, including:
providing a substrate;
forming a shallow trench isolation structure in the substrate, wherein the shallow trench isolation structure isolates a plurality of active areas which are arranged at intervals in the substrate; an edge groove is formed between the top edge of the shallow groove isolation structure and the active region;
forming a first dielectric layer on the upper surface of the active region;
forming a hard mask layer on the upper surface of the first dielectric layer and the upper surface of the shallow trench isolation structure; the hard mask layer fills the side groove;
forming a second dielectric layer on the upper surface of the hard mask layer;
etching the second dielectric layer and the hard mask layer to obtain a patterned dielectric layer and a patterned hard mask layer, wherein openings are formed in the patterned dielectric layer and the patterned hard mask layer, and the openings expose part of the upper surface of the first dielectric layer, part of the shallow trench isolation structure and part of the side trench; the exposed side grooves are internally provided with residual hard mask layers;
and removing the residual hard mask layer.
In one embodiment, the method further comprises:
removing the patterned dielectric layer and the exposed first dielectric layer to expose part of the active region;
and forming a gate dielectric layer on the exposed upper surface of the active region.
In one embodiment, after forming the gate dielectric layer on the exposed upper surface of the active region, the method further includes:
forming a grid structure on the upper surface of the grid dielectric layer;
and forming a source region and a drain region in the active region at two opposite sides of the gate structure.
In one embodiment, the material of the first dielectric layer, the material of the second dielectric layer and the material of the shallow trench isolation structure are the same.
In one embodiment, the first dielectric layer includes a silicon oxide layer, the second dielectric layer includes a silicon oxide layer, the hard mask layer includes a silicon nitride layer, and the shallow trench isolation structure includes a silicon oxide isolation structure.
In one embodiment, the removing the residual hard mask layer includes:
and taking the patterned dielectric layer as a protective layer of the patterned hard mask layer, and removing the residual hard mask layer by using a first wet cleaning process.
In one embodiment, the removing the patterned dielectric layer and the exposed first dielectric layer includes:
and simultaneously removing the patterned dielectric layer and the exposed first dielectric layer by using a second wet cleaning process.
In one embodiment, the cleaning solution of the first wet cleaning process comprises phosphoric acid; the cleaning solution of the second wet cleaning process comprises hydrofluoric acid diluent.
In one embodiment, a dry etching process is used to etch the second dielectric layer and the hard mask layer.
In one embodiment, the etching the second dielectric layer and the hard mask layer to obtain a patterned dielectric layer and a patterned hard mask layer includes:
forming a photoresist layer on the upper surface of the second dielectric layer;
patterning the photoresist layer to obtain a patterned photoresist layer;
and etching the second dielectric layer and the hard mask layer based on the patterned photoresist layer to obtain the patterned dielectric layer and the patterned hard mask layer.
According to the preparation method of the semiconductor structure, the shallow trench isolation structure is formed in the substrate, and a plurality of active areas which are distributed at intervals are isolated in the substrate by the shallow trench isolation structure; an edge groove is formed between the top edge of the shallow groove isolation structure and the active region; forming a first dielectric layer on the upper surface of the active region; forming a hard mask layer on the upper surface of the first dielectric layer and the upper surface of the shallow trench isolation structure; the hard mask layer fills the side groove; forming a second dielectric layer on the upper surface of the hard mask layer; etching the second dielectric layer and the hard mask layer to obtain a patterned dielectric layer and a patterned hard mask layer, wherein openings are formed in the patterned dielectric layer and the patterned hard mask layer, and the openings expose part of the upper surface of the first dielectric layer, part of the shallow trench isolation structure and part of the side trench; the exposed side grooves are internally provided with residual hard mask layers; therefore, the residual hard mask layer in the exposed side groove can be removed, so that the hard mask layer with small particles is difficult to remain in the cleaning groove, frequent replacement of cleaning liquid in the cleaning groove is not needed, and cost can be reduced.
Drawings
In order to more clearly illustrate the technical solutions of embodiments or conventional techniques of the present application, the drawings required for the descriptions of the embodiments or conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a schematic diagram of a structure formed in a conventional method for removing a hard mask layer according to an embodiment;
FIG. 2 is a schematic diagram of a structure formed in a conventional method for removing a hard mask layer according to an embodiment;
FIG. 3 is a schematic diagram illustrating a structure formed in a conventional method for removing a hard mask layer according to an embodiment;
FIG. 4 is a flow chart illustrating a method of fabricating a semiconductor structure according to one embodiment;
FIG. 5 is a schematic cross-sectional view of a semiconductor structure obtained in step S102 in a method for fabricating a semiconductor structure according to an embodiment;
FIG. 6 is a schematic cross-sectional view of the structure obtained in step S103 in the method for fabricating a semiconductor structure according to one embodiment;
FIG. 7 is a schematic cross-sectional view of the structure obtained in step S104 in the method for fabricating a semiconductor structure according to one embodiment;
FIG. 8 is a schematic cross-sectional view of the structure obtained in step S105 in a method for fabricating a semiconductor structure according to an embodiment;
FIG. 9 is a schematic cross-sectional view of the structure obtained in step S106 in the method for fabricating a semiconductor structure according to one embodiment;
FIG. 10 is a schematic cross-sectional view of a semiconductor structure obtained in step S107 in a method for fabricating a semiconductor structure according to an embodiment;
FIG. 11 is a flow chart illustrating a method of fabricating a semiconductor structure according to one embodiment;
FIG. 12 is a schematic cross-sectional view of a structure obtained in step S1101 in a method for fabricating a semiconductor structure according to one embodiment;
FIG. 13 is a schematic cross-sectional view of a semiconductor structure obtained in step S1102 in a method for fabricating a semiconductor structure according to an embodiment;
FIG. 14 is a flow chart of a method for fabricating a semiconductor structure according to one embodiment;
fig. 15 is a schematic cross-sectional view of a structure obtained in step S1402 in a method for manufacturing a semiconductor structure according to an embodiment;
fig. 16 is a flow chart illustrating the steps of step S106 in the method for fabricating a semiconductor structure according to an embodiment;
FIG. 17 is a schematic cross-sectional view of a semiconductor structure obtained in step S1061 in a method for manufacturing a semiconductor structure according to an embodiment;
FIG. 18 is a schematic cross-sectional view of a structure obtained in step S1062 in a method for fabricating a semiconductor structure according to an embodiment;
fig. 19 is a schematic cross-sectional view of a structure obtained in step S1063 in a method for manufacturing a semiconductor structure according to an embodiment.
Reference numerals illustrate: 10-substrate, 101-shallow trench isolation structure, 102-active region, 1011-side trench, 20-first dielectric layer, 30-hard mask layer, 301-patterned hard mask layer, 302-residual hard mask layer, 40-second dielectric layer, 401-patterned dielectric layer, 402-opening, 50-gate dielectric layer, 60-gate structure, 70-photoresist layer, 701-patterned photoresist layer, 80-dielectric layer.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Examples of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention; for example, the first doping type may be made the second doping type, and similarly, the second doping type may be made the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, in this specification, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations of the illustrated shapes due to, for example, manufacturing techniques and/or tolerances are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.
In the conventional art, referring to fig. 1 to 3, firstly referring to fig. 1, a patterned photoresist layer 701 is formed on the upper surface of the hard mask layer 30, then referring to fig. 2, the hard mask layer is etched based on the patterned photoresist layer 701 to form a patterned hard mask layer 301 and expose a portion of the dielectric layer 80, and the patterned photoresist layer 701 is removed after the etching is completed. At this time, since the shallow trench isolation structure 101 is easy to form a side trench (divot) 1011 during the formation process, the side trench 1011 has a residual hard mask layer 302 during the formation process of the patterned hard mask layer 301, as shown in fig. 2. Thereafter, the structure obtained in fig. 2 is placed in a cleaning tank, and a specific cleaning solution is used to clean the exposed dielectric layer 80, and in the cleaning process, as shown in fig. 3, the cleaning solution only can remove the dielectric layer 80, but cannot remove the hard mask layer 30, so that the residual hard mask layer 302 falls into the cleaning tank, and as the process proceeds, the cleaning solution in the cleaning tank fills with a large amount of residual hard mask layer 302. The cleaning solution in the cleaning tank is generally required to be reused, so that the residual hard mask layer 302 is randomly attached to the surface of the wafer to be cleaned, and if the cleaning solution in the cleaning tank is frequently replaced, the problem of high cost exists.
Referring to fig. 4, the present application provides a method for preparing a semiconductor structure, including:
s101: providing a substrate;
s102: forming a shallow trench isolation structure in the substrate, wherein the shallow trench isolation structure isolates a plurality of active areas which are arranged at intervals in the substrate; an edge groove is arranged between the top edge of the shallow trench isolation structure and the active region;
s103: forming a first dielectric layer on the upper surface of the active region;
s104: forming a hard mask layer on the upper surface of the first dielectric layer and the upper surface of the shallow trench isolation structure; the hard mask layer fills the edge groove;
s105: forming a second dielectric layer on the upper surface of the hard mask layer;
s106: etching the second dielectric layer and the hard mask layer to obtain a patterned dielectric layer and a patterned hard mask layer, wherein openings are formed in the patterned dielectric layer and the patterned hard mask layer, and the openings expose part of the upper surface of the first dielectric layer, part of the shallow trench isolation structure and part of the side trench; the exposed side groove is internally provided with a residual hard mask layer;
s107: and removing the residual hard mask layer.
In step S101, referring to step S101 in fig. 4 and fig. 5, a substrate 10 is provided.
The substrate 10 may include, but is not limited to, at least one of a silicon substrate, a gallium arsenide substrate, a gallium nitride substrate, and a silicon carbide substrate, and specifically, the substrate 10 may be any one of a silicon substrate, a gallium arsenide substrate, a gallium nitride substrate, and a silicon carbide substrate, or may be a composite substrate in which two or more thereof are combined, and the embodiment is not limited thereto.
In step S102, referring to step S102 in fig. 4 and fig. 5, shallow trench isolation structures 101 are formed in the substrate 10, and the shallow trench isolation structures 101 isolate a plurality of active regions 102 arranged at intervals in the substrate 10; a side trench 1011 is provided between the top edge of the shallow trench isolation structure 101 and the active region 102.
The insulating dielectric material filled in the shallow trench isolation structure 101 (Shallow Trench Isolation, STI) may be one or more of silicon dioxide, fluorosilicone glass, undoped Silicate Glass (USG), or tetraethyl orthosilicate.
In step S103, referring to step S103 in fig. 4 and fig. 6, a first dielectric layer 20 is formed on the upper surface of the active region 102.
In step S104, referring to step S104 in fig. 4 and fig. 7, a hard mask layer 30 is formed on the upper surface of the first dielectric layer 20 and the upper surface of the shallow trench isolation structure 101; the hard mask layer 30 fills the edge trench 1011.
Wherein the Hard Mask layer (HM) 30 is selected from titanium nitride (TiN), silicon nitride (SiN), silicon dioxide (SiO) 2 ) One or more combinations thereof.
For convenience of explanation of the present embodiment, the shallow trench isolation structure 101 is shown in fig. 4 to be higher than the first dielectric layer 20, so that the hard mask layer above the shallow trench isolation structure 101 has a certain level difference from the hard mask layer above the first dielectric layer 20. Of course, in an actual application scenario, the hard mask layer above the shallow trench isolation structure 101 and the hard mask layer above the first dielectric layer 20 may be level, or the hard mask layer above the shallow trench isolation structure 101 may be lower than the hard mask layer above the first dielectric layer 20, which is not limited herein.
In step S105, referring to step S105 in fig. 4 and fig. 8, a second dielectric layer 40 is formed on the upper surface of the hard mask layer 30.
Alternatively, the first dielectric layer 20 and the second dielectric layer 40 may be prepared by using the same process steps and the same process tools; further, the thicknesses of the first dielectric layer 20 and the second dielectric layer 40 may be the same.
In step S106, referring to step S106 in fig. 4 and fig. 9, the second dielectric layer 40 and the hard mask layer 30 are etched to obtain a patterned dielectric layer 401 and a patterned hard mask layer 301, and openings 402 are formed in the patterned dielectric layer 401 and the patterned hard mask layer 301, wherein the openings 402 expose a portion of the upper surface of the first dielectric layer 20, a portion of the shallow trench isolation structure 101 and a portion of the side trench 1011; the exposed edge trench 1011 has a residual hard mask layer 302 therein.
It should be understood that the shape of the opening 402 and the exposed area of the opening 402 shown in fig. 9 are only for convenience of describing the present embodiment, and the present embodiment is not limited herein, and the opening 402 may have other shapes or expose other different areas in a practical application environment.
In step S107, referring to step S107 in fig. 4 and fig. 10, the residual hard mask layer 302 is removed.
Because the residual hard mask layer in the side groove 1011 is exposed, and the patterned dielectric layer 401 is covered on the patterned hard mask layer 301 at this time, the patterned hard mask layer 302 can be removed while the residual hard mask layer 302 is kept due to the protection effect of the patterned dielectric layer 401, so that the residual hard mask layer 302 in the exposed side groove can be completely removed without damaging the structure of the patterned hard mask layer.
According to the preparation method of the semiconductor structure, the shallow trench isolation structure is formed in the substrate, and a plurality of active areas which are arranged at intervals are isolated in the substrate by the shallow trench isolation structure; an edge groove is arranged between the top edge of the shallow trench isolation structure and the active region; forming a first dielectric layer on the upper surface of the active region; forming a hard mask layer on the upper surface of the first dielectric layer and the upper surface of the shallow trench isolation structure; the hard mask layer fills the edge groove; forming a second dielectric layer on the upper surface of the hard mask layer; etching the second dielectric layer and the hard mask layer to obtain a patterned dielectric layer and a patterned hard mask layer, wherein openings are formed in the patterned dielectric layer and the patterned hard mask layer, and the openings expose part of the upper surface of the first dielectric layer, part of the shallow trench isolation structure and part of the side trench; the exposed side groove is internally provided with a residual hard mask layer; therefore, the residual hard mask layer in the exposed side groove can be removed, the residual hard mask layer is difficult to remain in the cleaning groove in the subsequent process steps, and the cleaning liquid in the cleaning groove is not required to be replaced frequently, so that the cost can be reduced.
Referring to fig. 11, in one embodiment, the method for fabricating a semiconductor structure of the present invention may further include the following steps:
s1101: removing the patterned dielectric layer and the exposed first dielectric layer to expose part of the active region;
s1102: and forming a gate dielectric layer on the exposed upper surface of the active region.
In step S1101, referring to step S1101 in fig. 11 and fig. 12, the patterned dielectric layer 401 and the exposed first dielectric layer 20 are removed to expose a portion of the active region 102.
In step S1102, referring to step S1102 in fig. 11 and fig. 13, a gate dielectric layer 50 is formed on the exposed upper surface of the active region 102.
The Gate dielectric layer 50 may include a Gate Oxide (GOX). Alternatively, the gate oxide layer may be formed by a furnace process, or other oxidation processes, which is not limited herein.
Referring to fig. 14, in an embodiment, after the step S1002, the method may further include the following steps:
s1401: forming a gate structure 60 on the upper surface of the gate dielectric layer 50;
s1402: source and drain regions are formed in the active region 102 on opposite sides of the gate structure 60.
In step S1401, referring to step S1401 in fig. 14 and fig. 15, a gate structure 60 is formed on the upper surface of the gate dielectric layer 50.
In step S1402, referring to step S1402 in fig. 14 and fig. 15, source regions (not shown) and drain regions (not shown) are formed in the active region 102 on opposite sides of the gate structure 60.
In one embodiment, the material of the first dielectric layer 20, the material of the second dielectric layer 40, and the material of the shallow trench isolation structure 101 are the same.
Based on the above embodiment, in one embodiment, the first dielectric layer 20 includes a silicon oxide layer, the second dielectric layer 40 includes a silicon oxide layer, the hard mask layer 30 includes a silicon nitride layer, and the shallow trench isolation structure 101 includes a silicon oxide isolation structure.
Based on the above embodiment, in one embodiment, the step S107 includes: the patterned dielectric layer 401 is used as a protective layer of the patterned hard mask layer 301, and the residual hard mask layer 302 is removed by using a first wet cleaning process.
The wet cleaning refers to a cleaning mode requiring the introduction of cleaning liquid, the wet cleaning can comprise steam cleaning, solution soaking cleaning, rotary spraying cleaning and the like, the cleaning liquid of the wet cleaning can comprise deionized water, acid cleaning liquid and the like, and when the wet cleaning process is carried out, the corresponding cleaning liquid can be selected according to the material to be removed for the wet cleaning. For example, when it is desired to remove silicon oxide, an acidic cleaning liquid such as phosphoric acid or the like can be generally used; where removal of silicon nitride is desired, a hydrofluoric acid diluent (Diluted Hydrofluoric Acid, DHF) or the like may typically be used. Different cleaning solutions cannot be mixed, different cleaning tanks are needed to be used for storage, in order to save cost, cleaning solutions in wet cleaning are needed to be used repeatedly for a plurality of times, if small-particle residues exist in the cleaning solutions, the residues can easily fall onto other wafers randomly in the next cleaning process to pollute the wafers, and the subsequent production process steps of the wafers are greatly influenced, so that the purity of the cleaning solutions is very important.
Based on the above embodiment, in one embodiment, the step S1101 includes: the patterned dielectric layer 401 and the exposed first dielectric layer 20 are removed simultaneously using a second wet cleaning process.
It should be noted that, since the material of the first dielectric layer 20 is the same as the material of the second dielectric layer 40, the material of the patterned dielectric layer 401 is also the same as the exposed first dielectric layer 20, so that the patterned dielectric layer 401 and the exposed first dielectric layer 20 can be removed simultaneously by using the second wet cleaning process; in addition, although the material of the first dielectric layer 20 is the same as that of the shallow trench isolation structure 101, the material filled in the shallow trench isolation structure 101 is slightly lost when the second wet cleaning process is performed, in the actual process, the thickness of the first dielectric layer 20 is thinner, and the second wet cleaning process is not performed for a long time, so that the loss of the shallow trench isolation structure 101 is almost negligible and the performance of the semiconductor device formed later is not affected.
On the basis of the above embodiments, in one embodiment, the cleaning solution of the first wet cleaning process includes phosphoric acid; the cleaning solution of the second wet cleaning process comprises hydrofluoric acid diluent.
In one embodiment, in step S106, the second dielectric layer 40 and the hard mask layer 30 are etched by a dry etching process.
The hard mask layer 30 can be used as an etching stop layer of the second dielectric layer 40 for etching when the second dielectric layer 40 is etched; after the etching of the second dielectric layer 40 is completed, the first dielectric layer 20 is etched as an etching stop layer of the hard mask layer 30 when the hard mask layer 30 is etched. Both etching processes can be performed in the same dry etching machine, and can be realized by only changing main etching gas (main gas).
Referring to fig. 16, in one embodiment, the step S106 includes:
s1061: forming a photoresist layer on the upper surface of the second dielectric layer;
s1062: patterning the photoresist layer to obtain a patterned photoresist layer;
s1063: and etching the second dielectric layer and the hard mask layer based on the patterned photoresist layer to obtain the patterned dielectric layer and the patterned hard mask layer.
In step S1061, referring to step S1061 of fig. 16 and fig. 17, a photoresist layer 70 is formed on the upper surface of the second dielectric layer 40.
In step S1062, referring to step S1062 in fig. 16 and fig. 18, the photoresist layer 70 is patterned to obtain a patterned photoresist layer 701.
In step S1063, referring to step S1063 in fig. 16 and fig. 19, the second dielectric layer 40 and the hard mask layer 30 are etched based on the patterned photoresist layer 701 to obtain the patterned dielectric layer 401 and the patterned hard mask layer 301.
In one embodiment, after the step S1063, the following steps may be further included: the patterned photoresist layer 701 is removed to form the structure resulting from step S106.
In the description of the present specification, reference to the terms "some embodiments," "other embodiments," "desired embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (10)
1. A method of fabricating a semiconductor structure, comprising:
providing a substrate;
forming a shallow trench isolation structure in the substrate, wherein the shallow trench isolation structure isolates a plurality of active areas which are arranged at intervals in the substrate; an edge groove is formed between the top edge of the shallow groove isolation structure and the active region;
forming a first dielectric layer on the upper surface of the active region;
forming a hard mask layer on the upper surface of the first dielectric layer and the upper surface of the shallow trench isolation structure; the hard mask layer fills the side groove;
forming a second dielectric layer on the upper surface of the hard mask layer;
etching the second dielectric layer and the hard mask layer to obtain a patterned dielectric layer and a patterned hard mask layer, wherein openings are formed in the patterned dielectric layer and the patterned hard mask layer, and the openings expose part of the upper surface of the first dielectric layer, part of the shallow trench isolation structure and part of the side trench; the exposed side grooves are internally provided with residual hard mask layers;
and taking the patterned dielectric layer as a protective layer of the patterned hard mask layer, and removing the residual hard mask layer by using a first wet cleaning process.
2. The method of manufacturing a semiconductor structure of claim 1, further comprising:
removing the patterned dielectric layer and the exposed first dielectric layer to expose part of the active region;
and forming a gate dielectric layer on the exposed upper surface of the active region.
3. The method of claim 2, further comprising, after forming a gate dielectric layer on the exposed upper surface of the active region:
forming a grid structure on the upper surface of the grid dielectric layer;
and forming a source region and a drain region in the active region at two opposite sides of the gate structure.
4. The method of claim 2, wherein the material of the first dielectric layer, the material of the second dielectric layer, and the material of the shallow trench isolation structure are the same.
5. The method of claim 4, wherein the first dielectric layer comprises a silicon oxide layer, the second dielectric layer comprises a silicon oxide layer, the hard mask layer comprises a silicon nitride layer, and the shallow trench isolation structure comprises a silicon oxide isolation structure.
6. The method of claim 1, wherein the substrate is a silicon substrate.
7. The method of claim 6, wherein removing the patterned dielectric layer and the exposed first dielectric layer comprises:
and simultaneously removing the patterned dielectric layer and the exposed first dielectric layer by using a second wet cleaning process.
8. The method of claim 7, wherein the cleaning solution of the first wet cleaning process comprises phosphoric acid; the cleaning solution of the second wet cleaning process comprises hydrofluoric acid diluent.
9. The method of claim 1, wherein the second dielectric layer and the hard mask layer are etched using a dry etching process.
10. The method for manufacturing a semiconductor structure according to claim 1, wherein the etching the second dielectric layer and the hard mask layer to obtain a patterned dielectric layer and a patterned hard mask layer comprises:
forming a photoresist layer on the upper surface of the second dielectric layer;
patterning the photoresist layer to obtain a patterned photoresist layer;
and etching the second dielectric layer and the hard mask layer based on the patterned photoresist layer to obtain the patterned dielectric layer and the patterned hard mask layer.
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| RU2252768C1 (en) * | 2004-01-05 | 2005-05-27 | Чаков Владимир Владимирович | Method for production of peloid water extract |
| CN102148181A (en) * | 2010-02-10 | 2011-08-10 | 上海宏力半导体制造有限公司 | Method for forming shallow trench isolation structure |
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| RU2252768C1 (en) * | 2004-01-05 | 2005-05-27 | Чаков Владимир Владимирович | Method for production of peloid water extract |
| CN102148181A (en) * | 2010-02-10 | 2011-08-10 | 上海宏力半导体制造有限公司 | Method for forming shallow trench isolation structure |
| JP2014027110A (en) * | 2012-07-26 | 2014-02-06 | Fujitsu Semiconductor Ltd | Semiconductor device manufacturing method |
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