CN115828841A - Integrated design method of system-level built-in self test based on boundary scan chain - Google Patents

Abstract

The invention discloses an integrated design method of system-level built-in self test based on a boundary scan chain, belonging to the field of testability design of integrated circuits. Inserting a BSC unit under an I/O port related to built-in self-test of the IP core to form a built-in self-test boundary scan chain of the IP core; adding a BIST JTAG instruction in an SoC system level TAP controller, wherein the JTAG user-defined instruction is specially used for built-in self-test of an IP core; an IP core built-in self-test boundary scan chain is integrated into a system level TAP controller. When the testability design of the large-scale integrated circuit is carried out, the method can greatly reduce the consumption of the I/O port, effectively avoid the generation of redundant test logic, realize simple and efficient IP core built-in self test at a system level and greatly reduce the design complexity.

Description

Integrated design method of system-level built-in self test based on boundary scan chain

Technical Field

The invention relates to the technical field of integrated circuit design for test (DFT), in particular to an integrated design method of a system level built-in self test (BIST) based on a boundary scan chain.

Background

With the technological progress of integrated circuits, the manufacturing process is developed from micron level to deep submicron, ultra deep submicron and nanometer level; LSI (large scale integrated circuit), VLSI (very large scale integrated circuit), ULSI (ultra large scale integrated circuit), GSI (very large scale integrated circuit) are appearing in succession, the integration level is continuously improved, the scale of silicon single chip transistors has reached billions, the number of I/O pins has sharply increased, and the power consumption has also increased. In addition, the continuous increase of the integrated scale of the silicon single chip also leads to the test of the chip becoming more complicated and the test cost is increasing, and according to incomplete statistics, the test cost can almost match with the silicon chip manufacturing cost, even exceeds the silicon chip manufacturing cost, which is obviously unacceptable. Thus, the testing problem becomes more stringent.

Aiming at the high-speed development of integrated circuits, designers design circuits according to functional and performance requirements, and testers make test schemes according to the designed or developed circuits, so that the traditional practice is not suitable for the requirements of actual production. This requires designers to design circuits and consider the requirements of testing, i.e. the criteria for evaluating a circuit not only has the advantages and disadvantages of implementing functions and performance, but also whether the designed circuit is easy to test, which is the DFT testability design technique.

Boundary scan chain based testing is a common approach in design for testability. Originally, boundary scan testing was only used for board level system testing, and with the gradual and intensive research and popularization, it has been widely applied in testing integrated circuits, and at present, it is increasingly applied to built-in self-test of silicon single chip.

The basic principle of the boundary scanning technology is that a boundary scanning unit (BSC) is added at the input end and the output end of a core logic circuit, and the BSC mainly comprises a trigger and an alternative multiplexer, and the boundary scanning units have the following characteristics: each unit can input data and also can output data; all boundary scan cells may be connected into one boundary scan shift register (BSR). Due to the addition of the shift registers, core logic test and test of connecting lines between integrated circuit components or PCB board level systems can be realized.

Since the development of integrated circuit manufacturing is ahead of design, in order to speed up the integrated circuit design, a system on chip (SoC) design based on Intellectual Property (IP) cores becomes the mainstream of design, so that the testability of the IP cores is considered at the beginning of the design, specifically, the design includes controllable, observable, high test coverage, no excessive consumption of I/O port resources, easy integration of testability logic at the SoC system level, and the like. In a large SoC design, there are often many IP cores, and the testability integrated design method of the SoC system level directly determines the quality of the testability design of the IP cores and the system core logic. Therefore, a design method for testability integration is urgently needed at a system level, and the testability design of an IP core is integrated into the system level testability design by using minimum I/O port resources and simple and easy-to-implement testability design logic.

Disclosure of Invention

The invention aims to provide an integrated design method of system-level built-in self test based on a boundary scan chain, which aims to solve the problem of testability design in the background technology.

In order to solve the technical problem, the invention provides an integrated design method of system-level built-in self test based on a boundary scan chain, which comprises the following steps:

inserting a BSC unit under an I/O port related to built-in self-test in the IP core to form a boundary scan chain, wherein the built-in self-test boundary scan chain of the IP core is specially used for built-in self-test of the IP core;

adding a user instruction, namely a BIST test instruction in the SoC system level TAP controller, wherein the user-defined JTAG instruction is specially used for built-in self-test of an IP core; meanwhile, instruction decoding logic is added, the built-in self-test boundary scan chain of the IP core is arranged between the TDI and TDO ends of the SoC system level TAP controller, and the IP core is arranged in a BIST test mode;

an IP core built-in self-test boundary scan chain is integrated into a system level TAP controller.

Optionally, before the BSC unit is inserted into the IP core under the I/O port related to the built-in self-test to form a built-in self-test boundary scan chain, the method further includes: the connection between the I/O port related to built-in self-test of the IP core and the internal logic is cut off, then the BSC unit is inserted, and a new connection is established between the I/O port and the internal logic, so that a test path is added between the I/O port and the internal logic through the new connection, and the normal working mode of the circuit is not influenced.

Optionally, the boundary scan chain is formed by sequentially connecting the serial input TDI and the serial output TDO of the BSC unit in series; the shift enable ShiftDR, the scan clock ClockDR and the refresh clock UpdataDR are connected to the system-level TAP controller in parallel to form a built-in self-test boundary scan chain controlled by the system-level TAP controller, so that the operations of parallel capture, serial scan shift, parallel refresh and the like under the related instructions of the system-level JTAG can be executed, and the related BIST test can be completed.

Optionally, the built-in self-test boundary scan chain in the IP core is formed by connecting BSC units under I/O ports related to built-in self test in the IP core in series, and this boundary scan chain is specially used for built-in self test of the IP core.

Optionally, for unidirectional input or output I/O, a BSC unit needs to be inserted; for bi-directional input or output I/O, three BSC units need to be inserted. For the BIST test, the corresponding I/O ports are all unidirectional, only one BSC unit needs to be inserted, test excitation can be input through scanning of the BSC unit under the input I/O port, and test results are output through scanning of the BSC unit under the output I/O port.

Optionally, a self-test boundary scan chain is built in the IP core, and is controlled by the system level TAP controller to execute a related JTAG instruction, perform operations such as capture, scan shift, refresh, and complete a related BIST test.

Optionally, the user-defined JTAG instruction is specially used for built-in self-test of the IP core, and is a user instruction and a BIST test instruction are added to the SoC system level TAP controller, and the JTAG user instruction is specially used for built-in self-test of the IP core.

Optionally, the integration of the IP core built-in self-test boundary scan chain into the system-level TAP controller includes integration of the serial input terminal TDI and the serial output terminal TDO of the IP core built-in self-test boundary scan chain, and integration of the parallel input terminals of the IP core built-in self-test boundary scan chain.

The invention has the following beneficial effects:

(1) The BSC unit is directly inserted below an I/O port related to built-in self test of the IP core to form an IP core built-in self test boundary scan chain, the scan chain is controlled by an SoC system level TAP controller, related TAP controller logic does not need to be implanted into the IP core, redundant logic can be effectively reduced, meanwhile, BIST related test signals are controlled by the boundary scan chain and do not need to be led out to an external port of a chip, and the consumption of I/O port resources is greatly reduced; for an SoC chip, the number of IPs is quite large, and the advantage is more obvious;

(2) By connecting the built-in self-test boundary scan chain of the IP core to the system-level JTAG controller at the system level of the SoC, the design complexity is greatly reduced under the control of only one TAP controller at the system level.

Drawings

FIG. 1 is a schematic diagram of an IP core built-in self-test system architecture including an IP core built-in self-test boundary scan chain and a connection to a SoC system-level TAP controller.

FIG. 2 is a schematic diagram of a boundary scan cell structure, including two types, the "scan/capture, refresh" boundary scan cell shown in FIG. 2-1 for input I/O ports, and the "scan/capture" boundary scan cell shown in FIG. 2-2 for output I/O ports.

Detailed Description

The method for designing an integration of a boundary scan chain based system level built-in self test according to the present invention is described in detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

The embodiment of the invention provides an integrated design method of system-level built-in self test based on a boundary scan chain, which comprises the following steps:

(1) Inserting a BSC unit under an I/O port related to built-in self-test of the IP core to form a boundary scan chain, wherein the boundary scan chain is specially used for the built-in self-test of the IP core;

before inserting the BSC unit under the I/O port related to built-in self-test in the IP core, the connection line between the I/O port related to built-in self-test in the IP core and the internal logic is cut off, and then the BSC unit is inserted to establish a new connection between the I/O port and the internal logic.

(2) Adding a user instruction, namely a BIST test instruction in the SoC system level TAP controller, wherein the user-defined JTAG instruction is specially used for built-in self-test of an IP core;

when the SoC system-level JTAG controller runs the BIST instruction, a control signal for a DR register generated by an instruction decoder needs to select the built-in self-test boundary scan chain of the IP core and place the self-test boundary scan chain between TDI and TDO two ends of the SoC system-level TAP controller; a Bist _ mode signal is also generated, placing the IP core in a BIST test mode.

When the BIST test instruction is added, the number of JTAG instructions needs to be expanded, and the IR value is added by one, so that the BIST test instruction is specially used for built-in self test of an IP core.

The control signal generated by the instruction decoder is used for selecting the IP core built-in self-test boundary scan chain and placing the IP core built-in self-test boundary scan chain between TDI and TDO ends of the SoC system-level TAP controller.

The generating of the Bist _ mode signal places the IP core in a BIST test mode, when the BIST test instruction is loaded into the instruction register, the instruction decoder needs to generate a control signal Bist _ mode to the BSC unit, once the Bist _ mode is valid, an I/O port and an internal logic function path of the IP core are cut off by the BSC unit, and the BSC unit provides a serial test path for the BIST test to the IP core, wherein the test excitation is input through TDI scanning, and the test result is output through TDO scanning.

(3) An IP core built-in self-test boundary scan chain is integrated into a system level TAP controller.

The integration method of the serial input end TDI and the serial output end TDO of the self-test boundary scan chain built in the IP core comprises the following steps:

a data path is added between the TDI and TDO ends of the SoC system level TAP controller, and an IP core built-in self-test boundary scan chain is arranged between the TDI and TDO ends. The serial input end of the self-test boundary scan chain built in the IP core is directly connected with the TDI end, the TDI signal drives the serial input end of the edge boundary scan chain in a one-push-multiple mode, the serial output end of the self-test boundary scan chain built in the IP core is connected to the TDO end through 2 MUX data selectors, and the gating signal MUX _ sel of the MUX (DRn) is driven by the output signal of the instruction decoder.

The method for integrating the parallel input ends of the built-in self-test boundary scan chains of the IP core comprises the following steps:

the scan shift control signal ShiftDR, the scan/capture gating clock signal ClockDR, the refresh gating clock signal UpdataDR and the like of each BSC unit on the built-in self-test boundary scan chain of the IP core are connected to an SoC system-level TAP controller in parallel, and the working mode control signal Bist _ mode is connected to an instruction decoder unit of an Instruction Register (IR) in parallel, so that the integrated design of the built-in self-test boundary scan chain of the IP core on a system level is completed and is controlled by the system-level TAP controller.

Fig. 1 shows a schematic diagram of an integrated design of an IP core built-in self-test boundary scan chain, which includes a 5-wire JTAG port, a system-level TAP controller, an IP core built-in self-test boundary scan chain, a chip I/O port boundary scan chain, and the like.

The BSC unit inserted under the I/O port related to self-test built in the IP core is shown in FIG. 2, for the input I/O, it needs to capture the initial value of the BIST test signal and scan-shift-in test excitation, and refresh to the BIST input port (Bist _ in [1:n ]), so the "scan/capture, refresh" boundary scan unit shown in FIG. 2-1 is adopted; for output I/O, it is only necessary to capture the test response result at the BIST output port (Bist _ out [1:m-n ]) and scan out, so the "scan/capture" boundary scan cell shown in FIG. 2-2 is used.

In fig. 1, the length of the self-test boundary scan chain built in the IP core is m, the serial BSC units #1 to # n correspond to the BIST input signal (BIST _ in [1:n ]), and the serial BSC units # n +1 to # m correspond to the BIST output signal (BIST _ out [1:m-n ]), and are controlled by the system level TAP controller.

The BIST test procedure is as follows:

1. first round of operation (input BIST stimulus)

(1) Write IR, shift "s" times, update to IR register. In this case, the JTAG instruction for conducting the BIST test is written to the IR instruction register.

(2) Write DR, shift "m" times, update to the Bist _ in port. The BIST excitation signal is serially written into a DR data register (self-test boundary scan chain built in an IP core), and the minimum m-n bit data value can be ignored, so that the 0 complementing processing is only needed.

2. Second round of operation (input BIST stimulus)

Operating in the same manner as step one, pulling the BIST enable signal high and the IP core begins to perform a built-in self test. The BIST starting signal is also a synchronous processing signal from the JTAG TCK clock domain to the BIST CLK clock domain.

3. Third round of operation (reading BIST results)

(1) Write IR, operate in the same manner as step one.

(2) Write DR, shift "m" times, observe the result at TDO. Wherein, the value of shift _ in is random, and the result is observed in shift _ out. The value of TDO is mainly observed from 1 st to m-n th shift _ out.

In summary, the three rounds of operations are mainly used to complete the BIST test of the IP core, which can be tested by A Tester (ATE).

When the testability design of the large-scale integrated circuit is carried out, the method can greatly reduce the consumption of the I/O port, effectively avoid the generation of redundant test logic, realize simple and efficient IP core built-in self test at a system level and greatly reduce the design complexity.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (8)

1. An integrated design method of system-level built-in self test based on boundary scan chain is characterized by comprising the following steps:

inserting a BSC unit under an I/O port related to self-test built in an IP core to form a boundary scan chain, wherein the self-test boundary scan chain is built in the IP core and is specially used for the built-in self-test of the IP core;

adding a user instruction, namely a BIST test instruction in the SoC system level TAP controller, wherein the user-defined JTAG instruction is specially used for built-in self-test of an IP core;

an IP core built-in self-test boundary scan chain is integrated into a system level TAP controller.

2. The method of claim 1, wherein before inserting a BSC unit under an I/O port associated with built-in self-test in the IP core to form a built-in self-test boundary scan chain, the method further comprises: the connection between the I/O port related to built-in self test of the IP core and the internal logic is cut off, then the BSC unit is inserted, and a new connection is established between the I/O port and the internal logic, so that a test path is added between the I/O port and the internal logic through the new connection, and the normal working mode of the circuit is not influenced.

3. The integrated design method for system level built-in self test based on boundary scan chain as claimed in claim 1, wherein the boundary scan chain is formed by connecting serial input TDI and serial output TDO of BSC unit in series; the shift enable ShiftDR, the scan clock ClockDR and the refresh clock UpdateDR are connected to the system-level TAP controller in parallel to form a built-in self-test boundary scan chain controlled by the system-level TAP controller, and the shift enable ShiftDR, the scan clock ClockDR and the refresh clock UpdateDR can execute parallel capture, serial scan shift and parallel refresh operations under a system-level JTAG related instruction and complete a related BIST test.

4. The method for integrated design of boundary scan chain based system level built-in self test of claim 1, wherein the IP core built-in self test boundary scan chain is formed by connecting IP core built-in self test related I/O port lower BSC units in series, this edge boundary scan chain being dedicated for built-in self test of IP core.

5. The integrated design method for boundary scan chain based system-level built-in self test as claimed in claim 1, wherein for unidirectional input or output I/O, a BSC unit needs to be inserted; for bidirectional input or output I/O, three BSC units need to be inserted; for the BIST test, the corresponding I/O ports are all unidirectional, only one BSC unit needs to be inserted, test excitation can be input through scanning of the BSC unit under the input I/O port, and test results are output through scanning of the BSC unit under the output I/O port.

6. The integrated design method for boundary scan chain-based system-level built-in self-test as claimed in claim 1, wherein the IP core built-in self-test boundary scan chain is controlled by the system-level TAP controller to execute related JTAG instructions, perform capture, scan shift, refresh operations, and complete related BIST tests.

7. The method of claim 1, wherein the user-defined JTAG instruction is dedicated to IP core built-in self-test, and a user instruction is added to the SoC system level TAP controller, and the BIST test instruction is dedicated to IP core built-in self-test, and when the BIST instruction is executed, the IP core built-in self-test boundary scan chain is selected between TDI and TDO terminals of the SoC system level TAP controller, and a Bist _ mode signal is generated to place the IP core in BIST test mode.

8. The method of claim 1, wherein the integration of the IP core built-in self-test boundary scan chain into the system-level TAP controller comprises an integration of a serial input TDI and a serial output TDO of the IP core built-in self-test boundary scan chain, and an integration of a parallel input of the IP core built-in self-test boundary scan chain.

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