CN115828811A - Method and device for realizing hardware pause mechanism in FPGA (field programmable Gate array) configuration process - Google Patents

Abstract

The invention provides a method and a device for realizing a hardware pause mechanism in an FPGA (field programmable gate array) configuration process. The method comprises the following steps: firstly, a slave interface SI port analyzes a first bit stream to obtain a pause position in the first bit stream; then, the SI end adds a corresponding pause frame to the pause position in the first bitstream to obtain the second bitstream; then, the SI end stores the second bit stream into a first-in first-out data buffer FIFO; then, when the host interface MI end reads the second bit stream from the FIFO, if a pause frame is read out, loading the pause time indicated by the pause frame into a counter, and starting counting down for a pause process; the MI end stops reading data from the FIFO and sending data out until the suspension process is finished. Therefore, the current configuration process can be suspended in the FPGA configuration process, and the subsequent configuration process can be continued after the previous configuration process is finished.

Description

Method and device for realizing hardware pause mechanism in FPGA (field programmable Gate array) configuration process

Technical Field

One or more embodiments of the present disclosure relate to the field of integrated circuit design technologies, and in particular, to a method and an apparatus for implementing a hardware suspension mechanism in an FPGA configuration process.

Background

At present, in a process of using a Field Programmable Gate Array (FPGA) chip, an electronic Automation Design (EDA) tool first converts a user Design file into a bitstream file and then downloads the bitstream file into the FPGA chip to complete a Design function, which is called as a configuration process of the FPGA.

However, in the FPGA configuration process, because a certain timing requirement needs to be met, in some configuration processes, a pause needs to be made for a period of time to wait for the previous configuration process to end before continuing the subsequent configuration. The original configuration process cannot be suspended. If the previous configuration process is not completed, a certain delay effect can only be achieved by inserting redundant invalid configuration frames.

Disclosure of Invention

The invention describes a method and a device for realizing a hardware pause mechanism in an FPGA (field programmable gate array) configuration process, which can solve the technical problem.

According to a first aspect, a method for implementing a hardware suspension mechanism in an FPGA configuration process is provided.

The method comprises the following steps:

analyzing the first bit stream by the slave interface SI end to obtain a pause position in the first bit stream; adding a corresponding pause frame at the pause position in the first bit stream by the SI end to obtain a second bit stream; the SI end stores the second bit stream into a first-in first-out data buffer; when the host interface MI end reads the second bit stream from the FIFO, if a pause frame is read out, loading the pause time indicated by the pause frame into a counter, and starting counting down for a pause process; the MI end stops reading data from the FIFO and sending data out until the suspension process is finished.

In some embodiments, before the slave interface SI-side parses the first bit stream, the method further comprises: and the SI terminal acquires the first bit stream from a configuration bus, wherein the first bit stream is obtained by converting a user design file by using an electronic automation design (EDA) tool.

In some embodiments, during the pause, the SI end continues to store data into the FIFO until the FIFO is full.

In some embodiments, the MI end continues reading the second bitstream from the FIFO based on the end of the suspension process.

In some embodiments, if a non-pause frame is read out, the non-pause frame is transmitted to a Field Programmable Gate Array (FPGA) chip to configure the FPGA chip.

According to a second aspect, an apparatus for implementing a hardware suspension mechanism in an FPGA configuration process is provided.

The device includes:

the first bit stream analyzing module is used for analyzing the first bit stream through the SI end of the slave machine interface to obtain a pause position in the first bit stream; a second bitstream obtaining module, configured to add, by the SI terminal, a corresponding pause frame at the pause position in the first bitstream, to obtain a second bitstream; the data buffer storage module is used for storing the second bit stream into a first-in first-out data buffer FIFO through the SI end; a second bit stream reading module, configured to, when the host interface MI reads the second bit stream from the FIFO, if a pause frame is read out, load a pause time indicated by the pause frame into a counter, and start counting down for a pause process; stopping reading data from the FIFO and sending data out through the MI end until the pause process is finished.

In some embodiments, the apparatus further comprises:

and the first bit stream acquisition module is used for acquiring the first bit stream from a configuration bus through the SI end, wherein the first bit stream is obtained by converting a user design file by using an electronic automation design (EDA) tool.

In some embodiments, the second bitstream reading module is further configured to:

and in the pause process, continuing to store data into the FIFO through the SI end until the FIFO is full.

In some embodiments, the second bitstream reading module is further configured to:

continuing to read the second bitstream from the FIFO through the MI end based on the end of the pause process.

In some embodiments, the second bitstream reading module is further configured to:

and if the read non-pause frame is read out, transmitting the non-pause frame to a Field Programmable Gate Array (FPGA) chip to configure the FPGA chip.

In the above method and apparatus provided by the embodiments of the present specification, the pause frame is added to the profile bitstream, and the pause process is controlled by the counter during reading the bitstream. The method can realize that the FPGA configuration process is suspended for a period of time and the configuration process is ended, and the subsequent configuration is continued to meet the requirements of certain configuration processes on time sequence.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a flowchart illustrating a method for implementing a hardware suspension mechanism in an FPGA configuration process according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram illustrating a method for implementing a hardware suspension mechanism in an FPGA configuration process according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram illustrating an apparatus for implementing a hardware suspension mechanism in an FPGA configuration process according to an embodiment of the present disclosure.

Detailed Description

The scheme provided by the specification is described below with reference to the accompanying drawings.

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the embodiments of the present application will be described below with reference to the accompanying drawings.

In the description of the embodiments of the present application, the words "exemplary," "for example," or "for instance" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary," "e.g.," or "e.g.," is not to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the words "exemplary," "e.g.," or "exemplary" is intended to present relevant concepts in a concrete fashion.

In the description of the embodiments of the present application, the term "and/or" is only one kind of association relationship describing an associated object, and means that three relationships may exist, for example, a and/or B may mean: a exists alone, B exists alone, and A and B exist at the same time. In addition, the term "plurality" means two or more unless otherwise specified.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit indication of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless expressly specified otherwise.

Fig. 1 is a flowchart illustrating a method for implementing a hardware suspension mechanism in an FPGA configuration process according to an embodiment of the present disclosure, where as shown in fig. 1, the method includes the following steps:

step S110, a Slave Interface SI (Slave Interface, SI for short) port parses the first bit stream to obtain a pause position in the first bit stream.

In some embodiments, prior to this step, the method further comprises: the SI terminal acquires a first bit stream from the configuration bus, wherein the first bit stream is obtained by converting a user design file by using an electronic automation design (EDA) tool.

In some embodiments, the SI side has several positions in the first bit stream that need to be paused, and the later configuration process can not be continued until the pause is set for a specified time.

In some more specific embodiments, the composition of the first bit stream is illustrated by taking the configuration process of an FPGA chip produced by Xilinx as an example, and the configuration data is composed of frames (frames), which are the smallest addressing units in the configuration data, and are 1 bit wide, and the height of the chip used is long.

The bit, i.e., bitstream file, is in binary format and contains header redundancy information, configuration data stream, and trailer redundancy information.

In which the length of the header redundancy information is uncertain and is about 72 bytes or so. The second part is a configuration data stream, beginning with 0xFF FF AA 99 55, the specific format and meaning of which can be found in reference FPGA parameter literature.

The last part is tail redundancy information, which is specified by 16 32-bit no-operation instructions: 0x20 00 0000. These no-op instructions indicate that no-op is to be performed. This part of the information may not be loaded into the FPGA.

Illustratively, these no-op instructions in the first bitstream are locations that need to be paused.

Step S120, the SI end adds a corresponding pause frame to the pause position in the first bitstream to obtain a second bitstream.

In some embodiments, the parsed pause location is marked with a pause frame, including a pause location and a pause time, to convert the first bitstream into the second bitstream. The second bitstream thus contains data frames and pause frames.

Illustratively, the format of the pause frame is not limited, and only the corresponding pause time needs to be indicated.

In step S130, the SI side stores the second bit stream into a First-In First-Out data buffer FIFO (First In First Out, FIFO for short).

In some embodiments, the SI side may send a write request to the FIFO before storing the second bitstream in the FIFO, and then send the second bitstream after receiving a response message from the FIFO indicating that writing is allowed.

Step S140, when the MI (Master Interface, abbreviated as MI) end of the host Interface reads the second bitstream from the FIFO, if the read-out is a pause frame, loading the pause time indicated by the pause frame into the counter, and starting to count down for the pause process; the MI end stops reading data from the FIFO and sending data out until the pause process is finished.

In some embodiments, the performing of this step comprises: during the pause, the SI end continues to store data into the FIFO until the FIFO storage space is full.

In some embodiments, the performing of this step comprises: at the end of the pause process, the MI end continues reading the second bitstream from the FIFO.

In some embodiments, the performing of this step further comprises: and if the read non-pause frame is read out, transmitting the non-pause frame to the FPGA chip of the field programmable logic gate array to configure the FPGA chip.

Illustratively, the bit width of the counter is not limited, and may be set according to actual needs.

Fig. 2 is a schematic diagram illustrating an implementation method of a hardware suspension mechanism in an FPGA configuration process according to an embodiment of the present disclosure. The solution according to the invention is described further below with reference to fig. 2.

The SI end receives a first bit stream wdata obtained by converting a user design file by using an EDA tool and acquired from a configuration bus, analyzes the first bit stream and adds a pause Frame (Frame parse) to obtain a second bit stream data + addr, wherein the addr represents the position of the pause Frame. The SI end sends a write operation request wr _ req _ n to the FIFO and starts to write the second bit stream into the FIFO according to a response message which is returned by the FIFO and indicates that the writing is allowed.

The MI side first sends a read operation request rd _ req _ n to the FIFO and then reads the second bit stream stored in the FIFO according to a response message returned by the FIFO indicating that reading is permitted. According to the FIFO first-in first-out characteristic, the bit stream stored first is read out from the MI end first. According to the sequence of storing the second bit stream into the FIFO, when the data frame data is read out, the MI end directly sends out the data frame data to configure the FPGA. When the pause frame addr is read out, the MI side loads the pause frame into the counter and starts counting down, and when the counting down is finished, the pause process is finished. The MI terminal continues reading the second bitstream from the FIFO.

During the pause, the SI end continues to send the bit stream to the FIFO until the FIFO storage space is full. The MI end stops reading data from the FIFO and sending data to the FPGA until the pause process is finished.

Corresponding to the method provided by the invention, the invention also provides a device. Fig. 3 is a schematic structural diagram illustrating an apparatus for implementing a hardware suspension mechanism in an FPGA configuration process according to an embodiment of the present disclosure. As shown in fig. 3, the apparatus S300 includes:

the first bitstream parsing module S320 is configured to parse the first bitstream through the slave interface SI side to obtain a pause position in the first bitstream.

A second bitstream obtaining module S330, configured to add a corresponding pause frame at a pause position in the first bitstream through the SI end, so as to obtain a second bitstream.

And a data buffer storage module S340, configured to store the second bit stream into a first-in-first-out data buffer FIFO through the SI terminal.

A second bit stream reading module S350, configured to, when the host interface MI reads the second bit stream from the FIFO, if a pause frame is read out, load a pause time indicated by the pause frame into the counter, and start counting down for a pause process; the reading of data from the FIFO and the sending of data out is stopped by the MI side until the pause process is finished.

In some embodiments, the apparatus S300 further comprises:

a first bit stream obtaining module S310, configured to obtain a first bit stream from the configuration bus through the SI terminal, where the first bit stream is obtained by converting a user design file with an electronic automation design EDA tool.

In some embodiments, the second bitstream reading module S350 may further be configured to: when the pause process ends, the MI end continues reading the second bitstream from the FIFO.

In some embodiments, the second bitstream reading module S350 may further be configured to: and if the read non-pause frame is read out, transmitting the non-pause frame to the FPGA chip of the field programmable logic gate array to configure the FPGA chip.

It should be noted that, for the description of the apparatus in fig. 3, reference may also be made to the description of the foregoing method.

According to an embodiment of another aspect, there is also provided a computer-readable storage medium having stored thereon a computer program which, when executed in a computer, causes the computer to perform the method described in connection with fig. 1.

According to an embodiment of yet another aspect, there is also provided a computing device comprising a memory having stored therein executable code, and a processor that, when executing the executable code, implements the method described in connection with fig. 1. Those skilled in the art will recognize that, in one or more of the examples described above, the functions described in this invention may be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium.

The above-mentioned embodiments, objects, technical solutions and advantages of the present invention are further described in detail, it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made on the basis of the technical solutions of the present invention should be included in the scope of the present invention.

Claims (10)

1. A method for realizing a hardware pause mechanism in an FPGA configuration process is characterized by comprising the following steps:

analyzing the first bit stream by the slave interface SI end to obtain a pause position in the first bit stream;

adding a corresponding pause frame at the pause position in the first bit stream by the SI end to obtain a second bit stream;

the SI end stores the second bit stream into a first-in first-out data buffer FIFO;

when the host interface MI end reads the second bit stream from the FIFO, if a pause frame is read out, loading the pause time indicated by the pause frame into a counter, and starting counting down for a pause process; the MI end stops reading data from the FIFO and sending data out until the suspension process is finished.

2. The method of claim 1, wherein prior to parsing the first bit stream from the SI port of the slave interface, the method further comprises:

and the SI terminal acquires the first bit stream from a configuration bus, wherein the first bit stream is obtained by converting a user design file by utilizing an electronic automation design (EDA) tool.

3. The method of claim 1, further comprising:

during the pause, the SI end continues to store data into the FIFO until the FIFO is full.

4. The method of claim 1, further comprising:

upon completion of the pause process, the MI end continues to read the second bitstream from the FIFO.

5. The method of claim 1, further comprising:

and if the read non-pause frame is read out, transmitting the non-pause frame to the FPGA chip of the field programmable logic gate array to configure the FPGA chip.

6. An apparatus for implementing a hardware suspension mechanism in an FPGA configuration process, the apparatus comprising:

the first bit stream analyzing module is used for analyzing the first bit stream through the SI end of the slave machine interface to obtain a pause position in the first bit stream;

a second bitstream obtaining module, configured to add, by the SI terminal, a corresponding pause frame at the pause position in the first bitstream, to obtain a second bitstream;

the data buffer storage module is used for storing the second bit stream into a first-in first-out data buffer FIFO through the SI end;

a second bit stream reading module, configured to, when the host interface MI reads the second bit stream from the FIFO, if a pause frame is read out, load a pause time indicated by the pause frame into a counter, and start counting down for a pause process; stopping reading data from the FIFO and sending data out through the MI end until the pause process is finished.

7. The apparatus of claim 6, wherein the apparatus further comprises:

and the first bit stream acquisition module is used for acquiring the first bit stream from a configuration bus through the SI end, wherein the first bit stream is obtained by converting a user design file by using an electronic automation design (EDA) tool.

8. The apparatus of claim 6, the second bitstream reading module further to:

and in the pause process, continuing to store data into the FIFO through the SI end until the FIFO is full.

9. The apparatus of claim 6, the second bitstream reading module further configured to:

continuing to read the second bitstream from the FIFO through the MI end based on the end of the pause process.

10. The apparatus of claim 6, the second bitstream reading module further configured to:

and if the read non-pause frame is read out, transmitting the non-pause frame to a Field Programmable Gate Array (FPGA) chip to configure the FPGA chip.

Images