CN115828804A - Method for modifying RTL source code file and electronic equipment - Google Patents
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Abstract
The application discloses a method and electronic equipment for modifying an RTL source code file, wherein the method comprises the following steps: acquiring all RTL source code files of the design to be tested and file names of top RTL source codes of the design to be tested, associating example names of modules in each RTL source code file with the file names, and storing association results into a tree-shaped data structure; acquiring all signal names corresponding to modules in each RTL source code file one by one and position information corresponding to each RTL source code file in a data structure, and adding prefixes in front of the signal names according to the position information to obtain complete signal names; and selecting at least one signal to be observed from all the complete signals, detecting each signal to be observed in the signal list to be observed one by one to obtain a detection result, and modifying the RTL source code file corresponding to the signal to be observed based on the detection result. The method and the device solve the technical problem that in the prior art, the efficiency of the adaptability modification work of the design to be tested is low.
Description
Technical Field
The present application relates to the field of data logic design simulation technologies, and in particular, to a method for modifying an RTL source code file and an electronic device.
Background
Simulation verification is a necessary step of digital logic design test, and is one of effective means for guaranteeing the quality of digital logic design. The traditional simulation verification method uses pure software for simulation, for example, IES, modelsim, questasim, NC _ Sim, active-HDL and other software are used, and the simulation is performed on a computer or a server through a CPU according to a serial execution process. As the functional requirements of digital logic design become increasingly complex, the design complexity and the size of the used logic resources increase rapidly. Such as 5G communication, artificial intelligence and other application scenes, the logic resource occupation of the application scenes is usually more than 1 hundred million gates. For the simulation of large-scale complex digital logic design, the running time is long, the efficiency is low, particularly in the later stage of design, when regression testing is needed, the circuit scale is huge, the simulation scenes are numerous, and the time of hours, days or even weeks can be consumed when the traditional software is used for simulation, so that the verification period is greatly prolonged, the research and development cost is relatively increased sharply, and the market competitiveness of the product is finally reduced.
The simulation speed can be effectively improved by using software and hardware combined simulation, the test excitation generation with higher running speed is placed at a software end, the design to be tested with lower running speed is placed in an FPGA chip of a hardware end for running, and the software end and the hardware end interact data through a software and hardware interface. The Design Under Test (DUT) is placed in a real FPGA chip, and the running speed is greatly increased by utilizing an FPGA parallel processing architecture, so that the aim of improving the simulation speed is fulfilled.
The test excitation generated by the software end is sent to the design to be tested in the FPGA chip of the hardware end through the software and hardware port, and the running result of the design to be tested is uploaded to the software end through the software and hardware port, so that the waveform is displayed in the simulation software. The design to be tested is connected with the software and hardware interface through the top layer interface, namely, a signal to be observed in the design to be tested must be firstly connected to the top layer port of the design to be tested. Therefore, the design to be tested needs to be adaptively modified, the signal to be observed is connected to the top port of the design to be tested, and the signal to be observed is downloaded to the FPGA chip of the hardware end to operate after synthesis, layout and wiring. When the number of signals to be observed is large or the hierarchical structure of the design to be observed is deep, the manual modification work is very complicated and is very easy to make mistakes. When the design to be tested is complex, a lot of time is consumed for synthesizing, laying out and wiring, once the manual modification is wrong, the wiring needs to be synthesized and laid out again, and the efficiency of the adaptive modification work of the design to be tested is reduced.
Disclosure of Invention
The technical problem that this application was solved is: aiming at the problem that the efficiency of adaptability modification work of a design to be tested is low in the prior art, the method and the electronic equipment for modifying the RTL source code file are provided. In addition, the process of manually modifying the RTL source code is omitted, so that code errors caused by manual misoperation are eliminated, time waste caused by repeatedly modifying the RTL source code due to errors found after synthesis and layout wiring is avoided, and efficiency is further improved.
In a first aspect, an embodiment of the present application provides a method for modifying an RTL source code file, where the method includes: acquiring all RTL source code files of the design to be tested and the file names of the top RTL source codes of the design to be tested, associating the instantiation names of all modules in each RTL source code file with the file names, and storing the association results as tree-shaped data structures; acquiring all signal names corresponding to modules in each RTL source code file one by one and position information corresponding to each RTL source code file in the data structure, and adding prefixes in front of the signal names according to the position information to obtain complete signal names; selecting at least one signal to be observed from all the complete signals, detecting each signal to be observed in the signal list to be observed one by one to obtain a detection result, and modifying the RTL source code file corresponding to the signal to be observed based on the detection result to obtain a modified RTL source code file.
Optionally, associating instantiation names of modules in each RTL source code file with the file name, including: determining the instantiation relationship of each module in each RTL source code file, and determining the hierarchical structure of the design to be tested according to the instantiation relationship; and associating the instantiation names of the modules in the hierarchical structure with the file names.
Optionally, adding a prefix before the signal name according to the location information to obtain a complete signal name, including:
and generating a signal prefix according to the position information and the hierarchical structure, and adding the signal prefix to the signal name to obtain the complete signal name with an instantiated hierarchy.
Optionally, selecting at least one signal to be observed from all the complete signals includes:
organizing all complete signals according to the hierarchical structure to obtain a complete signal list;
selecting at least one signal to be tested from the complete signal list, and marking each selected signal to be tested on the complete signal list;
and extracting the at least one signal to be detected from the complete signal list according to the mark to obtain a signal list to be detected.
Optionally, detecting each signal to be observed in the signal list to be observed one by one to obtain a detection result, including:
determining an RTL source code file corresponding to each signal to be observed according to the signal name prefix corresponding to each signal to be observed and the data structure;
and detecting whether each signal to be observed is an output port signal of the corresponding RTL source code file, and obtaining a detection result.
Optionally, if the detection result is that the first signal to be observed is an output port signal of a first RTL source code file corresponding to the first signal to be observed, marking the first observed signal in the first RTL source code file, and determining a second RTL source code file based on the data structure; the first signal to be observed is any signal in the at least one signal to be observed, and the second RTL source code file is an RTL source code file located at a layer above the first RTL source code file in the data structure; extracting a port signal of a module corresponding to the first RTL source code file from the second RTL source code file, searching the first signal to be observed from the port signal, and adding a new signal in the second RTL source code file or marking the first observed signal in the second RTL source code file based on a search result.
Optionally, if the search result is that the first to-be-observed signal is not searched from the port signals, adding a first port signal at a position where the second RTL source code file instantiates the first RTL source code file; judging whether the first port signal is an output port signal of the second RTL source code file; and if so, marking the first observation signal in the second RTL source code file.
Optionally, if the first port signal is not an output port signal of the second RTL source code file, adding a second port signal in the second RTL source code file, and associating the second port signal with the first signal to be observed.
Optionally, if the detection result is that the first signal to be observed is not the output port signal of the first RTL source code file corresponding to the first signal to be observed, a third port signal is added to the first RTL source code file, and the third port signal is associated with the first signal to be observed.
In a second aspect, the present application provides an electronic device, comprising:
a memory for storing instructions for execution by at least one processor;
a processor for executing instructions stored in a memory to perform the method of the first aspect.
Drawings
Fig. 1 is a schematic flowchart of a method for modifying an RTL source code file according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a tree data structure according to an embodiment of the present application;
fig. 3 is a schematic flowchart of a process of modifying an RTL source code file according to an embodiment of the present application;
fig. 4 is a flowchart illustrating a connection of signals to be observed according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
In the solutions provided in the embodiments of the present application, the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.
In order to better understand the technical solutions of the present application, the following detailed descriptions are provided with accompanying drawings and specific embodiments, and it should be understood that the specific features in the embodiments and examples of the present application are detailed descriptions of the technical solutions of the present application, and are not limitations of the technical solutions of the present application, and in a case of no conflict, the technical features in the embodiments and examples of the present application may be combined with each other.
The method for modifying the RTL source code file provided in the embodiment of the present application is described in further detail below with reference to the drawings in the specification, and a specific implementation manner of the method may include the following steps (a method flow is shown in fig. 1):
step 101, acquiring all RTL source code files of the design to be tested and file names of top RTL source codes of the design to be tested, associating example names of modules in each RTL source code file with the file names, and storing association results into a tree-shaped data structure.
By way of example, the design under test is software or a program to be tested loaded in a chip, which includes at least one RTL source code file. And software or programs are typically designed in a hierarchical structure. The design to be tested includes RTL source code files of different levels, wherein a part of the design to be tested, in which software and hardware interfaces are connected, is called a top layer of the design to be tested. In order to automatically add the observation signal to be detected in the design to be detected, all RTL source code files of the design to be detected and the file names of the top RTL source codes of the design to be detected need to be acquired. Each RTL source code file comprises at least one module, and a certain instantiation relationship exists among the modules; wherein, the instantiation relationship is, for example, the connection relationship after each module is instantiated. Then, determining a hierarchical structure of the design to be tested according to the instantiation relationship of each module, associating instantiation names of the modules in the hierarchical structure with RTL file names, and finally storing the hierarchical structure and the corresponding file names into a tree-shaped data structure. The input of the process is all RTL source codes of the design to be tested and the file names of the RTL source codes at the top layer of the design to be tested, and the output of the process is a tree data structure.
As another example, associating instantiation names of modules in each RTL source code file with the file name includes: determining the instantiation relationship of each module in each RTL source code file, and determining the hierarchical structure of the design to be tested according to the instantiation relationship; and associating the instantiation names of the modules in the hierarchical structure with the file names.
Fig. 2 illustrates a schematic diagram of a tree data structure according to an embodiment of the present application.
By way of example, in FIG. 2, a top-level RTL source code file is taken as an example. The process accesses a top RTL source code file according to an input top file name to be designed, obtains a module name of the top RTL source code file, a module name of a top file instantiation sub-module and an instantiation name of the top file through a static analysis method, stores the module name of the top RTL source code file into a root node of a tree-shaped data structure, and stores the module name of the top RTL source code file instantiation sub-module and the instantiation name of the top RTL source code file into a first-level sub-node of the tree-shaped data structure. And accessing other RTL source code files except the top layer one by one, acquiring the module names of the RTL source code files through static analysis, if the module names are in the primary subnode of the tree-shaped data structure, acquiring the module names and instantiation names of instantiation subnodes in the RTL source code files, storing the module names and instantiation names of instantiation subnodes in the RTL source code files into a secondary subnode below the current primary subnode of the tree-shaped data structure, and if the module names are not in the primary subnode of the tree-shaped data structure, accessing the next RTL source code file. And after all the RTL source code files are accessed, if the tree-shaped data structure contains secondary sub-nodes, performing next round of RTL source code file traversal, analyzing the RTL source code files corresponding to the secondary sub-nodes, and filling the tertiary sub-nodes of the tree-shaped data structure. And then down-fill step by step until there are no lower level sub-nodes. And after the completion, outputting the tree data structure.
And 102, acquiring all signal names corresponding to modules in each RTL source code file one by one and position information corresponding to each RTL source code file in the data structure, and adding prefixes in front of the signal names according to the position information to obtain complete signal names.
As an example, adding a prefix before the signal name according to the location information to obtain a complete signal name includes: and generating a signal prefix according to the position information and the hierarchical structure, and adding the signal prefix to a signal name to obtain the complete signal name with an instantiated hierarchy. Specifically, all RTL source code files are visited one by one, the module name, the port signal name and the internal signal name of the current RTL source code file are obtained through a static analysis method, the module name of the current RTL source code file is used for obtaining output search in a to-be-tested design hierarchical structure, the search result is one or more nodes in a tree-shaped data structure, processing is carried out on each searched node, if the node is a root node, the module name of the root node is used as a prefix and added in front of the port signal name and the content signal name of the current RTL source code file, and then the prefix is stored in a complete signal list; if the node is a child node, acquiring the instantiation name of the child node, then acquiring the instantiation name of the parent node of the child node, acquiring the module name of the root node until the root node, then adding the acquired module name and instantiation name as prefixes in front of the port signal name and the content signal name of the current RTL source code file according to the sequence from the root node to the child node, and then storing the prefixes in a complete signal list. And after analyzing and processing all RTL source code files, outputting a complete signal list.
103, selecting at least one signal to be observed from all the complete signals, detecting each signal to be observed in the signal to be observed list one by one to obtain a detection result, and modifying the RTL source code file corresponding to the signal to be observed based on the detection result to obtain a modified RTL source code file.
As an example, selecting at least one signal to be observed from all the complete signals includes: organizing all complete signals according to the hierarchical structure to obtain a complete signal list; selecting at least one signal to be tested from the complete signal list, and marking each selected signal to be tested on the complete signal list; and extracting the at least one signal to be detected from the complete signal list according to the mark to obtain a signal list to be detected.
As another example, a complete signal list output in all signal acquisition processes of a design to be observed is read, a complete signal name list with a hierarchical structure is output according to each signal name in a hierarchical structure organization of the design to be observed through a visual human-computer interface, an operator selects a signal in the list as a signal to be observed through the human-computer interface and marks the signal, after the selection is completed, marking information is transmitted to the complete signal name list for marking, and finally, the marked signal is output as the signal list to be observed.
Further, as another example, detecting each signal to be observed in the signal list to be observed one by one to obtain a detection result includes: determining an RTL source code file corresponding to each signal to be observed according to the signal name prefix corresponding to each signal to be observed and the data structure; and detecting whether each signal to be observed is an output port signal of the corresponding RTL source code file, and obtaining a detection result.
For another example, if the detection result is that the first signal to be observed is an output port signal of a first RTL source code file corresponding to the first signal to be observed, marking the first observed signal in the first RTL source code file, and determining a second RTL source code file based on the data structure; the first signal to be observed is any one of the at least one signal to be observed, and the second RTL source code file is an RTL source code file located at a layer above the first RTL source code file in the data structure; extracting a port signal of a module corresponding to the first RTL source code file from the second RTL source code file, searching the first signal to be observed from the port signal, and adding a new signal in the second RTL source code file or marking the first observed signal in the second RTL source code file based on a search result.
As another example, if the search result is that the first to-be-observed signal is not searched from the port signals, adding a first port signal at a position where the second RTL source code file instantiates the first RTL source code file; judging whether the first port signal is an output port signal of the second RTL source code file; and if so, marking the first observation signal in the second RTL source code file.
As another example, if the first port signal is not an output port signal of the second RTL source code file, a second port signal is newly added to the second RTL source code file, and the second port signal is associated with the first signal to be observed.
For another example, if the detection result is that the first signal to be observed is not the output port signal of the corresponding first RTL source code file, a third port signal is added to the first RTL source code file, and the third port signal is associated with the first signal to be observed.
To facilitate understanding of the above-described process of modifying the RTL source code file, the following description is given by way of example. FIG. 3 is a flow chart illustrating a process for modifying an RTL source code file according to an embodiment of the present disclosure.
For example, as shown in fig. 3, the process reads the list of signals to be observed output by the signal to be observed selection process, and the tree data structure output by the design hierarchy to be observed acquisition process. And processing all signals to be observed one by one, firstly deducing an RTL source code file of the current signal to be observed according to the prefix of the name of the current signal to be observed and combining a tree data structure, and setting the RTL source code file as the current RTL source code file. Secondly, judging whether the current signal to be observed is an output port signal of the current RTL source code file, if not, adding an output signal in the current RTL source code file to be connected with the current signal to be observed, and marking the added signal; if yes, the current observed signal is directly marked. And finding the upper-layer RTL source code file of the current RTL source code file according to the hierarchical structure, instantiating the port signal of the module corresponding to the current RTL source code file in the upper-layer RTL source code file to search for the mark signal name, if the mark signal name is not found in the instantiating position, adding a port signal name at the instantiating position, and resetting the upper-layer RTL source code file as the current RTL source code file. Then judging whether the marking signal is an output port signal of the current RTL source code file, if not, adding an output signal in the current RTL source code file to be connected with the current signal to be observed, and marking the added signal; if so, directly marking the current observation signal, repeating the process to detect the RTL source code file in the design to be detected until the current RTL source code file is the top RTL source code file of the design to be detected. When all the signals in the signal list to be observed are processed, the process is finished.
Fig. 4 is a flowchart of a signal connection to be observed according to an embodiment of the present application.
As an example, the modification process for the RTL source code file of the design to be tested can be divided into the following steps, namely, obtaining the hierarchical structure of the design to be tested (obtaining the tree data structure), obtaining all signals of the design to be tested, selecting the signals to be observed, and connecting the signals to be observed. In fig. 4, the file names (such as Top file name in fig. 4) of the RTL source code file of the design to be tested and the Top RTL source code file of the design to be tested are input, the hierarchical structure of the design to be tested is determined by the instantiation relationship of each module in each RTL source code file, then the instantiation names of the modules in the hierarchical structure are associated with the RTL file name, and finally the hierarchical structure and the corresponding file names are stored in a tree-shaped data structure. Further, all signals of the design to be detected are obtained, then a complete signal list is obtained based on all signals, then signal names in the hierarchical structure organization are organized according to the design to be detected, the complete signal name list with the hierarchical structure is output through a visual human-computer interface, an operator selects the signals in the list as the signals to be observed through the human-computer interface and marks the signals, after the selection is completed, marking information is transmitted to the complete signal name list to mark the signals, and finally the marked signals are output as the signals to be observed. And then, detecting each signal to be observed in the observed signal list, and constructing the connection of each signal to be observed to obtain a modified RTL source code file.
According to the scheme provided by the embodiment of the application, only the to-be-tested design RTL source code file, the to-be-tested design top RTL source code file name and other processes need to be input into an automatic process without operation, and the process of manually modifying the RTL source code is omitted, so that the complexity of manual operation is greatly reduced, and the time of manual operation is greatly reduced. In addition, in the scheme provided by the embodiment of the application, the process of manually modifying the RTL source code is omitted, so that code errors caused by manual misoperation are eliminated. The time waste caused by repeatedly modifying the RTL source code after synthesis, layout and wiring are avoided, and the efficiency is further improved.
Referring to fig. 5, the present application provides an electronic device, comprising:
a memory 501 for storing instructions for execution by at least one processor;
a processor 502 for executing instructions stored in memory to perform the method described in fig. 1.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (10)
1. A method of modifying an RTL source code file, comprising:
acquiring all RTL source code files of the design to be tested and the file names of the top RTL source codes of the design to be tested, associating the instantiation names of all modules in each RTL source code file with the file names, and storing the association results as tree-shaped data structures;
acquiring all signal names corresponding to modules in each RTL source code file one by one and position information corresponding to each RTL source code file in the data structure, and adding prefixes in front of the signal names according to the position information to obtain complete signal names;
selecting at least one signal to be observed from all the complete signals, detecting each signal to be observed in the signal list to be observed one by one to obtain a detection result, and modifying the RTL source code file corresponding to the signal to be observed based on the detection result to obtain a modified RTL source code file.
2. The method of claim 1, wherein associating instantiation names of modules in each RTL source code file with the file name comprises:
determining the instantiation relationship of each module in each RTL source code file, and determining the hierarchical structure of the design to be tested according to the instantiation relationship;
and associating the instantiation names of the modules in the hierarchical structure with the file names.
3. The method of claim 2, wherein prefixing the signal name according to the location information to obtain a full signal name comprises:
and generating a signal prefix according to the position information and the hierarchical structure, and adding the signal prefix to a signal name to obtain the complete signal name with an instantiated hierarchy.
4. The method of claim 3, wherein selecting at least one signal to be observed from all complete signals comprises:
organizing all complete signals according to the hierarchical structure to obtain a complete signal list;
selecting at least one signal to be tested from the complete signal list, and marking each selected signal to be tested on the complete signal list;
and extracting the at least one signal to be detected from the complete signal list according to the mark to obtain a signal list to be detected.
5. The method of claim 4, wherein detecting each signal to be observed in the list of signals to be observed one by one to obtain a detection result comprises:
determining an RTL source code file corresponding to each signal to be observed according to the signal name prefix corresponding to each signal to be observed and the data structure;
and detecting whether each signal to be observed is an output port signal of the corresponding RTL source code file, and obtaining a detection result.
6. The method of claim 5, wherein,
if the detection result is that the first signal to be observed is an output port signal of a first RTL source code file corresponding to the first signal to be observed, marking the first observed signal in the first RTL source code file, and determining a second RTL source code file based on the data structure; the first signal to be observed is any one of the at least one signal to be observed, and the second RTL source code file is an RTL source code file located at a layer above the first RTL source code file in the data structure;
extracting a port signal of a module corresponding to the first RTL source code file from the second RTL source code file, searching the first signal to be observed from the port signal, and adding a new signal in the second RTL source code file or marking the first observed signal in the second RTL source code file based on a search result.
7. The method of claim 6, wherein,
if the search result is that the first signal to be observed cannot be searched from the port signals, adding a first port signal at a position where the second RTL source code file instantiates the first RTL source code file;
judging whether the first port signal is an output port signal of the second RTL source code file;
and if so, marking the first observation signal in the second RTL source code file.
8. The method of claim 7, wherein,
and if the first port signal is not the output port signal of the second RTL source code file, adding a second port signal in the second RTL source code file, and associating the second port signal with the first signal to be observed.
9. The method according to any one of claims 6 to 8, wherein,
and if the detection result is that the first signal to be observed is not the output port signal of the corresponding first RTL source code file, adding a third port signal in the first RTL source code file, and associating the third port signal with the first signal to be observed.
10. An electronic device, comprising:
a memory for storing instructions for execution by at least one processor;
a processor for executing instructions stored in a memory to perform the method of any one of claims 1 to 9.
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| CN117313622A (en) * | 2023-10-27 | 2023-12-29 | 深圳华芯盛软件科技有限公司 | Method, equipment and medium for adjusting module hierarchy in chip design |
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