CN115827636B

CN115827636B - Method for storing and reading simulation data of logic system design from waveform database

Info

Publication number: CN115827636B
Application number: CN202211632226.4A
Authority: CN
Inventors: 白继伟
Original assignee: Core Huazhang Technology Xiamen Co ltd
Current assignee: Core Huazhang Technology Xiamen Co ltd
Priority date: 2022-12-19
Filing date: 2022-12-19
Publication date: 2024-05-28
Anticipated expiration: 2042-12-19
Also published as: CN115827636A

Abstract

The application relates to the technical field of data storage, and particularly discloses a method for storing and reading simulation data of a logic system design from a waveform database, which comprises the following steps: determining a structure tree file corresponding to the logic system design according to the logic system design, wherein the structure tree file comprises a plurality of modules at a plurality of levels and a plurality of identifiers of signals corresponding to the plurality of modules, and the plurality of identifiers comprise a first identifier of a first signal; receiving first data, the first data comprising a change in a value of the first signal at a first time; storing a first identification of the first signal in association with the first data to a first data file; and associating the structure tree file with the first data file. The waveform data generated in the simulation process of the logic system design is stored in the waveform database in a mode of separating the data structure and the value change data of the signals, so that the storage efficiency is improved, and the data redundancy of the waveform database is reduced.

Description

Method for storing and reading simulation data of logic system design from waveform database

Technical Field

The present disclosure relates to the field of data storage, and more particularly to a method of storing and reading simulation data of a logic system design from a waveform database.

Background

Databases generally refer to a repository that organizes, stores and manages data according to a data structure, which may be a collection of large amounts of data stored in a computer for a long period of time, organized, sharable, and uniformly managed. With the development of cloud computing and the arrival of big data age, more and more data need to be stored and managed in a database, and higher requirements are put on the database. Storing waveform data is critical to the operation of the trace-back design, for example, during logic design verification. As the design scale increases, the waveform data to be stored becomes larger.

In the related art, in order to accelerate the storage speed of waveform data, one waveform database may be split into a plurality of waveform databases, so that data may be written to the plurality of databases at the same time. Each split database is an independent database and stores the waveform structure and signal value change data of the data. However, as the design scale increases, the waveform structure of the data occupies more memory space, so that a large amount of redundant data exists for each split database.

Disclosure of Invention

In view of the foregoing, it is desirable to provide a method of storing simulation data of a logic system design, a method of reading simulation data of a logic system design from a waveform database, an electronic device, and a non-transitory computer readable storage medium.

In a first aspect, the present application provides a method of storing simulation data of a logic system design. The method comprises the following steps:

Determining a structure tree file corresponding to the logic system design according to the logic system design, wherein the structure tree file comprises a plurality of modules at a plurality of levels and a plurality of identifiers of signals corresponding to the plurality of modules, and the plurality of identifiers comprise a first identifier of a first signal;

receiving first data, the first data comprising a change in a value of the first signal at a first time;

Storing a first identification of the first signal in association with the first data to a first data file; and

The structure tree file is associated with the first data file.

In a second aspect, the present application also provides a method of reading simulation data of a logic system design from a waveform database. The waveform database includes a structural tree file corresponding to the logical system design, the structural tree file including a plurality of modules at a plurality of levels and a plurality of identifications of signals corresponding to the plurality of modules, the plurality of identifications including a first identification of a first signal, a first data file and a second data file, the structural tree file associated with the first data file and the second data file, the method comprising:

receiving an instruction for reading the waveform of a target signal, and determining the identification of the target signal;

According to the identification of the target signal, obtaining structural data of the target signal in the structural tree file, wherein the structural data comprises module information of the target signal;

and loading the first data file or the second data file, and acquiring the value change data of the target signal according to the identification of the target signal.

In a third aspect, the present application also provides a non-transitory computer readable storage medium storing a set of instructions of a computer for, when executed, causing the computer to perform the method of the first or second aspect.

According to the embodiment of the application, the waveform data generated in the simulation process of the logic system design is stored into the waveform database in a mode of separating the data structure and the value change data of the signals through the debugging tool, the specific structure tree file stores a plurality of modules of a plurality of levels and a plurality of identifiers of the signals corresponding to the plurality of modules, the data file stores the value change data of the signals, and the structure tree file is associated with the plurality of data files, so that the value change data generated in the simulation process can be quickly stored into the data file according to the associated structure tree file, the data file can be flexibly added according to the scale of the value change data generated in the simulation process, the data structure and the value change data are separated and stored, the repeated storage of the data structure in the data file is avoided, the storage efficiency is improved, and the data redundancy of the waveform database is reduced. In addition, by establishing correspondence between signal names and signal identifications, data can be read and stored in the waveform database.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments or the conventional techniques of the present disclosure, the drawings required for the descriptions of the embodiments or the conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to the drawings without inventive effort to those of ordinary skill in the art.

FIG. 1 shows a schematic diagram of a host according to an embodiment of the application.

FIG. 2A shows a schematic diagram of an emulation tool, a debug tool, and a debug tool in accordance with an embodiment of the present application.

Fig. 2B shows a schematic diagram of a waveform database according to an embodiment of the application.

FIG. 3 shows a schematic diagram of a structural tree file according to an embodiment of the present application.

FIG. 4 illustrates a schematic diagram of a storage tool determining a structural tree file according to an embodiment of the present application.

FIG. 5 shows a schematic diagram of a data file according to an embodiment of the application.

FIG. 6 illustrates a schematic diagram of a method of storing simulation data of a logic system design in accordance with an embodiment of the present application.

FIG. 7 illustrates a schematic diagram of a method of reading simulation data of a logic system design from a waveform database, in accordance with an embodiment of the present application.

Detailed Description

The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.

It should be noted that the terms "first," "second," and the like in the description and claims of the present disclosure and in the foregoing figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the disclosure described herein may be capable of operation in sequences other than those illustrated or described herein. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present disclosure as detailed in the accompanying claims. The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, it is not excluded that additional identical or equivalent elements may be present in a process, method, article, or apparatus that comprises a described element. For example, if first, second, etc. words are used to indicate a name, but not any particular order.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, in this specification, the term "and/or" includes any and all combinations of the associated listed items.

Fig. 1 shows a schematic diagram of a host 100 according to an embodiment of the application. The host 100 may be an electronic device running an emulation system. As shown in fig. 1, the host 100 may include: processor 102, memory 104, network interface 106, peripheral interface 108, and bus 110. Wherein the processor 102, the memory 104, the network interface 106, and the peripheral interface 108 are communicatively coupled to each other within the host via a bus 110.

The processor 102 may be a central processing unit (Central Processing Unit, CPU), an image processor, a neural Network Processor (NPU), a Microcontroller (MCU), a programmable logic device, a Digital Signal Processor (DSP), an Application SPECIFIC INTEGRATED Circuit (ASIC), or one or more integrated circuits. The processor 102 may be used to perform functions related to the techniques described herein. In some embodiments, processor 102 may also include multiple processors integrated as a single logical component. As shown in fig. 1, the processor 102 may include a plurality of processors 102a, 102b, and 102c.

The memory 104 may be configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). In some embodiments, the simulation test system used to simulate the test design may be a computer program stored in memory 104. As shown in fig. 1, the data stored in the memory may include program instructions (e.g., program instructions for implementing the method of the present application according to the function starting software) as well as data to be processed (e.g., the memory may store temporary code generated during the compiling process). The processor 102 may also access program instructions and data stored in the memory and execute the program instructions to perform operations on the data to be processed. The memory 104 may include volatile storage or nonvolatile storage. In some embodiments, memory 104 may include Random Access Memory (RAM), read Only Memory (ROM), optical disks, magnetic disks, hard disks, solid State Disks (SSD), flash memory, memory sticks, and the like.

The network interface 106 may be configured to provide communication with other external devices to the host 100 via a network. The network may be any wired or wireless network capable of transmitting and receiving data. For example, the network may be a wired network, a local wireless network (e.g., bluetooth, wiFi, near Field Communication (NFC), etc.), a cellular network, the internet, or a combination of the foregoing. It will be appreciated that the type of network is not limited to the specific examples described above. In some embodiments, network interface 106 may include any combination of any number of Network Interface Controllers (NICs), radio frequency modules, receivers, modems, routers, gateways, adapters, cellular network chips, etc.

The peripheral interface 108 may be configured to connect the host 100 with one or more peripheral devices to enable information input and output. For example, the peripheral devices may include input devices such as keyboards, mice, touchpads, touch screens, microphones, various types of sensors, and output devices such as displays, speakers, vibrators, and indicators.

Bus 110 may be configured to transfer information between the various components of host 100 (e.g., processor 102, memory 104, network interface 106, and peripheral interface 108), such as an internal bus (e.g., processor-memory bus), an external bus (e.g., USB port, PCI-E bus), etc.

It should be noted that, although the above-described host architecture only shows the processor 102, the memory 104, the network interface 106, the peripheral interface 108, and the bus 110, in a specific implementation, the host architecture may also include other components necessary to achieve proper operation. Furthermore, it will be understood by those skilled in the art that the above-described host architecture may include only components necessary for implementing the embodiments of the present application, and not all components shown in the drawings.

FIG. 2A shows a schematic diagram of a simulation tool 202 and a debug tool 200 in accordance with an embodiment of the present application. Debug tool 200 may be a computer program running on host 100. The simulation tool 202 may be a software simulation tool or a hardware simulation tool.

In the field of chip design, a design may be simulated, typically with simulation tools. The simulation tool may be, for example, galaxSim simulation tool available from core chapter technologies, inc. The example simulation tool 202 illustrated in FIG. 2A may include a compiler 120 and a simulator 220. Compiler 120 may compile a design (e.g., verification design 214) into object code 204, and simulator 220 may simulate based on object code 204 and output simulation results 206. For example, the simulation tool 202 may output simulation results (e.g., simulation waveform diagrams) onto an output device (e.g., displayed on a display) via the peripheral interface 108 of fig. 1. Verification design 214 may include a logic system design 214a and a verification environment 214b. Verification environment 214b may also be referred to as a test bench (testbench). For example, the verification environment 214b may be a UVM environment.

Debug tool 200 may also read simulation results 206. The Debug tool 200 may be, for example, a Fusion Debug tool available from core chapter technologies, inc. For example, debug tool 200 may read simulation results 206 stored in a waveform file and generate corresponding simulated waveforms for debugging. Debug tool 200 may also read a description of verification system 214 (typically SystemVerilog and Verilog code) and display to the user. Debug tool 200 may also generate various graphical interfaces (e.g. debug windows) to facilitate user debugging operations. The user may issue a debug command 208 to the debug tool 200 (e.g., run the verification design 214 to a certain time), and the debug tool 200 then applies the debug command 208 to the simulation tool 202 to execute accordingly. Debug tool 200 may also read log files. The log file may include various information of the simulation process, including information of the simulation error, a line number of the error, a time when the simulation error occurs, and the like.

It is understood that in addition to interfacing with simulation tool 202, debug tool 200 may also interface with hardware simulator (emulator).

Before the logic system design is put into actual operation, the running debugging of the programmed logic system design is required by the debugging tool 200. Debug tool 200 may receive user instructions from a user and make corresponding debug actions. In some embodiments, the user may issue a user instruction in the graphical interface by clicking a mouse; in some embodiments, a user may enter a command line in a command line interface to issue user instructions. In the debugging process, a user often stores waveform files in simulation data and inquires waveform signals of variable signals within a certain time range, so that the user can find out abnormality of logic system design through waveform visualization, further diagnose, find out reasons and specific source positions of the abnormality, and correct the abnormality, thereby guaranteeing robustness of the logic system design.

Debug tool 200 may read simulation results 206 and store simulation results 206 in waveform database 212. The waveform database 212 storing waveform data may also be referred to as a waveform file.

As the design scale of logic systems increases, the waveform data that needs to be stored becomes larger. In order to accelerate the storage speed of waveform data, one waveform database may be split into a plurality of waveform databases, so that data may be written to the plurality of databases at the same time. Each split database is an independent database and stores structural tree and signal value change data of logic system design. Logic system designs typically include multiple tiers, each with a respective signal. The multiple levels and the signals of each level constitute a structural tree of the logic system design. It is common practice to provide a complete structural tree for each individual waveform database so that the signal value change data of this waveform database can correspond to a specific signal so that the debugging tool can restore the signal. However, as the design scale increases, the number of levels of the logic system design increases, and signals in each level increase, so that the structural tree occupies a larger storage space, a large amount of redundant data exists in each split database, the overall waveform file is enlarged, and the reading and writing efficiency is reduced.

In view of the foregoing, embodiments of the present application provide a method of storing logic system simulation data, a method of reading logic system simulation data from a waveform database, an electronic device, and a non-transitory computer readable storage medium. The method provided by the application can store the waveform data in the simulation result 206 in a plurality of waveform databases in the simulation test process, particularly store the structure data of the variable signals in the logic system design in the structure tree files in the plurality of waveform databases, store the value change data of the variable signals in the data files in the structure tree files in the plurality of waveform databases, and establish the association relationship between the structure tree files and the data files, thereby reducing the redundant data of the waveform structures in the plurality of waveform databases, enabling the waveform data to be quickly and efficiently stored in the waveform databases, and being capable of quickly reading the waveform data from the waveform databases.

Next, the present application will be explained further on how to store waveform data in the simulation result 206 in a plurality of waveform databases and how to let the waveform data read from the waveform databases.

Fig. 2B shows a schematic diagram of waveform database 212, according to an embodiment of the application. The waveform database 212 may include a structure tree file 210 and a data file 220.

Debug tool 200 may determine structure tree file 210 corresponding to the logical system design based on the logical system design (e.g., source code of logical system design 214 a). The structure tree file 210 includes a complete structure tree of the logical system design for recording the structure of the waveform data. Debug tool 200 may receive value change data for variable signals in simulation results 206 over a range of time and store in data file 220 and associate structure tree file 210 with data file 220. The structure tree file 210 may correspond to a plurality of data files 220, such as a first data file 220a, a second data file 220b, … … nth data file 220N. According to the embodiment of the application, the structure tree and the value change data of the waveform data are respectively stored by adopting the storage files, and one structure tree file is associated with a plurality of data files, so that not only can the data redundancy caused by the structure data of the storage variables in the data files be avoided, but also the storage segmentation of the data files can be facilitated, and the storage is quicker and more flexible.

FIG. 3 shows a schematic diagram of a structural tree file according to an embodiment of the present application. Current logic system designs include multiple tiers, each of which may include one or more modules.

The structure tree file 210 may store a plurality of modules of a plurality of levels of the logic system design, a plurality of signals corresponding to the plurality of modules, through a tree structure. The structure tree file 210 may include a root directory (root scope) and a hierarchical directory (scope) corresponding to a plurality of hierarchies. A root directory (root scope) and a hierarchical directory (scope) of a plurality of levels are in one-to-one correspondence with a plurality of modules of a plurality of levels of a logical system design. The primary directories scope_1 and scope_2 are included under the root directory (root Scope) of the structure tree file 210 shown in fig. 3, for example. The primary catalog scope_1 includes secondary catalogs scope_1_1, scope_1_2 and variable var4. The variables var1 and var2 are included under the secondary directory scope_1_1. The variable var3 is included under the secondary directory scope_1_2. The secondary directory scope_2_1 is included under the primary directory scope_2. The variable var5 is included under the secondary directory scope_2_1. The root directory (root Scope), the primary directory scope_1 and scope_2, and the secondary directory scope_1_1, scope_1_2, scope_2_1 respectively correspond to a plurality of modules of a plurality of levels of the logic system design, and the variables var1 to var5 are signals in the logic system design.

In some embodiments, debug tool 200 may also store a signal Identification (ID) corresponding to the signal in structure tree file 210 when storing the value (e.g., change in value) of the signal for the logic system design to the waveform database. The structure tree file 210 stores the variables var 1-var 5 in the form of a structure for recording the signal identification and the global names of the signals in the structure tree. For example, the global name of the variable var1 in the structure tree is "root_scope_1. Scope_1_1.Var1". The correspondence between the signal and the signal identifier is also stored in the structure tree file 210, for example, in a mapping table. The signal Identification (ID) may be a number corresponding to a plurality of signals. For example, the mapping table may record a correspondence between a signal name and a signal identifier, and specifically, reference may be made to table one, where variables var1 to var5 in the mapping table are variable signal names.

ID	Var
		1	var1
2	Var2
		3	Var3
4	Var4
		5	Var5

List one

It should be noted that, when the value change data of the variable signal is stored in the data file, the signal identification and the change of the value of the signal may be directly stored. Since the signal identification is a variable of a digital type (e.g., int) and the name of the variable signal is a variable of a character string type, the use of the signal identification can help to further increase the storage speed of the value change data and facilitate subsequent quick interrogation of the value change data of the signal from the signal identification.

FIG. 4 shows a schematic diagram of a storage tool determining structure tree file 210 according to an embodiment of the application. As shown in fig. 4, the structure tree file 210 may include a plurality of signal block files (e.g., a first signal block file 210a and a second signal block file 210 b) in addition to the structure of the recording logic system design. When the simulation of the logic system design is performed, waveform data is continuously generated along with the progress of simulation time. The generated waveform data is first stored in a buffer, and after being buffered to a certain number of waveform data, the generated waveform data is stored in the form of one data block in the waveform database 212. That is, each of the first data file 220a, the second data file 220b, …, the nth data file 220N may include a plurality of data blocks. The signal block file may indicate the location of the data block to which the signal identification belongs, so that reading and writing of the value of the signal may be performed in the corresponding data file 220.

In some embodiments, during the process of reading simulation data of a logic system design from a waveform database, debug tool 200 may receive user instructions from a user to view the waveform of a target signal. The instruction for reading the waveform of the target signal generally includes the signal name of the target signal. Further, the debug tool 200 may read the correspondence between the plurality of signal identifications and the signal names (e.g. mapping table one) in the structure tree file 210, and may determine the Identification (ID) of the target signal according to the signal name of the target signal. The debug tool 200 can quickly locate the structural data of the target signal in the structural tree file 210 according to the determined Identification (ID) of the target signal, i.e. the module to which the target signal specifically belongs in the logical system design can be determined. The debugging tool 200 can also quickly locate the value change data of the target signal in the data file according to the determined Identification (ID) of the target signal, and generate the waveform data of the target signal by combining the structural data and the value change data of the target signal, and show the waveform of the target signal to the user through the debugging tool 200.

The simulation data may include signal names and value change data. The process of writing simulation data to the waveform database is similar to the reading simulation data described above. That is, the debugging tool 200 may determine the signal identifier corresponding to the signal name based on the correspondence relationship of the plurality of signal identifiers and the signal name according to the signal name of the generated simulation data. Debug tool 200 may store value change data to data file 220 in accordance with the determined signal identification.

Fig. 5 shows a schematic diagram of a data file 500 according to an embodiment of the application. The data file 500 shown in fig. 5 may include a data file a, a data file B, and a data file C. Data file a, data file B, and data file C are associated with structure tree file 210. The division of the data file may be performed according to a time range, i.e. the data file a is used for storing the value change data of the time range [0, 100], the data file B is used for storing the value change data of the time range [101, 200], and the data file C is used for storing the value change data of the time range [201, 300 ]. The units of the time range may be set by the user himself.

In determining the value change data of the target signal according to the Identification (ID) of the target signal, the debug tool 200 may load the target data file satisfying the instruction in a plurality of data files. The instruction to read the waveform of the target signal also typically includes a time range of the target signal in which the waveform is to be displayed. The debug tool 200 may determine a target time range of the target signal according to an instruction of the waveform of the target signal, for example, waveform data indicating that the acquisition target signal is in the time range of [80, 150] in an instruction of reading the waveform of the target signal.

The debug tool 200 may determine the target data file to be loaded according to the time ranges of the plurality of data files and the target time range, so that the target data file contains the value change data of the target time range, thereby enabling the debug tool 200 to quickly load the target data file and reducing unnecessary data loading.

In some embodiments, debug tool 200 further treats the value change data of the overlapping ranges in the data files as the target data file by determining whether there is an overlapping range between the time ranges of the plurality of data files and the target time range. Referring to fig. 5, the debug tool 200 compares the time range [0, 100] of the data file a with the target time range [80, 150] to determine whether there is a coincidence range in the time ranges. At this time, the debug tool 200 determines that [80, 100] in the data file a is the target data file. The tool 200 continues to compare the time range [101, 200] of the data file B with the target time range [80, 150] to determine if there is a coincidence range in the time ranges. At this time, the debug tool 200 determines yes that [101, 150] in the data file B is the target data file. The debug tool 200 continues to compare the time range [201, 300] of the data file C with the target time range [80, 150] to determine whether there is a coincidence range in the time ranges. At this time, the debug tool 200 determines no, and the debug tool 200 may end the determination with [80, 100] in the data file a and [101, 150] in the data file B as target data files. After determining all the target data files, the debug tool 200 loads the [80, 100] in the data file a and the [101, 150] time range value change data in the data file B, and determines the value change data of the target signal in the target time range according to the target signal. According to the embodiment, the target data files in the target time range can be accurately loaded in the plurality of data files through the time range, so that the data reading speed can be further improved, and unnecessary data loading is reduced.

Some embodiments of the application also provide a method of storing logic system simulation data.

FIG. 6 illustrates a schematic diagram of a method 600 of storing logical system simulation data, in accordance with an embodiment of the present application. Method 600 may be performed by host 100 of fig. 1, and more specifically, by debug tool 200 of fig. 2A running on host 100. The method 600 may include the following steps.

At step 610, the host 100 may determine a structural tree file corresponding to the logical system design based on the logical system design (e.g., source code of the logical system design). The structure tree file (e.g., 210 in fig. 2B and fig. 3) includes a plurality of modules at a plurality of levels and a plurality of identifications of signals corresponding to the plurality of modules, the signal identifications being used to determine corresponding signals. The plurality of identifications may include a first identification of the first signal and a second identification of the second signal. It will be appreciated that the host 100 may analyze and compile the logic system design, and further analyze the modules therein to obtain a plurality of modules at a plurality of levels and a plurality of signals under the plurality of modules of the logic system design.

At step 620, the host 100 may receive first data, wherein the first data includes a change in a value of the first signal at a first time. The first data may be value change data generated by a simulation tool simulating the first signal of the process.

At step 630, the host 100 may save the first identification of the first signal and the first data in association to a first data file.

At step 640, the host 100 may associate the structure tree file with the first data file. That is, the first data file corresponding thereto can be determined by the structure tree file, the structure data and the first identification of the first signal are stored in the structure tree file, and the value change data and the first identification of the first signal are stored in the first data file.

In some embodiments, the method 600 further comprises:

At step 650, the host 100 may receive second data including a change in a value of the second signal at a second time.

At step 660, the host 100 may save the second identification of the second signal and the second data in association to a second data file.

At step 670, the host 100 may associate the structure tree file with the first data file and the second data file. The structural tree file and the first data file and the second data file are stored in association as a waveform database (e.g., waveform database 212 of fig. 2A) that includes the structural tree file and a plurality of data files associated with the structural tree file, the plurality of data files including the first data file and the second data file, the structural tree file further including a first signal block file. The first data file and the second data file may include a plurality of data blocks, the plurality of signal identifications may include a target signal identification, and the first signal block file may indicate a location of the data block to which the target signal identification belongs.

It should be noted that the first signal and the second signal are variable signals in the logic system design, and the first signal and the second signal each include a plurality of variable signals, and the plurality of variable signals included in the first signal and the plurality of variable signals included in the second signal may be completely different or partially/completely the same. The first time and the second time may be completely different or partially/completely the same time range, and typically the first time and the second time are completely different.

In some embodiments, the plurality of identifiers are numbers corresponding to the plurality of signals, and the structure tree file includes correspondence between the plurality of numbers and signal names of the plurality of signals (e.g., the aforementioned mapping table one).

In some embodiments, step 610 further comprises: in connection with fig. 4, the host 100 may determine a plurality of modules at a plurality of levels in the logical system design, and store the plurality of modules to the first cache file. The host 100 may further determine signals corresponding to the plurality of modules, and store the signals corresponding to the plurality of modules to the second cache file. The host 100 may determine a structural tree file corresponding to the logical system design from the first cache file and the second cache file.

A method of reading logic system simulation data from a waveform database is also provided in some embodiments of the application.

FIG. 7 illustrates a schematic diagram of a method of reading logic system simulation data from a waveform database in accordance with an embodiment of the present application. The waveform database includes a structural tree file corresponding to the logical system design, a first data file, and a second data file, the structural tree file including a plurality of modules at a plurality of levels and a plurality of identifications of signals corresponding to the plurality of modules, the plurality of identifications including a first identification of the first signal, the structural tree file being associated with the first data file and the second data file. Method 700 may be performed by host 100 of fig. 1, and more specifically, by debug tool 410 of fig. 2A running on host 100. The method 700 may include the following steps.

At step 710, host 100 may receive an instruction to read a waveform of a target signal (e.g., debug command 208 in FIG. 2A) and determine an identification of the target signal. Specifically, the host 100 may receive an instruction of a user to issue a waveform of a read target signal by clicking a mouse in a graphical interface, and may also receive an instruction of a user to input a command line in a command line interface to issue a waveform of a read target signal. In some embodiments, the instruction for reading the waveform of the target signal generally includes a signal name of the target signal, and the host 100 may determine the signal name of the target signal according to the instruction for reading the waveform of the target signal, and further read the correspondence between the plurality of numbers and the signal names of the plurality of signals from the structure tree file, to determine the number of the target signal.

In step 720, the host 100 may obtain, in the structure tree file, structure data of the target signal according to the identifier of the target signal, where the structure data includes module information to which the target signal belongs.

In step 730, the host 100 may load the first data file or the second data file, and obtain the value change data of the target signal according to the identification of the target signal.

In some embodiments, step 730 further includes steps 732-736 as follows.

In step 732, the host 100 may determine a target time range of the target signal in accordance with an instruction to read the waveform of the target signal. The instructions to read the waveform of the target signal typically also include a target time range for the target signal.

In step 734, the host 100 may determine a target data file to be loaded according to the first time of the first data file, the second time of the second data file, and the target time range, where the target data file is a part or all of the first data file and/or a part or all of the second data file. The target data file at least comprises value change data of a target signal in a target time range.

At step 736, the host 100 may load the target data file and obtain the value change data of the target signal in the target time range according to the identification of the target signal in the target data file.

In some embodiments, step 734 further comprises: the host 100 may determine whether a range of overlap exists between the first time and the target time range, and in response to the range of overlap exists between the first time and the target time range, the host 100 may determine that the value change data in the first data file in which the range of overlap exists between the first time and the target time range is the target data file. The host 100 may determine whether a second time and a target time range overlap, and in response to the second time and the target time range overlap, the host 100 may determine that value change data in the second data file for which the second time and the target time range overlap is the target data file.

The embodiment of the application also provides electronic equipment. The electronic device may be the host 100 of fig. 1. The electronic device may include a memory to store a set of instructions; and at least one processor configured to execute the set of instructions to cause the electronic device to perform the method 600 or the method 700.

Embodiments of the present application also provide a non-transitory computer readable storage medium. The non-transitory computer readable storage medium stores a set of instructions for a computer that, when executed, cause the computer to perform method 600 or method 700.

The foregoing describes some embodiments of the present application. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

Those of ordinary skill in the art will appreciate that: the discussion of any of the embodiments above is merely exemplary and is not intended to suggest that the scope of the application (including the claims) is limited to these examples; the technical features of the above embodiments or in the different embodiments may also be combined within the idea of the application, the steps may be implemented in any order and there are many other variations of the different aspects of the application as described above, which are not provided in detail for the sake of brevity.

While the application has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of those embodiments will be apparent to those skilled in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.

The present application is intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Therefore, any omission, modification, equivalent replacement, improvement, etc. of the present application should be included in the scope of the present application.

Claims

1. A method of storing simulation data of a logic system design, the method comprising:

Determining a structure tree file corresponding to the logic system design according to the logic system design, wherein the structure tree file comprises a plurality of modules at a plurality of levels and a plurality of identifiers of a plurality of signals corresponding to the plurality of modules, and the plurality of identifiers comprise a first identifier of a first signal; the structure tree file is used for associating a plurality of data files, and the plurality of data files comprise a first data file and a second data file;

storing a first identification of the first signal in association with the first data to the first data file; and

Associating the structure tree file with the first data file;

receiving second data, the second data comprising a change in a value of a second signal at a second time;

Storing a second identification of the second signal in association with the second data to the second data file;

Associating the structure tree file with the first data file and the second data file, wherein the structure tree file, the first data file and the second data file are respectively stored by adopting a storage file, and the structure tree file comprises a structure tree designed by the logic system and is used for recording the structure of waveform data; the plurality of data files store data of changes in values of the plurality of signals over a range of times.

2. The method of claim 1, wherein the plurality of identifications are numbers corresponding to the plurality of signals, and wherein the structure tree file comprises a correspondence of the plurality of numbers to signal names of the plurality of signals.

3. The method of claim 1, wherein the structural tree file and the first data file and the second data file are stored in association as a waveform database, the waveform database comprising the structural tree file and a plurality of data files associated with the structural tree file, the structural tree file further comprising a first signal block file.

4. A method of reading simulation data of a logical system design from a waveform database, the waveform database comprising a structural tree file corresponding to the logical system design, a first data file, and a second data file, the structural tree file comprising a plurality of modules at a plurality of levels and a plurality of identifications of a plurality of signals corresponding to the plurality of modules, the plurality of identifications comprising a first identification of a first signal, the structural tree file associated with the first data file and the second data file, the method comprising:

Loading the first data file or the second data file, and acquiring value change data of the target signal according to the identification of the target signal, wherein the structure tree file, the first data file and the second data file are respectively stored by adopting a storage file, and the structure tree file comprises a structure tree designed by the logic system and is used for recording the structure of waveform data; the plurality of data files store data of changes in values of the plurality of signals over a range of times.

5. The method of claim 4, wherein the plurality of identifiers are numbers corresponding to the plurality of signals, and wherein the structure tree file comprises correspondence of the plurality of numbers to signal names of the plurality of signals; the receiving an instruction to read a waveform of a target signal and determining an identity of the target signal further comprises:

And reading the corresponding relation between the plurality of numbers and the signal names of the plurality of signals from the structure tree file, and determining the number of the target signal.

6. The method of claim 4, wherein the loading the first data file or the second data file, the obtaining the value change data of the target signal based on the identification of the target signal further comprises:

Determining a target time range of the target signal according to the instruction for reading the waveform of the target signal;

Determining a target data file to be loaded according to the first time of the first data file, the second time of the second data file and the target time range, wherein the target data file is a part or all of the first data file and/or a part or all of the second data file;

and loading the target data file, and acquiring value change data of the target signal in the target time range according to the identification of the target signal in the target data file.

7. The method of claim 6, wherein the determining the target data file to be loaded based on the first time of the first data file, the second time of the second data file, and the target time range further comprises:

judging whether a coincidence range exists between the first time and the target time range;

determining that value change data in the first data file, in which a range of coincidence exists between the first time and the target time range, is the target data file in response to the range of coincidence exists between the first time and the target time range;

judging whether a coincidence range exists between the second time and the target time range;

And in response to the second time and the target time range being in a coincidence range, determining that value change data of the second time and the target time range in the second data file are in the coincidence range as the target data file.

8. An electronic device, comprising

A memory for storing a set of instructions; and

At least one processor configured to execute the set of instructions to cause the electronic device to perform the method of any one of claims 1 to 7.

9. A non-transitory computer readable storage medium storing a set of instructions for a computer, which when executed, cause the computer to perform the method of any of claims 1 to 7.