CN115810374A - Memory circuit and memory computing circuit with BCAM addressing and logic operation functions - Google Patents

Abstract

The invention relates to the technical field of static random access memories, in particular to a memory circuit and a memory computing circuit with BCAM addressing and logical operation functions. The memory circuit comprises NMOS transistors N1-N5 and PMOS transistors P0-P1; N1-N4 and P0-P1 form a 6T-SRAM unit, N5 is connected between two MOS tubes corresponding to any storage node of the 6T-SRAM unit, and the grid electrode of N5 is controlled by a control signal line EN. Compared with the traditional 6T-SRAM, the storage circuit designed by the invention is additionally provided with a transistor for isolating the read port from the storage node, thereby improving the problem of read damage of the 6T structure. Meanwhile, compared with the traditional 8T-SRAM with separate reading and writing, the SRAM has one less transistor and has larger area advantage.

Description

Memory circuit and memory computing circuit with BCAM addressing and logic operation functions

Technical Field

The invention relates to the technical field of static random access memories, in particular to a storage circuit, a memory computing circuit with BCAM addressing and logic operation functions based on the storage circuit and a storage chip based on the storage circuit.

Background

To overcome the computational limitations imposed by the traditional von Neumann architecture, the concept of Computing In Memory (CIM) was proposed. The memory calculation does not need to frequently transmit data from the memory to the processor, and the operation part is directly integrated into the memory array to execute the calculation, so that the transmission of intermediate data is reduced, and the operation amount of the processor is reduced; another significant advantage of memory computing is the ability to perform multiple row reads, where the amount of bit line discharge and stored data is linear with multiple row read techniques. The bit line voltage is used for completing some simple logic operations, so that the access times of the memory are reduced, the energy loss is reduced to a certain extent, and the data throughput is increased. SRAM, which is a memory widely used in the cache memory field, occupies an increasing proportion of chip area and power consumption, and research on SRAM-based memory calculation is becoming more and more important.

A conventional 6T-SRAM has cross-coupled inverters and two access transistors for read and write operations. During a read operation, bit lines BL and BLB are precharged to VDD, and word line WL is set to VDD for reading. The read path of the 6T-SRAM is through the storage node to Ground (GND), which typically results in read disturb. The key technology of memory computing is the multi-row reading technology, namely, in the reading operation, word lines of multiple rows are opened at the same time instead of one row; the conventional 6T-SRAM can only read one row of data in one data reading process.

The 8T-SRAM structure with read coupling is provided for solving the read interference problem, the structure has the structural advantages of read-write separation, 9T-SRAM with read-write separation and even 10T-SRAM units are used for realizing internal calculation, and compared with the traditional 6T-SRAM, the structures can improve the read interference problem, but the area is increased correspondingly.

Disclosure of Invention

In view of the above, it is necessary to provide a memory circuit, a memory computing circuit based on the memory circuit and having BCAM addressing and logic operation functions, and a memory chip based on the memory circuit, aiming at the problem of improving read disturb by sacrificing area of the existing SRAM cell.

In order to realize the purpose, the invention adopts the following technical scheme:

a memory circuit includes NMOS transistors N1-N5 and PMOS transistors P0-P1. N1-N4 and P0-P1 form a 6T-SRAM unit, N5 is connected between two MOS tubes corresponding to any one storage node of the 6T-SRAM unit, and the grid of N5 is controlled by a control signal line EN. The specific connection mode of the storage circuit is as follows:

the gate of N1 is electrically connected to the drain of N2, the drain of N4, and the gate of P1. The drain of N1 is electrically connected to the drain of N3 and the source of N5. The source of N1 and the source of N2 are connected with GND. The gate of P2 is electrically connected to the drain of P1, the gate of N2, and the drain of N5. The drain of P2 is electrically connected to the gate of N1, the drain of N2, the drain of N4, and the gate of P1. The source of P1 and the source of P2 are connected to VDD. The grid of N3 is connected with the right word line WLR, the grid of N4 is connected with the left word line WLL, and the grid of N5 is electrically connected with an external control signal line EN. The source of N3 is connected to bit line BLB, and the source of N4 is connected to bit line BL.

Wherein P2 and N2 form an inverter, and N3 and N4 form a transmission tube of the storage circuit. Storage node Q is connected to bit line BL via N4, and storage node QB is connected to bit line BLB via N5, N3.

Further, the memory circuit implements the SRAM mode including a hold operation, a write operation, and a read operation. When the storage circuit performs the holding operation, the control signal line EN is held at a high level, the left word line WLL and the right word line WLR are held at a low level, and the latch structure formed by P1, P2, N1, N2, and N5 latches the storage data of the storage nodes Q and QB. When the storage circuit executes writing operation, the control signal line EN is kept at high level, the left word line WLL and the right word line WLR are pulled to high level, and simultaneously, data needing to be written are loaded on the writing bit line. When the storage circuit executes reading operation, the bit line BLB is precharged to a high level, the control signal line EN is at a low level, the left word line WLL is pulled down, the right word line WLR keeps at a high level, and the result is read through the sense amplifier SA.

The invention also relates to a memory computing circuit with BCAM addressing and logical operation functions, which is formed by a plurality of identical memory cells in an N multiplied by M array form. Wherein, N is the row number of the memory cell, and M is the column number of the memory cell. Each row of memory cells shares a left word line WLL and a right word line WLR. Each column of memory cells shares a bit line BL, BLB.

The storage unit adopts the circuit structure of the storage circuit and realizes the complete function of the circuit structure.

Further, all bit lines BL, BLB are connected to the sense amplifiers in a one-to-one correspondence. Bit lines BL or BLB in each column of memory cells are respectively used as one path of input of a sense amplifier, and the other path of the sense amplifier is input with a reference voltage. When the level of the BL or BLB is higher than the reference voltage, the sense amplifier outputs a high level, otherwise, the sense amplifier outputs a low level.

Further, the bit lines BL, BLB of each column of memory cells are connected to an and gate through single-ended sense amplifiers. The output ends of the two single-ended sensitive amplifiers are respectively used as two paths of inputs of an AND gate. And when the outputs of the two sensitive amplifiers are both high level, the AND gate outputs high level, otherwise, the AND gate outputs low level.

Further, when the memory computing circuit performs a memory boolean logic operation, the output terminal of the sense amplifier connected to the bit line BLB is used as the result output terminal for performing the operation. When the memory computing circuit executes BCAM operation, the output end of the AND gate is used as the result output end for executing the operation. When the memory calculation circuit performs multiplication, the discharge amount of the bit line BLB is the result of the multiplication. Further, the memory computing circuit implements the memory Boolean logic operation as follows: the left word line WLL and the control signal line EN of the memory cells in the same row are kept at low level, the right word line WLR of the memory cells which need to participate in the memory Boolean logic operation is set at high level, and the rest word lines are set at low level. The voltage on the bit line BLB is compared with a reference voltage by a sense amplifier and then a corresponding memory Boolean logic operation result is output.

Further, the memory computing circuit implements the BCAM operation as follows: keeping the control signal line EN of the storage units in the same column at a low level; inputting a voltage signal corresponding to the search data and an opposite signal thereof to a memory cell pre-storing data to be searched through a left word line WLL and a right word line WLR respectively; the voltage signals of the bit lines BL and BLB representing the operation result are output through two single-ended sense amplifiers and an AND gate; the output end of the AND gate outputs high level to represent that the search data is matched with the data to be searched; and the output end of the AND gate outputs low level, which indicates that the search data is not matched with the data to be searched.

Further, the memory computing circuit implements the multiplication operation as follows:

and keeping the control signal line EN and the left word line WLL of the same row of storage units at low level, inputting a voltage signal corresponding to a multiplicand into the storage unit in which the multiplier is prestored through the right word line WLR, and obtaining a required multiplication result according to the discharge amount of the bit line BLB.

The invention also relates to a memory chip which is formed by packaging the memory circuit. The pin of the memory chip includes:

and the grounding pin is connected with the source electrodes of the PMOS tubes P1 and P2.

And the power supply pin is connected with the source electrodes of the NMOS tubes N1 and N2.

And the first pin is connected with the source electrode of the NMOS transistor N4.

And the second pin is connected with the source electrode of the NMOS transistor N3.

And the third pin is connected with the grid electrode of the NMOS transistor N4.

And the fourth pin is connected with the grid electrode of the NMOS transistor N3.

The technical scheme provided by the invention has the following beneficial effects:

1. compared with the traditional 6T-SRAM, the storage circuit designed by the invention is additionally provided with a transistor for isolating the read port from the storage node, thereby improving the read damage problem of the 6T structure. Meanwhile, compared with the traditional 8T-SRAM with separate reading and writing, the SRAM has one less transistor and has larger area advantage.

2. The array distributed memory computing circuit designed by the invention can carry out the SRAM mode of normal holding, reading and writing, and can carry out simple Boolean logic operation, BCAM addressing operation and multiplication operation, thereby meeting various operation requirements.

Drawings

Fig. 1 is a circuit configuration diagram of a memory circuit of embodiment 1 of the present invention;

FIG. 2 is a circuit diagram illustrating an AND/NAND operation performed on two rows of memory cells according to embodiment 2 of the present invention;

FIG. 3 is a graph of simulation results based on the AND and NAND operation of FIG. 2;

FIG. 4 is a circuit diagram of a two-row memory cell NOR and OR NOT operation in embodiment 2 of the present invention;

FIG. 5 is a graph of simulation results based on the OR and OR NOT operations of FIG. 4;

fig. 6 is a schematic circuit diagram of a BCAM addressing circuit using 4 × 4 memory cells as an example according to embodiment 2 of the present invention;

fig. 7 is a graph of simulation results based on the BCAM addressing of fig. 6;

FIG. 8 is a circuit configuration diagram for executing a 4bit by 1bit binary multiplication operation according to embodiment 2 of the present invention;

FIG. 9 is a graph of simulation results based on FIG. 8 performing a 4bit by 1bit binary multiplication operation;

fig. 10 is a graph showing the change in linearity of the result of the 4bit × 1bit binary multiplication operation based on fig. 8.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.

Example 1

Referring to fig. 1, fig. 1 shows a memory circuit including NMOS transistors N1-N5 and PMOS transistors P0-P1 according to an embodiment. N1-N4 and P0-P1 form a 6T-SRAM unit, N5 is connected between two MOS tubes corresponding to any storage node of the 6T-SRAM unit, and the grid electrode of N5 is controlled by a control signal line EN. The specific connection mode of the storage circuit is as follows:

the drain of N2 is electrically connected to the gate of N1, and the source of N2 is electrically connected to the source of N1. The gate of N3 is electrically connected to right word line WLR, the drain of N3 is electrically connected to the drain of N1, and the source of N3 is electrically connected to bit line BLB. The gate of N4 is electrically connected to the right word line WLL, the drain of N4 is electrically connected to the drain of N2 and the gate of N1, and the source of N4 is electrically connected to the bit line BL. The grid electrode of N5 is electrically connected with an external control signal EN, the drain electrode of N5 is electrically connected with the grid electrode of N2, and the source electrode of N5 is electrically connected with the drain electrode of N1 and the drain electrode of N3. The gate of P1 is electrically connected to the gate of N1, the drain of N2, and the drain of N4, and the drain of P1 is electrically connected to the gate of N2, and the drain of N5. The grid of P2 is electrically connected with the grid of N2 and the drain of N5, the drain of P2 is electrically connected with the grid of N1, the drain of N2, the drain of N4 and the grid of P1 is electrically connected with the source of P1 and the source of P2.

An NMOS transistor N5 is additionally arranged between the drain electrode of the P1 of the right half part of the circuit and the drain electrode of the N1, the grid electrode of the N5 is controlled by an external control signal line EN, the P2 and the N2 of the left half part form an inverter, when the N5 transistor is conducted, data stored by storage nodes Q and QB are latched on the left side and the right side, the source electrodes of the transistors P1 and P2 are electrically connected to VDD, the power supply path of the storage nodes Q and QB is started, the source electrodes of the transistors N1 and N2 are electrically connected to GND, and the ground path of the storage nodes Q and QB is started. When the N5 tube is turned off, the transistor P1 and the transistor N1 are disconnected, the grid electrode of the N1 is controlled by Q, the drain electrode of the N1 is not directly influenced by QB any more, the transistor N3 is controlled by the word line WLR, the transistor N1, the transistor N3 and the right bit line BLB are connected, when the transistors N1 and N3 are both conducted, the right bit line BLB can form a grounding path, the discharge quantity of the right bit line BLB can be controlled by controlling the conduction degree of the transistors N1 and N3, and different calculation modes can be realized by utilizing the principle.

The storage node Q is connected with the bit line BL through the transistor N4, the storage node QB is connected with the bit line BLB through the transistors N5 and N3, and the transistors N4 and N3 are transmission tubes positioned on the left side and the right side of the structure and used as two paths and controlled by the left word line WLL and the right word line WLR respectively.

Compared with the traditional 6T-SRAM, the 7T-SRAM circuit formed by 7 transistors improves the reading damage problem of a 6T structure because the reading port is isolated from the storage node. Compared with the traditional 8T-SRAM with separate read and write, the SRAM has the advantages of being one transistor less and having larger area.

The specific operation of the memory circuit of the present embodiment in the SRAM mode will be described below. In the SRAM mode, including a hold operation, a write operation, and a read operation, the specific operation steps are as follows:

(1) Hold mode

In the data holding period, the external control signal line EN is held at a high level, the left word line WLL and the right word line WLR are held at a low level, the NMOS transistors N3 and N4 are turned off, and N5 is turned on. The latch structure formed by the PMOS transistors P1 and P2 and the NMOS transistors N1, N2, and N5 latches the values of the storage nodes Q and QB, and the change of the bit lines BL and BLB does not affect the storage nodes Q and QB.

(2) Write operation

During a write operation, the external control signal line EN, the left word line WLL, and the right word line WLR are kept at a high level, the NMOS transistors N3, N4, and N5 are all turned on, and data to be written is loaded onto the write bit line.

Assuming that before a write operation, the storage node Q is at a high level, QB is at a low level, i.e. the storage data is "1", and data "0" is written, data "0" to be written is loaded onto the write bit line, i.e. BL is at a low level and BLB is at a high level. BL pulls down storage node Q through NMOS pipe N2, BLB pulls up storage node QB through PMOS pipe P1, and the feedback mechanism of latching structure is broken, and data "0" is write in the memory circuit.

Assuming that before a write operation, the storage node Q is at a low level and QB is at a high level, i.e. the storage data is "0", and data "1" is written, data "1" to be written is loaded onto the write bit line, i.e. BL is at a high level and BLB is at a low level. BL pulls up the storage node Q through P2, BLB pulls down the storage node QB through N1, the feedback mechanism of the latch structure is broken, and data "1" is written into the storage circuit.

(3) Read operation

During the read operation, the external control signal line EN and the left word line WLL are at a low level, the right word line WLR is at a high level, the NMOS transistors N4 and N5 are turned off, and the NMOS transistor N3 is turned on, i.e., the single-sided read operation is performed.

Assuming that before a read operation, the storage node Q is at a high level and QB is at a low level, that is, the stored data is "1", at the beginning of the read operation, the bit line BLB is precharged to a high level, the storage node Q controls the gate of N1, N1 is turned on when Q is at a high level, the bit line BLB is discharged to a low level through the NMOS transistors N3 and N1, and the operation of reading "1" is completed through the sense amplifier SA.

Assuming that the storage node Q is at a low level and QB is at a high level, that is, the storage data Q is "0", at the beginning of the read operation, the bit line BLB is precharged to a high level, the storage node Q is at a low level, the NMOS transistor N1 is controlled to be turned off, the bit line BLB cannot discharge, and still maintains a high level, and the operation of reading "0" is completed through the sense amplifier SA.

Based on this, a truth table for implementing the SRAM mode is shown in the following table, where L represents a low level, H represents a high level, read represents a Read operation, write represents a Write operation, and Hold represents a Hold state.

Table 1: SRAM truth table

Therefore, the memory circuit of the present embodiment can improve the problem of read disturb when reading data stored inside the memory circuit through the bit line, not only by spacing the read port from the storage node Q. Meanwhile, only one transistor is added, and compared with 8T-SRAM, 9T-SRAM and 10T-SRAM, the area occupation is reduced on the basis of improving the read interference, so that the structure has a good area advantage compared with the existing structure for improving the read interference.

Example 2

The embodiment introduces a memory computing circuit with BCAM addressing and logical operation functions, which is formed by a plurality of identical memory cells in an N multiplied by M array form; wherein N is the row number of the memory cell, and M is the column number of the memory cell; each row of memory cells shares a left word line WLL and a right word line WLR; each column of memory cells shares bit lines BL, BLB; the storage unit adopts the circuit structure of the storage circuit and realizes the complete function of the circuit structure.

The number of the sense amplifiers is the same as that of the bit lines, the bit line BL or BLB in each column of memory cells is respectively used as one path of input of one sense amplifier, and the other path of the input of the reference voltage of the sense amplifier; when the level of the BL or BLB is higher than the reference voltage, the sense amplifier outputs a high level, otherwise, the sense amplifier outputs a low level. The number of the AND gates is half of the number of the columns of the storage units, and the output ends of two sense amplifiers in each column of the storage units are respectively used as two paths of inputs of one AND gate; and when the outputs of the two sensitive amplifiers are both high level, the AND gate outputs high level, otherwise, the AND gate outputs low level.

Based on the circuit, the embodiment not only can realize the function of the SRAM mode, but also can realize memory Boolean logic operation, BCAM addressing and multiplication operation based on the mutual cooperation between different columns and rows. The following describes in detail how these operations are implemented.

1. Memory boolean logic operation

When the memory Boolean logic operation is executed, the left word line WLL and the control signal line EN of the memory unit in the same row keep low level, the right word line WLR of the memory unit needing to participate in the memory Boolean logic operation is set to be high level, and the rest word lines are set to be low level; the voltage on the bit line BLB is compared with a reference voltage by a sense amplifier SA, and then a corresponding memory Boolean logic operation result is output.

As shown in fig. 2, taking two 1-bit logical and-nand for storing data as an example, the implementation of and-nand function for storing data between two rows in the same column is described.

The left word lines WLL and the external control signal line EN of the two memory cells are always at low potential, so the NMOS transistors N4 and N5 are always in an off state, the memory cells in two rows are respectively labeled as a and B, the word lines in the a-th row are labeled as WLL0 and WLR0, the word lines in the B-th row are labeled as WLL1 and WLR1, and the bit lines BL and BLB are shared by a and B. Whether the right word line WLR is started or not determines whether the row participates in operation, a sense amplifier SA is configured for the right word line WLR, the other end of the SA is connected with a reference voltage VREF1, the voltage of a bit line BLB is compared with the reference voltage VREF1 by the sense amplifier, and then the operation results of logical AND and NOT-AND of A and B are output.

Bit line BLB is precharged to high while right word lines WLR0 and WLR1 of both cells are turned on, i.e., WLR0 and WLR1 are high. When the data stored in the cell is "1", that is, Q is high level, QB is low level, a ground path is formed between the bit lines BLB and GND, the charges on BLB flow to GND, at this time, the bit lines BLB are discharged, the discharging speeds of the bit lines BLB are the same when the data stored in a or B is 1, the discharging speeds of the bit lines BLB are faster when the data stored in a and B are both 1, the reference voltage VREF1 of the sense amplifier SA is set by using the difference between the discharging speeds of the bit lines when both the data stored in two cells are "1" and only one cell stores "1" in the same time, that is, the reference voltage VREF1 of the sense amplifier SA is between the bit line voltage after the two cells are discharged and the bit line voltage after one cell is discharged in the same time, if VBLB > VREF1, at least one of the data stored in a and B is "0" or both of the data are "0". If VBLB < VREF1, both A and B store data as "1".

Since the principle of and operation is that a high level is output only when both operands are high, and nand operation is that a low level is output only when both operands are high. Therefore, in the present embodiment, a simulation experiment is performed, and as can be seen from the simulation result in fig. 3, if and only if both the upper and lower cells are discharged, the output of the sense amplifier is "0", otherwise, the output is "1", the nand operation results of a and B are output, the output of the other end of the sense amplifier SA is opposite to the output of the other end, and the output of the phase of a and B is opposite to the output of the other end. The principle of and nand operations between rows is the same as the principle of operations between two rows.

As shown in FIG. 4, the implementation of OR and NOT functions between two rows in the same column will be described by taking two 1-bit logical OR and NOT for storing data as an example.

The setting condition of the AND/OR operation of A and B is the same as the setting condition of the AND/OR operation, the difference is that one end of SA is connected with a bit line BLB when the A and B perform the OR/OR operation, the other end is connected with a reference voltage VREF2, and the SA compares the voltage of the bit line BLB with the reference voltage VREF2 and outputs the logical OR/OR operation result of the A and B.

Bit line BLB is precharged to high level, right word lines WLR0 and WLR1 of the two cells are simultaneously turned on, when any or all stored data in the cell is "1", namely Q is 1 and QB is 0, a ground path is formed between bit lines BLB and GND, charges on bit line BLB flow to GND, and bit line BLB is discharged. The judgment is made by using the principle that the bit line BLB is not discharged when the stored data in the A-th row and the B-th row are both low level and the bit line BLB is discharged when one of the stored data in the A or B is high level. The reference voltage VREF2 for SA lies between the bitline voltage not discharged and the bitline voltage after one cell is discharged. If VBLB > VREF2, the data stored in A and B are both '0'; if VBLB < VREF2, then at least one of a or B stores a data of "1" or both are "1".

Since the principle of or operation is that only two operands are low, a low level is output, or only two operands are low, a high level is output, so the simulation result of fig. 5 shows that only when the stored data of two cells are both "0", that is, the right bit line BLB in the two cells is not discharged to ground, BLB maintains a high level, the output result of SA is "1", any cell stores data "1", that is, when the right bit line BLB in any cell is discharged to ground, the output result of SA is "0", the reference voltage VREF2 of SA at this time is between the bit line voltage not discharged and the bit line voltage after one cell is discharged, and one end of the sense amplifier SA outputs the nor operation results of a and B, and the other end outputs the opposite, and outputs the or operation results of a and B phases. The principle of the OR and OR NOT operation between the rows is the same as the principle of the operation between the two rows.

Based on this, the memory computing circuit of the embodiment can implement logical operations and nand operations, or and or non-operations; it is emphasized that the two outputs of the sense amplifier output opposite results, the output on the same side as the input connected to bit line BLB outputs the nand or result, and the output on the same side as the input connected to the reference voltage outputs the and or result.

The truth table for implementing the logical AND and NAND, OR AND OR NOT mode between two rows in the same column in the Boolean logic operation is shown in the following table, wherein A represents the stored data of the A-th row, B represents the stored data of the B-th row, L represents the low level, and H represents the high level.

Table 2: in-memory boolean logic operation truth table

2. BCAM addressing operations

Keeping the control signal line EN of the storage units in the same column at a low level; inputting a voltage signal corresponding to the search data and an opposite signal thereof to a memory cell pre-storing data to be searched through a left word line WLL and a right word line WLR respectively; the result of whether the two single-ended sense amplifiers SA are matched or not is represented by two single-ended sense amplifiers SA and an and gate output. The output end of the AND gate outputs high level to indicate matching; the output of the and gate outputs a low level indicating a mismatch.

As shown in fig. 6, in the BCAM operation mode, the external control signal line EN is always at a low level, that is, the NMOS transistor N5 is in an off state, binary data to be searched is stored in the internal Q node of the memory cell, the search line is a left word line WLL, the left word line WLL is a high level or a low level corresponding to the binary data of the search data, the right word line WLR is a high level or a low level corresponding to an inverse code of the binary data of the search data, the corresponding word line is set at a high level when the data is "1", the corresponding word line is set at a low level when the data is "0", the lower ends of the left and right bit lines BL and BLB are respectively connected to one sense amplifier SA, outputs of the two SAs are connected to one and gate, and an output result of the and gate indicates whether the two SA are matched. Before data searching, a storage unit stores binary data to be searched, left and right bit lines BL and BLB are precharged to a high level, left and right word lines are respectively set to a high level or a low level according to search data, then whether the bit lines are discharged or not is controlled according to whether the data to be searched and the search data are matched, discharging is not carried out when the bit lines are matched, otherwise discharging is carried out, only when the left and right bit lines of the column are not discharged, the output of a sense amplifier SA is the high level, the output is the high level after passing through an AND gate, matching is shown, otherwise, the output of the AND gate is the low level, and mismatching is shown.

Analyzing the data comparison process, wherein when the search data is '0', the left word line WLL is at a low level, the NMOS transistor N4 is turned off, the BL cannot discharge, and the high level is maintained, the right word line WLR is at a high level, the NMOS transistor N3 is turned on, assuming that the storage node Q is '0', the gate acting on the NMOS transistor N1 controls N1 to be turned off, the BLB discharge path is pinched off, and the BLB does not discharge, which indicates that the bit lines BL and BLB do not discharge at the moment, and the unit data are matched; assuming that the storage node Q is "1", the gate of the NMOS transistor N1 controls N1 to be turned on, BLB is discharged, and the bit line BL is not discharged and the bit line BLB is discharged, which results in a mismatch of cell data. Similarly, when the search data is "1", the right word line WLR is at a low level, the NMOS transistor N3 is turned off, the BLB cannot discharge, and the high level is maintained, the left word line WLL is at a high level at this time, the NMOS transistor N3 is turned on, assuming that the storage node Q is "0", the storage node QB is "1", the gate acting on N2 controls the NMOS transistor N2 to be turned on, and the BL discharges, and the bit line BLB does not discharge at this time, the bit line BL discharges, the unit data does not match, assuming that the storage node Q is "1", the storage node QB is "0", the gate acting on N2 controls the NMOS transistor N2 to be turned off, and the BL does not discharge, and then the bit lines BL and BLB do not discharge at this time, and the unit data matches.

With reference to fig. 6, taking 4 × 4 memory cells for performing a BCAM operation as an example, four pairs of word lines in the first row to the fourth row are respectively denoted as WLL0 and WLR0; WLL1, WLR1; WLL2, WLR2; WLL3, WLR3, the four pairs of bit lines from the first column to the fourth column are marked as BL0, BLB0 respectively; BL1, BLB1; BL2, BLB2; BL3, BLB3. In order to more clearly show the technical solutions and the technical effects thereof provided by the present invention, a four-bit binary data "0011" is used for column search, i.e. the searched data is "0011", the "0" is low level, and the "1" is high level. Therefore, the left word lines WLL0, WLL1, WLL2, WLL3 are respectively set to low level, high level, and the right word lines WLR0, WLR1, WLR2, WLR3 are respectively set to high level, low level, and low level. The array has four columns in total, and the data stored in each column from left to right are "0111", "0011", "1011", "1101" in sequence.

As can be seen from the above analysis, the data stored in the first column is "0111", and although the data stored in the second row is "1", the left word line WLL1 is at a low level and in an off state, so the left bit line BL0 is not discharged and SA outputs "1", but the right word line WLR1 and the left word line WLL1 are in a reverse state, so the right word line WLR1 is at a high level, the pass transistor N3 is turned on, at this time BLB0 is discharged, SA outputs "0", and the results of both SAs are output as "0" via the and gate, so the data stored in the first column does not match the search data.

The second column stores data "0011", at which point the bit lines BL1, BLB1 are not discharged, both SA outputs are "1", and the and gate outputs "1", so the second column matches the search data.

The data stored in the third column is "1011", although the data "1" stored in the first row does not match the search data, since the left word line WLL0 is at a low level and is in an off state, the left bit line BL2 is not discharged, SA outputs "1", but the right word line WLR0 is in a state opposite to the left word line WLL0, at this time, WLR0 is at a high level, the pass transistor N3 is turned on, the right bit line BLB2 is discharged, SA outputs "0", and the results of the two SAs are "0" after being output through the and gate, so the data stored in the third column does not match the search data.

The data stored in the fourth column is '1101', the data stored in the first row, the second row and the third row are different from the search data, but since the left word lines WLL0 and WLL1 of the first row and the second row are at low level, the pass transistor N4 is not turned on, the left bit line BL3 is not affected, the left word line WLL2 of the third row is at high level, the pass transistor N4 is turned on, the BL3 is discharged, the SA outputs '0', the right word lines WLR0, WLR1 and WLR2 are opposite to the left word lines WLL0, WLL1 and WLL2, the pass transistors N4 of the first row and the second row are turned on, the right bit line BLB3 is discharged, the SA outputs '0', and the results of the two SAs are '0' after being output by the and gate, the data stored in the fourth column are not matched with the search data.

Eventually it can be known that only the second column matches the search data. As can be known from the simulation result of the BCAM in fig. 7, when the four cell data in a column are all matched, the left and right bit lines BL and BLB are not discharged to maintain a high level, and then the BL and BLB output a high level after passing through two sense amplifiers and an and gate, which indicates that the search data is matched with the data to be searched; on the contrary, when the four cells in a column have cells with unmatched data, one of the left and right bit lines BL and BLB is discharged, and then the BL and BLB output a low level after passing through two sense amplifiers and an and gate, which indicates that the search data is unmatched with the data to be searched.

3. Multiplication operation

The left word line WLL and the external control signal EN remain low, the multiplicand is represented by a different voltage operating on the right word line WLR, the multiplier is stored inside the memory cell, and its multiplication output is represented by the amount of discharge on the right bit line BLB. Each storage unit completes 2-bit multiplied by 1-bit multiplication in each calculation stage, a 2-bit multiplicand acts on a right word line WLR, the multiplication is realized by converting the multiplicand into word line voltage, and the multiplier acts inside the storage unit.

Referring to fig. 8, the manner of implementing the function of the present embodiment is described by taking the implementation of binary multiplication of 4 bits × 1bit as an example. To realize 4bit × 1bit binary multiplication, only two units for realizing 2bit × 1bit binary multiplication need to discharge through one bit line.

First, a single memory cell is set to be able to perform binary multiplication of a 2-bit multiplicand and a 1-bit multiplier, and the 2-bit multiplicand, i.e., "00", "01", "10" and "11", corresponds to voltages 0 and V of four WLRs, respectively _WLR1 、V _WLR2 、V _WLR3 Different voltages of the right word line act on the grid of the NMOS transistor N3, different grid voltages control different conduction degrees of the NMOS and different currents flow under the same time, so that multiplicands with different weights are distinguished, binary multipliers are '0' and '1', and the binary multipliers are stored in an internal node Q of the storage unit. First go to bit line BLBAnd (2) line pre-charging, when the binary multiplier is '0', no matter what the grid voltage of the transistor N3 is, the discharge quantity on the bit line BLB is always zero, when the binary multiplier is '1', the NMOS transistor N1 is controlled to be conducted, and the discharge quantity of the bit line BLB depends on the grid voltage of the control transistor N3, so that the purpose of distinguishing 2bit multiplied by 1bit binary multiplication results is achieved.

The truth table for implementing a 2bit by 1bit binary multiplication operation is shown in the following table, where X represents any 2bit data and its corresponding wordline voltage.

Table 3:2bit x 1bit binary multiplication result truth table

Two units for realizing 2-bit multiplied by 1-bit binary multiplication realize 4-bit multiplied by 1-bit binary multiplication through one bit line discharge, and the high 2-bit and low 2-bit can be distinguished through a transistor size weighting technology, a capacitor array weighting technology, a pulse number/height/width weighting technology and the like. In this description, the selection is made by way of example of a pulse width modulation technique, which operates in a similar manner to the pulse width modulation technique, and bit line BLB is precharged to a high level to obtain different weighting currents according to different multiplicands and multipliers.

The truth table for implementing a 4bit by 1bit binary multiplication is shown in the following table, where X represents any 4bit data.

Table 4:4bit x 1bit binary multiplication result truth table

Fig. 9 is a schematic diagram of a 4bit × 1bit binary multiplication result, a computation capacitor is externally connected to the bit line BLB, the weighted current is converted into a weighted voltage, and analog-to-digital conversion is performed by the ADC, so that a binary number representing the 4bit × 1bit binary multiplication result is obtained. Therefore, the in-memory computing circuit of this embodiment can obtain 16 multiplication results of a 4bit × 1bit binary multiplication operation when performing the multiplication operation.

The way of distinguishing the multiplication result is to distinguish the multiplication result according to the different discharge quantities of the bit lines, the linearity between the different discharge quantities of the bit lines can be measured by the voltage variation quantity of the bit lines and the Integral Nonlinearity (INL), fig. 10 is the measured INL value, and it can be known from fig. 9 that the linearity is worst when the multiplication result is 9, and the INL value is 0.62LSB at this time, but the INL value is still small and the linearity is better. Therefore, the embodiment can effectively realize the 4bit × 1bit binary multiplication operation.

In summary, the memory computing circuit of the present embodiment not only has the same effects as those of embodiment 1, but also can perform operations for the entire array in the array configured in accordance with embodiment 1. In addition, simple Boolean logic operation, BCAM addressing operation and 4bit multiplied by 1bit binary operation can be carried out, and various operation modes can be satisfied.

Example 3

The embodiment describes a memory chip, which is formed by packaging the memory circuit. The pin of the memory chip includes: the grounding pin is connected with the source electrodes of the PMOS tubes P1 and P2; the power supply pin is connected with the source electrodes of the NMOS tubes N1 and N2; the first pin is connected with the source electrode of the NMOS transistor N4; the second pin is connected with the source electrode of the NMOS tube N3; a third pin connected with the grid of the NMOS tube N4; and the fourth pin is connected with the grid electrode of the NMOS transistor N3.

The mode of packaging the storage circuit into a chip is easier for the use of technicians in the field and is also beneficial to the popularization and the use of the storage circuit.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above examples only show several embodiments of the present invention, and the description thereof is specific and detailed, but not to be construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A memory circuit is characterized by comprising NMOS transistors N1-N5 and PMOS transistors P0-P1; N1-N4 and P0-P1 form a 6T-SRAM unit, N5 is connected between two MOS tubes corresponding to any storage node of the 6T-SRAM unit, and the grid electrode of N5 is controlled by a control signal line EN; the specific connection mode of the storage circuit is as follows:

the grid electrode of the N1 is electrically connected with the drain electrode of the N2, the drain electrode of the N4 and the grid electrode of the P1; the drain electrode of the N1 is electrically connected with the drain electrode of the N3 and the source electrode of the N5; the source electrode of the N1 and the source electrode of the N2 are connected with GND; the grid electrode of the P2 is electrically connected with the drain electrode of the P1, the grid electrode of the N2 and the drain electrode of the N5; the drain electrode of the P2 is electrically connected with the grid electrode of the N1, the drain electrode of the N2, the drain electrode of the N4 and the grid electrode of the P1; the source electrode of the P1 and the source electrode of the P2 are connected with VDD; the grid of N3 is connected with the right word line WLR, the grid of N4 is connected with the left word line WLL, and the grid of N5 is electrically connected with an external control signal line EN; the source of N3 is connected with the bit line BLB, and the source of N4 is connected with the bit line BL;

p2 and N2 form an inverter, and N3 and N4 form a transmission tube of the storage circuit; storage node Q is connected to bit line BL via N4, and storage node QB is connected to bit line BLB via N5, N3.

2. The memory circuit of claim 1, wherein the memory circuit implements an SRAM mode comprising a hold operation, a write operation, and a read operation; when the storage circuit executes a holding operation, the control signal line EN keeps a high level, the left word line WLL and the right word line WLR keep a low level, and a latch structure formed by P1, P2, N1, N2 and N5 latches storage data of storage nodes Q and QB; when the storage circuit executes write operation, a control signal line EN keeps high level, a left word line WLL and a right word line WLR are pulled to high level, and data needing to be written are loaded on bit lines; when the storage circuit executes reading operation, the bit line BLB is precharged to a high level, the control signal line EN is at a low level, the left word line WLL is pulled down, the right word line WLR keeps at a high level, and the result is read through the sense amplifier SA.

3. A memory computing circuit with BCAM addressing and logical operation functions is composed of a plurality of same memory units in an N multiplied by M array form; wherein N is the row number of the memory cell, and M is the column number of the memory cell; each row of memory cells shares a left word line WLL and a right word line WLR; each column of memory cells shares bit lines BL and BLB;

wherein the memory cell adopts the circuit structure of the memory circuit according to any one of claims 1-2, and realizes the complete function of the circuit structure.

4. The memory computing circuit with BCAM addressing and logic operation functions of claim 3, wherein all bit lines BL, BLB are connected with sense amplifiers in one-to-one correspondence; bit lines BL or BLB in each column of memory cells are respectively used as one path of input of a sense amplifier, and the other path of the sense amplifier is input with reference voltage; when the level of the BL or BLB is higher than the reference voltage, the sense amplifier outputs a high level, otherwise, the sense amplifier outputs a low level.

5. The memory computing circuit with BCAM addressing and logical operation functions of claim 3, wherein the bit lines BL, BLB of each column of memory cells are connected to an AND gate through a single-ended sense amplifier; the output ends of the two single-ended sensitive amplifiers are respectively used as two paths of input of an AND gate; and when the outputs of the two sensitive amplifiers are both high level, the AND gate outputs high level, otherwise, the AND gate outputs low level.

6. The memory computing circuit with BCAM addressing and logic operation functions of claim 4 or 5, wherein when the memory computing circuit executes a memory boolean logic operation, the output terminal of the sense amplifier connected to the bit line BLB is used as the result output terminal for executing the operation; when the memory computing circuit executes BCAM operation, the output end of the AND gate is used as the result output end for executing the operation; when the memory calculation circuit executes multiplication, the discharge quantity of the bit line BLB is the result of the multiplication.

7. The memory computing circuit with BCAM addressing and logic operation functions of claim 6, wherein the memory computing circuit implements the memory boolean logic operation as follows:

keeping the left word line WLL and the control signal line EN of the same row of storage units at low level, setting the right word line WLR of the storage units needing to participate in the memory Boolean logic operation to be at high level, and setting the rest word lines to be at low level; the voltage on the bit line BLB is compared with a reference voltage by a sense amplifier and then a corresponding memory Boolean logic operation result is output.

8. The memory computing circuit with BCAM addressing and logic operation functions of claim 6, wherein said memory computing circuit implements BCAM operations as follows:

keeping a control signal line EN of the storage units in the same column at a low level; inputting a voltage signal corresponding to the search data and an opposite signal thereof to a memory cell pre-storing data to be searched through a left word line WLL and a right word line WLR respectively; outputting voltage signals of bit lines BL and BLB representing the operation result through two single-ended sense amplifiers and an AND gate; the output end of the AND gate outputs high level to represent that the search data is matched with the data to be searched; and the output end of the AND gate outputs a low level, which indicates that the search data is not matched with the data to be searched.

9. The memory compute circuit having BCAM addressing and logic operation functions of claim 6, wherein the memory compute circuit implements multiplication as follows:

and keeping the control signal line EN and the left word line WLL of the same row of storage units at low level, inputting a voltage signal corresponding to a multiplicand into the storage unit in which the multiplier is prestored through the right word line WLR, and obtaining a required multiplication result according to the discharge amount of the bit line BLB.

10. A memory chip, wherein it is packaged by using the memory circuit according to any one of claims 1-2; the pin of the memory chip comprises:

the grounding pin is connected with the source electrodes of the PMOS tubes P1 and P2;

the power supply pin is connected with the source electrodes of the NMOS tubes N1 and N2;

the first pin is connected with the source electrode of the NMOS transistor N4;

the second pin is connected with the source electrode of the NMOS tube N3;

a third pin connected with the grid of the NMOS tube N4;

and the fourth pin is connected with the grid electrode of the NMOS transistor N3.

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