CN115804261A

CN115804261A - Display device

Info

Publication number: CN115804261A
Application number: CN202180041408.1A
Authority: CN
Inventors: 朴成镇; 柳俊锡; 姜敏霞; 金裕勳
Original assignee: LG Display Co Ltd
Current assignee: LG Display Co Ltd
Priority date: 2020-07-09
Filing date: 2021-07-08
Publication date: 2023-03-14
Also published as: DE112021003662T5; WO2022010278A1

Abstract

A display device, comprising: a first display region including a plurality of first pixel groups; and a second display region including a plurality of second pixel groups and a plurality of light-transmitting regions, wherein each of the plurality of second pixel groups includes a plurality of sub-pixels, and the light-emitting element is disposed in the light-transmitting region in any one of the plurality of sub-pixels.

Description

Display device

Technical Field

Embodiments herein relate to a display device.

Background

Electroluminescent display devices are classified into inorganic light emitting display devices and organic light emitting display devices according to the material of a light emitting layer. An active matrix type (active matrix type) Organic Light Emitting display device includes an Organic Light Emitting Diode (hereinafter, referred to as "OLED") that emits Light by itself, and has advantages in fast response time, high Light Emitting efficiency, high luminance, and a wide viewing angle. The Organic Light Emitting display device has an OLED (Organic Light Emitting Diode) formed in each pixel. The organic light emitting display device can represent a black gray as perfect black in addition to a fast response time, high light emitting efficiency, high luminance, and a wide viewing angle, and thus has excellent contrast ratio (contrast ratio) and color gamut.

Recently, multimedia functions of mobile terminals have been improved. For example, a camera is basically built in a mobile terminal and the resolution of the camera is gradually increased to the level of the existing digital camera. However, the front camera of the mobile terminal limits the design of the screen, thereby making it difficult to design the screen. In order to reduce the space occupied by the camera, screen designs including a notch (notch) or a punch (punch) have been adopted in the mobile terminal, but it is difficult to implement a Full-screen display (Full-screen display) because the screen size is still limited due to the camera.

In order to realize full-screen display, a method has been proposed in which an imaging area provided with low-resolution pixels is prepared in a screen of a display panel, and a camera and/or various sensors are provided in the imaging area.

Disclosure of Invention

Technical problem

The present invention is directed to providing a display device with improved picture quality in an imaging area (a down-screen camera (UDC) area) provided with a camera module.

It should be noted that the object of the present disclosure is not limited to the above object, and other objects of the present disclosure will be apparent to those skilled in the art from the following description.

Technical scheme

According to an aspect of the present disclosure, there is provided a display device including: a first display region including a plurality of first pixel groups; and a second display region including a plurality of second pixel groups and a plurality of light-transmitting regions, wherein each of the plurality of second pixel groups includes a plurality of sub-pixels, and a light-emitting element is disposed in the light-transmitting region in any one of the plurality of sub-pixels.

The second display region may include a first pixel row in which the plurality of second pixel groups are continuously disposed along a first direction, and a second pixel row in which the plurality of light-transmitting regions are continuously disposed along the first direction, wherein the first pixel row and the second pixel row may be alternately disposed along a second direction crossing the first direction.

The plurality of sub-pixels may include: a first sub-pixel including a first light emitting element, a second sub-pixel including a second light emitting element, a third sub-pixel including a third light emitting element, and a fourth sub-pixel including a fourth light emitting element, wherein a partial region of at least one of the second light emitting element and the fourth light emitting element may be disposed in the light transmitting region.

The second light emitting element and the fourth light emitting element may be green light emitting elements.

A first virtual line connecting centers of each of the second and fourth light emitting elements may cross the first and second directions.

Each of the plurality of first pixel groups may include a first green light emitting element and a second green light emitting element, wherein a virtual line connecting centers of each of the first green light emitting element and the second green light emitting element may be parallel to the first direction.

The second light emitting element may be disposed at one side of a second virtual line passing through a center of each of the first and third light emitting elements, and the fourth light emitting element may be disposed at the other side of the second virtual line.

The first to fourth light emitting elements of the plurality of second pixel groups may have a structure in which light emitting elements of the same color are arranged in a quadrangular shape.

The fourth light emitting elements of the plurality of second pixel groups may be disposed along each of a plurality of square lines, and the first, second, and third light emitting elements may be disposed inside each of the plurality of square lines.

The resolution of the second display region may be lower than the resolution of the first display region.

The display device may include lines disposed in the first display region and the second display region, wherein the lines may be disposed to bypass the light transmission region.

The display device may include a cathode disposed in the first display region and the second display region, wherein the cathode may include an opening corresponding to the light transmission region.

The shape of the light emitting element of the first pixel group may be different from the shape of the light emitting element of the second pixel group.

According to another aspect of the present disclosure, there is provided a display device including: a first display region including a plurality of first pixel groups; and a second display region including a plurality of second pixel groups and a plurality of light transmission regions, wherein the plurality of second pixel groups include a plurality of sub-pixels, the plurality of second pixel groups include a first light emitting element configured to emit red light, a third light emitting element configured to emit blue light, and a second light emitting element and a fourth light emitting element configured to emit green light, and a first virtual line connecting centers of each of the second light emitting element and the fourth light emitting element crosses a second virtual line connecting centers of each of the first light emitting element and the third light emitting element.

The second light emitting element may be disposed at one side of the second virtual line with reference to the second virtual line, and the fourth light emitting element may be disposed at the other side of the second virtual line.

The second display region may include a first pixel row in which the plurality of second pixel groups are continuously disposed, and a second pixel row in which the plurality of light-transmitting regions are continuously disposed.

A portion of at least one of the second light emitting element and the fourth light emitting element may be disposed in the light transmission region.

The number of the plurality of second pixel groups disposed in the second display region may be less than the number of the plurality of first pixel groups disposed in the first display region.

According to still another aspect of the present disclosure, there is provided a display device including: a first display region including a plurality of first pixel groups; and a second display region including a plurality of second pixel groups and a plurality of light transmission regions, wherein the second display region includes: a first unit region having a smaller number of pixels than the first display region; and a second unit region having a smaller number of pixels than the first unit region.

An image sensor may be disposed in the first unit area, and an infrared sensor may be disposed in the second unit area.

Advantageous effects

According to the embodiments, the picture quality in the imaging region can be improved. In addition, data noise of an image photographed in a state where light transmittance is increased may be reduced, so that camera performance may be improved.

The effects of the present disclosure are not limited to the above-described effects, and other effects not mentioned will be clearly understood from the subsequent claims by those skilled in the art.

Drawings

The above and other objects, features and advantages of the present disclosure will become more apparent to those of ordinary skill in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

FIG. 1 is a conceptual diagram of a display device according to one embodiment of the present disclosure;

fig. 2a to 2d are views illustrating various arrangement positions and shapes of the second display region;

fig. 3 is a schematic cross-sectional view illustrating a display panel according to an embodiment of the present disclosure;

fig. 4 is a view illustrating a pixel arrangement in a first display region according to one embodiment of the present disclosure;

fig. 5 is a view illustrating a pixel and a light transmission region of a second display region;

fig. 6 is a schematic diagram illustrating a structure of a display panel of a second display region;

FIG. 7 is a modification of FIG. 6;

fig. 8 is a view illustrating a pixel arrangement in a second display region according to a first embodiment of the present disclosure;

FIG. 9 is an enlarged partial view of FIG. 8;

fig. 10 is a view illustrating a pixel arrangement in a second display region according to a second embodiment of the present disclosure;

FIG. 11a is an enlarged view of a portion of FIG. 10;

FIG. 11b is a modification of FIG. 11 a;

fig. 12 is a view illustrating a pixel arrangement in a second display region according to a third embodiment of the present disclosure;

fig. 13 is a first comparative example illustrating the pixel arrangement in the second display region;

fig. 14 illustrates an observation result of whether a pattern is recognized from the outside;

fig. 15 is a second comparative example illustrating the arrangement of pixels in the second display region;

fig. 16 is a view illustrating a pixel arrangement in a second display region according to a fourth embodiment of the present disclosure;

fig. 17 is a view illustrating a pixel arrangement in a second display region according to a fifth embodiment of the present disclosure;

fig. 18 is a view illustrating a pixel arrangement in a second display region according to a sixth embodiment of the present disclosure;

fig. 19 is a view illustrating a pixel arrangement in a second display region according to a seventh embodiment of the present disclosure;

fig. 20 is a view illustrating a pixel arrangement in a second display region according to an eighth embodiment of the present disclosure;

FIG. 21 is an enlarged view of FIG. 20;

FIG. 22 is a modification of FIG. 21;

fig. 23 is a second modification of fig. 21;

fig. 24a is a view illustrating a pixel arrangement in a second display region according to a ninth embodiment of the present disclosure;

fig. 24b is a view illustrating a structure in which the area of a light-transmitting region is changed in a second display region;

fig. 25 is a view illustrating a pixel arrangement in a second display region according to a tenth embodiment of the present disclosure;

FIG. 26 is an enlarged view of FIG. 25;

fig. 27 is a view illustrating a pixel arrangement in a second display region according to an eleventh embodiment of the present disclosure;

fig. 28 is a view illustrating a pixel arrangement in a second display region according to a twelfth embodiment of the present disclosure;

fig. 29 is a view illustrating a pixel arrangement in a second display region according to a thirteenth embodiment of the present disclosure;

fig. 30 is a view illustrating a pixel arrangement in a second display region according to a fourteenth embodiment of the present disclosure;

fig. 31 is a view illustrating a pixel arrangement in a second display region according to a fifteenth embodiment of the present disclosure;

fig. 32 is a view illustrating a pixel arrangement in a second display region according to a sixteenth embodiment of the present disclosure;

fig. 33 is a view illustrating a pixel arrangement in a second display region according to a seventeenth embodiment of the present disclosure;

fig. 34 is a block diagram illustrating a display panel and a display panel driving unit according to an embodiment of the present disclosure;

fig. 35 is a schematic block diagram illustrating a configuration of a driver Integrated Circuit (IC);

fig. 36 is a circuit diagram illustrating an example of a pixel circuit;

fig. 37 is a circuit diagram illustrating another example of a pixel circuit;

fig. 38 is a view illustrating a method of driving a pixel circuit;

fig. 39 is a cross-sectional view illustrating in detail a cross-sectional structure of a pixel region in a display panel according to one embodiment of the present disclosure;

fig. 40 illustrates a sectional structure of a pixel region and a light-transmitting region of a second display region according to an embodiment of the present disclosure;

fig. 41 is a view illustrating data voltages applied to pixels of the first display region and data voltages applied to pixels of the second display region.

Detailed Description

Advantages and features of the present disclosure and methods of accomplishing the same will be set forth in the following description of embodiments with reference to the accompanying drawings. However, the present disclosure is not limited to the embodiments described below, but may be embodied in various different forms. These embodiments are provided only for a complete understanding of the scope of the present disclosure by those skilled in the art, and the present disclosure is limited only by the scope of the claims.

The figures, dimensions, proportions, angles, quantities, and the like disclosed in the accompanying drawings for purposes of describing embodiments of the present disclosure are illustrative only and are not intended to be limiting of the details shown in the present disclosure. Like reference numerals refer to like elements throughout. Also, in describing the present disclosure, when it is determined that a detailed description of known technology may unnecessarily obscure the subject matter of the present invention, the detailed description of known technology may be omitted.

As used herein, terms such as "comprising," "including," "consisting of, \82303030, are intended to allow the addition of other elements unless these terms are used in conjunction with the term" only. Any reference to singular may include the plural unless explicitly stated otherwise.

Components are to be construed as including common error ranges even if not explicitly described.

For describing the positional relationship, for example, when the positional relationship between two members is described as "on 82303030, as", "on 8230, as" below "and" after 8230, and the like, one or more members may be interposed between the two members unless the terms "immediately" or "directly" are used in the expression.

In describing embodiments, the terms "first," "second," and the like may be used herein to describe various components, but the components are not limited by these. These terms are only used to distinguish one element from another. Thus, a first component discussed below could be termed a second component without departing from the teachings of the present disclosure.

Like reference numerals refer to like elements throughout.

The features of the various embodiments may be combined with each other, in part or in whole. Embodiments may interoperate in various technologies and may be implemented independently of each other or in association with each other.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

Fig. 1 is a conceptual diagram of a display device according to an embodiment of the present disclosure, fig. 2a to 2d are views illustrating various arrangement positions and shapes of a second display region, fig. 3 is a schematic sectional view illustrating a display panel according to an embodiment of the present disclosure, and fig. 4 is a view illustrating an arrangement of pixels in a first display region according to an embodiment of the present disclosure.

Referring to fig. 1, a display panel 100 and a housing may be included, and the entire surface of the display panel 100 may be formed as a display region. Thus, a Full-screen display (Full-screen display) can be realized.

The display area may include a first display area DA and a second display area CA. Both the first display area DA and the second display area CA may output images, but the resolutions may be different. As an example, the plurality of second pixels disposed in the second display area CA may have a lower resolution than the plurality of first pixels disposed in the first display area DA. By reducing the resolution in the plurality of second pixels provided in the second display area CA as much as possible, a sufficient amount of light can be injected into the

sensors

41 and 42 provided in the second display area CA.

However, the present disclosure is not limited thereto, and the resolution of the first display area DA and the resolution of the second display area CA may be the same as long as the second display area CA may have a sufficient light transmittance or an appropriate compensation algorithm may be implemented.

The second display area CA may be an area where the

sensors

41 and 42 are disposed. The second display area CA is an area overlapping with various sensors and thus may be smaller than an area of the first display area DA outputting most of the image. The second display area CA may be an imaging area where various sensors collect information.

The

sensors

41 and 42 may include at least one of an image sensor, a proximity sensor, an illumination sensor, a gesture sensor, a motion sensor, a fingerprint recognition sensor, and a bio-sensor. As an example, the first sensor 41 may be an illuminance sensor or an infrared sensor, and the second sensor 42 may be an image sensor configured to capture an image or video, but the present disclosure is not necessarily limited thereto.

Referring to fig. 2a to 2d, the second display area CA may be disposed at various positions where light is required to be incident. As an example, the second display area CA may be disposed at the upper left end of the display area as shown in fig. 2a, the second display area CA may be disposed at the upper right end of the display area as shown in fig. 2b, the second display area CA may be disposed at the entire upper end of the display area as shown in fig. 2c, and the width of the second display area CA may be variously modified as shown in fig. 2 d. However, the present disclosure is not necessarily limited thereto, and the second display area CA may be disposed at a central portion of the first display area DA or at a lower end of the display area.

Referring to fig. 3 and 4, the first and second display areas DA and CA may include a pixel array provided with pixels to which pixel data is written. The number of Pixels Per unit area (hereinafter, referred to as "Pixels Per Inch (PPI)") of the second display region CA may be lower than the PPI of the first display region DA in order to ensure the light transmittance of the second display region CA.

The pixel array of the first display region DA may include a pixel region provided with a plurality of pixel groups having a high PPI. The pixel array of the second display region CA may include a pixel region provided with a plurality of pixel groups having a relatively low PPI by being spaced apart by the light transmissive region. In the second display area CA, external light may pass through the display panel 100 through a light transmission area having high light transmittance and may be received by a sensor disposed under the display panel 100.

Since both the first display area DA and the second display area CA include pixels, an input image can be reproduced on the first display area DA and the second display area CA. Thus, a Full-screen display (Full-screen display) can be realized.

Each of the pixels of the first and second display regions DA and CA may include sub-pixels having different colors to realize colors of an image. The sub-pixels may include red, green, and blue sub-pixels. Although not shown in the drawings, the pixel group may further include a white subpixel. Each sub-pixel may include a pixel circuit part and a light emitting element (organic light emitting diode: OLED).

The second display area CA may include pixels and a camera module disposed under the screen of the display panel 100. The camera module may include an image sensor. The pixels of the second display area CA may display the input image by writing the pixel data of the input image in the display mode.

The camera module may take an external image in an imaging mode to output picture or video image data. The lens 30 of the camera module may face the second display area CA. External light is incident on the lens 30 of the camera module through the second display area CA, and the lens 30 may condense the light onto an image sensor omitted in the drawing. The camera module may take an external image in an imaging mode to output picture or video image data.

In order to secure the light transmittance, since the pixels are removed from the second display area CA, an image quality compensation algorithm for compensating the luminance and color coordinates of the pixels in the second display area CA may be applied.

The display panel 100 may have a width in an X-axis direction, a length in a Y-axis direction, and a thickness in a Z-axis direction. The display panel 100 may include a circuit layer 12 disposed on a substrate 10, and a light emitting element layer 14 disposed on the circuit layer 12. A polarizing plate 18 may be disposed on the light emitting element layer 14, and a cover glass 20 may be disposed on the polarizing plate 18.

The circuit layer 12 may include pixel circuits connected to lines such as data lines, gate lines, power supply lines, and the like; a gate driving unit connected to the gate lines, and the like.

The circuit layer 12 may include circuit elements such as transistors implemented as Thin Film Transistors (TFTs), capacitors, and the like. The lines and circuit elements of the circuit layer 12 may be implemented by a plurality of insulating layers, two or more metal layers separated from each other with the insulating layers interposed therebetween, and an active layer including a semiconductor material.

The light emitting element layer 14 may include light emitting elements driven by pixel circuits. The light emitting element may be implemented as an OLED. The OLED may include an organic compound layer formed between an anode and a cathode.

The organic compound layer may include a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an Emission layer (EML), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL), but the disclosure is not limited thereto.

When a voltage is applied to the anode and the cathode of the OLED, holes passing through the hole transport layer HTL and electrons passing through the electron transport layer ETL move to the light emitting layer EML to generate excitons, and thus visible light may be emitted from the light emitting layer EML.

The light emitting element layer 14 may further include a color filter array disposed on the pixels to selectively transmit light of red, green, and blue wavelengths.

The light-emitting element layer 14 may be covered with a protective film, and the protective film may be covered with an encapsulation layer (encapsulation layer). The protective film and the encapsulation layer may have a structure in which organic films and inorganic films are alternately stacked. The inorganic film may block permeation of moisture or oxygen. The organic film may planarize the surface of the inorganic film. When the organic film and the inorganic film are stacked in a multilayer, since the length of the movement path of moisture or oxygen is increased compared to that of a single layer, the permeation of moisture/oxygen affecting the light emitting element layer 14 can be effectively blocked.

A polarizing plate 18 may be disposed on the encapsulation layer. Polarizing plate 18 may improve outdoor visibility of the display device. The polarizing plate 18 may reduce reflection of light from the surface of the display panel 100 and block light reflected from the metal of the circuit layer 12, thereby improving the brightness of the pixel. The polarizing plate 18 may be implemented as a polarizing plate in which a linear polarizing plate and a phase retardation film are combined, or a circular polarizing plate.

Referring to fig. 4, the first display area DA may include a plurality of first pixel groups PG1 arranged in a matrix form. In the plurality of first pixel groups PG1, two subpixels may form one pixel using a subpixel rendering algorithm. For example, the first unit pixel PIX1 may include R and G1 sub-pixels SP1, SP2, and the second unit pixel PIX2 may include B and G2 sub-pixels SP3, SP4. Insufficient color rendering in each of the unit pixels PIX1 and PIX2 can be compensated for using an average value of respective pieces of corresponding color data between adjacent pixels. However, the present disclosure is not necessarily limited thereto, and the plurality of first pixel groups PG1 may be real type pixels including R, G, and B sub-pixels.

Each of the plurality of first pixel groups PG1 may include a red light emitting element R, a first green light emitting element G1, a blue light emitting element B, and a second green light emitting element G2. Here, a virtual line connecting the centers of each of the first and second green light emitting elements G1 and G2 in each of the first pixel groups PG1 may be parallel to the first direction.

Fig. 5 is a view illustrating a pixel and a light transmission region of a second display region according to one embodiment of the present disclosure.

Referring to fig. 5, the second display area CA may include a plurality of second pixel groups PG2 and a plurality of light transmission areas TA. The plurality of light transmission regions TA may be disposed between the plurality of second pixel groups PG 2. Specifically, the light transmission regions TA and the second pixel groups PG2 may be alternately disposed in the first direction and the second direction. The external light may be received to the lens of the camera module through the light transmission region TA. The resolution of the second display area CA may decrease the degree to which the area of the light transmission area TA is increased with respect to the resolution of the first display area DA.

The light transmission region TA may include a transparent medium having high light transmittance without metal so that light can be incident with minimum light loss. The light transmission region TA may be made of a transparent insulating material excluding metal lines or pixels. As the light transmission area TA becomes larger, the light transmittance of the second display area CA may be higher.

Each of the plurality of second pixel groups PG2 may include one or two pixels. For example, in each second pixel group PG2, the first unit pixel PIX1 may include R and G1 sub-pixels SP1, SP2, and the second unit pixel PIX2 may include B and G2 sub-pixels SP3, SP4. The shape and arrangement of the pixels of the second pixel group PG2 may be the same as or different from those of the pixels of the first pixel group PG1.

The shape of the light transmission area TA is illustrated as being a quadrangular shape, but the present disclosure is not limited thereto. For example, the light transmission region TA may be designed in various shapes such as a circular shape, an elliptical shape, a polygonal shape, and the like.

All of the metal electrode material may be removed from the light transmission region TA. Therefore, each line TS of the pixels may be disposed outside the light transmission area TA. Therefore, light can be efficiently incident through the light-transmitting region. However, the present disclosure is not necessarily limited thereto, and a metal electrode material may be present in a partial region of the light transmission region TA.

Fig. 6 is a schematic diagram illustrating a structure of a display panel of the second display region, and fig. 7 is a modification of fig. 6.

Referring to fig. 6, the display panel may include a circuit layer 12 disposed on a substrate 10, and a light emitting element layer 14 disposed on the circuit layer 12. A polarizing plate 18 may be disposed on the light emitting element layer 14, and a cover glass 20 may be disposed on the polarizing plate 18.

In the polarizing plate 18, a first light-transmitting pattern 18d may be formed in a region corresponding to the light-transmitting region TA. The light transmittance of the substrate made of PI is about 70% to 80% based on green light having a wavelength of 555nm, and the light transmittance of the cathode electrode is 80% to 90%. On the other hand, the light transmittance of the polarizing plate 18 is relatively very low, about 40%. Thus, in order to effectively increase the light transmittance in the light transmission region, the light transmittance of the polarizing plate 18 needs to be increased.

The polarizing plate 18 according to this embodiment has the first light transmission pattern 18d formed on the light transmission region TA to increase light transmittance. The light transmittance of the region in the polarizing plate in which the first light-transmitting pattern is formed may be highest. Thus, the amount of light entering the camera module in the light-transmitting area increases, thereby improving camera performance.

The first light-transmitting pattern 18d of the polarizing plate 18 may be formed by removing a portion of the polarizing plate 18, or may be formed by decomposing a compound constituting the polarizing plate 18. That is, the first light transmission pattern 18d may have various structures capable of increasing the light transmittance of the conventional polarizing plate 18.

Referring to fig. 7, in the light transmission region TA, the polarizing plate 18 may have first light transmission patterns 18d, and the cathode CAT may have second light transmission patterns. The second light-transmitting pattern may be an opening H1 formed in the light-transmitting area TA. Since the light transmittance of the cathode is 80% to 90%, the light transmittance of the light transmission region TA may be further increased due to the opening H1.

The method of forming the opening H1 in the cathode CAT is not particularly limited. As an example, after the cathode is formed, an opening H1 may be formed in the cathode using an etching process, or the cathode may be removed using an Infrared (IR) laser at a lower portion of the substrate 10.

A polarizing layer PCL may be formed on the cathode CAT, and a touch sensor TOE may be disposed on the polarizing layer PCL. Here, in the light transmission area TA, the sensing electrode and the line of the touch sensor may be made of a transparent material such as Indium Tin Oxide (ITO) or a metal mesh, thereby increasing light transmittance.

Fig. 8 is a view illustrating a pixel arrangement in a second display region according to a first embodiment of the present disclosure, and fig. 9 is a partially enlarged view of fig. 8.

Referring to fig. 8 and 9, the second display area CA may include a plurality of second pixel groups PG2 and a plurality of light transmission areas TA. The plurality of second pixel groups PG2 may be disposed in the plurality of pixel rows RW1 to RW8 and the plurality of pixel columns in the first and second directions. Hereinafter, the first direction may be an X-axis direction, and the second direction may be a Y1-axis or a Y2-axis direction. Here, the pixel row and the pixel column may refer to a row and a column in which a plurality of sub-pixels are disposed, and the light transmission region may be disposed in a partial region or a whole region of the row and the column.

Each of the second pixel groups PG2 may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. The first sub-pixel SP1 may include a first light emitting element R, the second sub-pixel SP2 may include a second light emitting element G1, and the third sub-pixel SP3 may include a third light emitting element B.

The first light emitting element R may be a red light emitting element, the second light emitting element G1 may be a green light emitting element, and the third light emitting element B may be a blue light emitting element, but the present disclosure is not necessarily limited thereto, and the emission wavelength may be variously modified.

According to the embodiment, the first to third sub-pixels SP1 to SP3 may be implemented as real type pixels constituting one pixel, but the present disclosure is not necessarily limited thereto. As an example, the second pixel group PG2 may further include a fourth sub-pixel, and the fourth sub-pixel may include a green light emitting element or a white light emitting element. Each light emitting element may be an organic or inorganic light emitting element.

The plurality of sub-pixels SP1, SP2, and SP3 may have a regular arrangement in the first direction or the second direction. The first, second, and third sub-pixels SP1, SP2, and SP3 may be sequentially disposed in the first direction.

The width of the light transmission region TA may correspond to the width of each sub-pixel. According to this structure, a large number of light transmission regions TA can be provided in a relatively small structure, so that uniform light transmission regions can be ensured. However, the present disclosure is not necessarily limited thereto, and the size of the light-transmitting area may be variously adjusted. Further, although the light-transmitting area is illustrated as having a quadrangular shape, a circular or polygonal shape may also be applied.

The first and third light emitting elements R and B may be alternately arranged in the first and second directions. The second light emitting element G1 may not overlap the first and third light emitting elements R and B in the first and second directions.

The second light emitting elements G1 and the third light emitting elements B may be alternately arranged in the first diagonal direction D1, and the second light emitting elements G1 and the first light emitting elements R may be alternately arranged in the second diagonal direction D2. The first diagonal direction D1 may be a diagonal direction between the Y1 axis and the X axis, and the second diagonal direction D2 may be a diagonal direction between the Y2 axis and the X axis.

The first light emitting elements R of the plurality of second pixel groups PG2 may be disposed on the first square line P1 inclined at 45 °. In addition, the second light emitting element G1 may be disposed on the second square line P2, and the third light emitting element B may be disposed on the third square line P3. That is, each light emitting element may be provided in a structure in which light emitting elements of the same color are provided in a quadrangular shape.

According to this embodiment, since the center of each light emitting element (or the center of each sub-pixel) is disposed on a square line, the distance between the respective light emitting elements becomes uniform, so that there is an advantage that a relatively uniform image quality can be achieved even when some pixels are omitted. Further, the pixel pattern is not observed from the outside, so that the image quality can be improved.

Referring to fig. 9, circuit portions CT1, CT2, and CT3 may be provided in the sub-pixels SP1, SP2, and SP3, respectively. The circuit sections CT1, CT2, and CT3 may each include a pixel circuit connected to the line TS to drive the pixels.

The line TS may be disposed to bypass the light transmission area TA. Here, the term "bypassing" may mean that the line TS is disposed to cover the light transmission area TA as little as possible. That is, the lines may be disposed in the partially light-transmitting regions. In addition, a portion of the cathode corresponding to the light transmission region TA may be patterned to increase light transmittance.

Fig. 10 is a view illustrating a pixel arrangement in a second display region according to a second embodiment of the present disclosure. Fig. 11a is a partial enlarged view of fig. 10. Fig. 11b is a modification of fig. 11 a.

Referring to fig. 10 and 11a, the second display area CA may include a plurality of second pixel groups PG2 and a plurality of light transmission areas TA. Each of the second pixel groups PG2 may include a 2-1 pixel group PG21 and a 2-2 pixel group PG22 having different subpixel arrangements. Each of the second pixel groups PG2 may include a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3, and a fourth sub-pixel SP4.

The first sub-pixel SP1 may include a first light emitting element R, the second sub-pixel SP2 may include a second light emitting element G1, the third sub-pixel SP3 may include a third light emitting element B, and the fourth sub-pixel SP4 may include a fourth light emitting element G2.

The first light emitting element R may be a red light emitting element, the second light emitting element G1 and the fourth light emitting element G2 may be a green light emitting element, and the third light emitting element B may be a blue light emitting element, but the present disclosure is not necessarily limited thereto, and the light emitting wavelength of each light emitting element may be variously modified.

The fourth sub-pixel SP4 may be disposed in a different pixel row from the first to third sub-pixels SP1 to SP3. As an example, in the 2-1 th pixel group PG21, the first to third sub-pixels SP1 to SP3 may be disposed in the first pixel row RW1, and the fourth sub-pixel SP4 may be disposed in the second pixel row RW 2. The second light emitting element G1 of the second sub-pixel SP2 and the fourth light emitting element G2 of the fourth sub-pixel SP4 may be disposed in the second diagonal direction D2.

However, the present disclosure is not necessarily limited thereto, and the circuit portion of the fourth sub-pixel SP4 may be formed in the first pixel row RW1 and a portion of the fourth light emitting element G2 may be disposed in the second pixel row RW 2. That is, the meaning of the expression "one sub-pixel is provided in a pixel row different from the other sub-pixels" may include a case where both the circuit section and the light emitting element are provided in different pixel rows, and a case where at least a part of the circuit section and the light emitting element are provided in different pixel rows.

In contrast, in the 2 nd-2 nd pixel group PG22, the first, third, and fourth sub-pixels SP1, SP3, and SP4 may be disposed in the second pixel row RW2, and the second sub-pixel SP2 may be disposed in the first pixel row RW 1. That is, the adjacent 2 nd-1 st pixel group PG21 and 2 nd-2 nd pixel group PG22 may have different pixel arrangements. According to this configuration, the second sub-pixel SP2 of the 2 nd-2 nd pixel group PG22 may be disposed in the light transmission region TA between the 2 nd-1 th pixel groups PG21 adjacent in the first direction, thereby improving uniformity and luminance.

The first and third light emitting elements R and B may be alternately arranged in the first direction. The second light emitting element G1 may not overlap with the first and third light emitting elements R and B in the first direction. In addition, the first, second, and third light emitting elements R, G1, and B may be disposed not to overlap each other in the second direction.

The second light emitting elements G1 or the fourth light emitting elements G2 and the third light emitting elements B may be alternately disposed in the first diagonal direction D1, and the first light emitting elements R may not overlap the second light emitting elements G1, the fourth light emitting elements G2 and the third light emitting elements B in the first diagonal direction D1.

The first and second light emitting elements R and G1 and the fourth light emitting element G2 may be alternately disposed in the second diagonal direction D2, and the third light emitting element B may not overlap the first, second and fourth light emitting elements R, G1 and G2 in the second diagonal direction D2.

According to this arrangement, since the second and fourth sub-pixels SP2 and SP4 can be uniformly disposed in the diagonal direction, there is an advantage in that uniform image quality can be achieved even when some pixels are omitted, as compared with the first display area DA. Further, the pixel pattern is not observed from the outside, so that the image quality can be improved.

Although the case where the plurality of light transmission regions TA of various sizes may be formed is exemplified, the size of each light transmission region TA may be the same. As an example, each light transmission region TA may have a size corresponding to that of a sub-pixel.

Referring to fig. 11b, the light transmission region TA may be disposed between the third and fourth sub-pixels SP3 and SP4 constituting the second pixel group PG 2. In the case where the light transmission regions TA between the second pixel groups PG2 are large, there is a problem in that the luminance of the corresponding light transmission regions TA is relatively lowered so that the image quality is deteriorated, but according to this embodiment, the fourth sub-pixel SP4 may be disposed between the light transmission regions TA so that the uniformity and the luminance may be improved.

As an example, the light transmission area TA may be disposed between the third and fourth sub-pixels SP3 and SP4 in the 2-1 th pixel group PG21, and between the second and third sub-pixels SP2 and SP3 in the 2-2 th pixel group PG22. Further, the size of the light transmission region TA provided in the 2 nd-1 st pixel group PG21 and the size of the light transmission region TA provided in the 2 nd-2 nd pixel group PG22 may be different.

According to an embodiment, a method of grouping a plurality of sub-pixels to form a pixel group may be variously modified. Fig. 12 is a view illustrating a pixel arrangement in a second display region according to a third embodiment of the present disclosure.

Referring to fig. 12, the first and third sub-pixels SP1 and SP3 may be disposed in the first pixel row RW1, and the second and fourth sub-pixels SP2 and SP4 may be disposed in the second pixel row RW 2.

Therefore, the first and third light emitting elements R and B may be alternately disposed in the first pixel row RW1, and the second and fourth light emitting elements G1 and G2 may be alternately disposed in the second pixel row RW 2.

However, the present disclosure is not necessarily limited thereto, and the circuit part of each of the second and fourth sub-pixels SP2 and SP4 may be formed in the first pixel row RW1, and a portion of each of the second and fourth light emitting elements G1 and G2 may be disposed in the second pixel row RW 2.

In addition, the second light emitting element G1 of the second sub-pixel SP2 and the fourth light emitting element G2 of the fourth sub-pixel SP4 may have different shapes. As an example, the second light emitting element G1 may have a shape extending in the second diagonal direction D2, and the fourth light emitting element G2 may have a shape extending in the first diagonal direction D1.

The second light emitting elements G1 in the second pixel row RW2 and the second light emitting elements G1 in the fourth pixel row RW4 may also be manufactured to have different shapes. That is, the second light emitting element G1 may be manufactured to have a different shape in the second direction. Similarly, the fourth light emitting elements G2 of the second pixel row RW2 and the fourth light emitting elements G2 of the fourth pixel row RW4 may be manufactured to have different shapes in the second direction.

Since the light emitting element is variously modified in this manner, when the organic light emitting element is formed on the substrate, a Fine Metal Mask (FMM) for the first display region and a FMM for the second display region CA may be differently manufactured.

As an example, in the FMM for the first display region, openings having the same shape may be formed in the second and fourth light emitting elements G1 and G2, and in the FMM for the second display region, openings may be formed by changing the shape and arrangement of the light emitting elements to facilitate improvement of image quality. Thus, the shape and/or arrangement of the pixels in the first display area DA may be different from the shape and/or arrangement of the pixels in the second display area CA.

According to this embodiment, uniformity and luminance may be improved by differently forming the shapes and/or arrangements of the light emitting elements of the first display area DA and the light emitting elements of the second display area CA. According to an embodiment, the method of grouping a plurality of sub-pixels to form a pixel group may be variously modified.

Fig. 13 is a first comparative example illustrating the pixel arrangement in the second display region. Fig. 14 illustrates an observation result of whether a pattern is recognized from the outside. Fig. 15 is a second comparative example illustrating the arrangement of pixels in the second display region.

Referring to fig. 13, red and blue light emitting elements may be disposed in each of the first and fourth pixel rows RW1 and RW4, and a green light emitting element may be disposed in the second pixel row RW 2. In this case, a green light emitting element may also be provided in the third pixel row RW 3.

Therefore, since only the green light emitting elements are provided in the second pixel row RW2 and the third pixel row RW3, there is a problem in that luminance uniformity is relatively lowered. As a result, as shown in fig. 14, the line pattern Q1 is observed from the outside, and thus there is a problem that image quality deteriorates.

Referring to fig. 15, only green light emitting elements are provided in the second pixel row RW2 and the third pixel row RW3, and thus there is a problem in that a line pattern is recognized from the outside. In contrast, in the case of the embodiments of the present disclosure, since the sub-pixels are relatively uniformly arranged, there is an effect of improving image quality.

Fig. 16 is a view illustrating a pixel arrangement in the second display region according to the fourth embodiment of the present disclosure. Fig. 17 is a view illustrating a pixel arrangement in the second display region according to the fifth embodiment of the present disclosure.

Referring to fig. 16, in the second pixel group PG2, the first and second sub-pixels SP1 and SP2 may be disposed in the first pixel row RW1, and the third and fourth sub-pixels SP3 and SP4 may be disposed in the second pixel row RW 2.

In addition, the second and third sub-pixels SP2 and SP3 may be disposed in the second diagonal direction D2, and the first and third sub-pixels SP1 and SP3 may be disposed in the first diagonal direction D1. The light transmission region TA may be disposed between the plurality of second pixel groups PG 2. The light transmission region TA may also be formed to correspond to the size of the second pixel group PG 2.

Referring to fig. 17, in the second pixel group PG2, the first and second sub-pixels SP1 and SP2 may be disposed in the first pixel row RW1, and the third and fourth sub-pixels SP3 and SP4 may be disposed in the second pixel row RW 2.

In addition, the first and fourth sub-pixels SP1 and SP4 may be disposed in the second diagonal direction D2, and the second and third sub-pixels SP2 and SP3 may be disposed in the first diagonal direction D1. The light transmission region TA may be disposed between the plurality of second pixel groups PG 2. The light transmission region TA may also be formed to correspond to the size of the second pixel group PG 2.

Fig. 18 is a view illustrating a pixel arrangement in the second display region according to the sixth embodiment of the present disclosure. Fig. 19 is a view illustrating a pixel arrangement in a second display region according to a seventh embodiment of the present disclosure.

Referring to fig. 18, in the second pixel group PG2, the first to fourth sub-pixels SP1, SP2, SP3, and SP4 may be disposed in the same pixel row. The second pixel group PG2 and the light transmission region TA may be alternately disposed in the first direction and the second direction. Here, the size of the light transmission region TA may correspond to the size of the second pixel group PG 2.

Referring to fig. 19, the second pixel group PG2 includes first to fourth sub-pixels SP1, SP2, SP3, and SP4, and the second pixel group PG2 and the light transmission regions TA may be alternately disposed in the first direction. In the second direction, the 2 nd-1 st pixel group PG21 and the 2 nd-2 nd pixel group PG22 may be alternately disposed. In the 2-1 pixel group PG21 and the 2-2 pixel group PG22, the positions of the first subpixel SP1 and the third subpixel SP3 may be different from each other.

Fig. 20 is a view illustrating a pixel arrangement in a second display region according to an eighth embodiment of the present disclosure, fig. 21 is an enlarged view of fig. 20, fig. 22 is a modification of fig. 21, and fig. 23 is a second modification of fig. 21.

Referring to fig. 20, in the second pixel group PG2, the first, second, and third sub-pixels SP1, SP2, and SP3 may be disposed in the first direction, and the fourth sub-pixel SP4 may be disposed in the second diagonal direction D2 of the third sub-pixel SP3.

The light transmission region TA may be disposed between the plurality of second pixel groups PG 2. In this case, the light transmission region TA may include a region corresponding to the width of each sub-pixel and a region corresponding to the width of three sub-pixels. That is, the sizes of the plurality of light transmission regions TA may be different from each other. However, the present disclosure is not necessarily limited thereto, and the sizes of the plurality of light transmission areas TA may be the same.

The first to third sub-pixels SP1, SP2 and SP3 may be alternately disposed in the first direction. The fourth subpixel SP4 may not overlap the first to third subpixels SP1, SP2, and SP3 in the first direction. The first to fourth sub-pixels SP1, SP2, SP3 and SP4 may be disposed not to overlap each other in the second direction.

The first to fourth sub-pixels SP1, SP2, SP3 and SP4 of the plurality of second pixel groups PG2 may be disposed on each of the square lines P1, P2, P3 and P4. In addition, the first to third sub-pixels SP1, SP2 and SP3 may be disposed inside the square line P4 connecting the fourth sub-pixel SP4. According to this arrangement, since all the sub-pixels are uniformly disposed, even when some pixels are omitted as compared with the first display area DA, uniform image quality can be achieved. Further, the pixel pattern is not observed from the outside, so that the image quality can be improved.

In this embodiment, it is described that the fourth subpixel SP4 is disposed in a different pixel row from the first to third subpixels SP1 to SP3, but the present disclosure is not necessarily limited thereto. The circuit part of the fourth sub-pixel SP4 may be formed in the first pixel row RW1, and a portion of the fourth light emitting element may be disposed in the second pixel row RW 2.

Referring to fig. 21, the second display area CA may include odd pixel rows RW3 and RW5 in which the plurality of second pixel groups PG2 are continuously disposed in the first direction, and even pixel rows RW2 and RW4 in which the plurality of light-transmitting areas TA are continuously disposed in the first direction, and the odd pixel rows RW3 and RW5 and the even pixel rows RW2 and RW4 may be alternately disposed in the second direction.

The circuit sections CT1, CT2, CT3, and CT4 of the sub-pixels SP1, SP2, SP3, and SP4 disposed in each of the odd-numbered pixel rows RW3 and RW5 may be continuously disposed in the first direction. Thus, since the light transmission region TA is not disposed between the sub-pixels, there is an advantage in that the line design is simplified. When multiple light-transmissive regions are provided between the sub-pixels, the line design becomes complicated because the lines have to bypass the light-transmissive regions.

The circuit portion CT4 of the fourth subpixel SP4 may be continuously disposed along the first direction together with the circuit portions CT1, CT2, and CT3 of the first to third light emitting elements. That is, the circuit portion of each sub-pixel may be continuously formed in the third pixel row RW 3. Thus, the light-transmitting areas TA provided in the fourth pixel row RW4 may be continuously provided.

The light transmission area TA disposed in the third pixel row RW3 may be divided into a plurality of areas by the data lines DL. However, the present disclosure is not necessarily limited thereto, and the size of the light transmission area TA may vary according to design variation of the data line.

A first virtual line FL1 connecting the center of each of the second and fourth light emitting elements G1 and G2 in the second pixel group PG2 may cross the first and second directions. That is, the second light emitting element G1 and the fourth light emitting element G2 may be disposed in the second diagonal direction D2 with the third light emitting element B interposed therebetween.

The second light emitting element G1 may be disposed at one side (upper side) of a second virtual line FL2 passing through the center of each of the first and third light emitting elements R and B, and the fourth light emitting element G2 may be disposed at the other side (lower side) of the second virtual line FL 2. However, the present disclosure is not necessarily limited thereto, and the second light emitting element G1 may be disposed at a lower side of the second virtual line FL2 and the fourth light emitting element G2 may be disposed at an upper side of the second virtual line FL 2.

According to this embodiment, the first virtual line FL1 may cross the second virtual line FL 2. Therefore, a portion of the fourth light emitting element G2 may be disposed to overlap the light transmission region TA. Here, the anode disposed under the fourth light emitting element G2 may also extend onto the light transmission region TA. According to this configuration, luminance and uniformity can be improved by partially disposing the fourth light emitting element G2 in the light transmission region TA.

A portion of the fourth light emitting element G2 is illustrated as being disposed outside the light transmission region TA, but the present disclosure is not necessarily limited thereto. As an example, the fourth light emitting element G2 may be disposed at the center of the light transmission region TA. In this case, the anode may extend to connect the circuit portion CT4 and the fourth light emitting element G2. The anode may be formed as a transparent electrode, but the present disclosure is not necessarily limited thereto.

According to this embodiment, since the fourth light emitting elements G2 are disposed in the light transmission region TA, the first distance W1 between the fourth light emitting elements G2 disposed in the third pixel row RW3 and the second light emitting elements G1 disposed in the fifth pixel row RW5 may be relatively small. The first distance W1 may be substantially similar to a second distance W2 between the second light emitting element G1 and the fourth light emitting element G2 in the same second pixel group PG 2.

Thus, even when a plurality of light transmission regions TA are continuously provided in the third pixel row RW3, the distance between the second light emitting elements G1 and the fourth light emitting elements G2 may be regularly arranged in the second display region CA, so that the luminance may be uniform. In addition, image quality can be improved.

The line TS connected to each sub-pixel may be configured to avoid the light transmission region TA. As an example, the lines TS such as the data lines, the scan lines, and the EM lines connected to each sub-pixel may be designed to bypass the light transmission area TA as much as possible. As an example, the line TS extending from the fourth pixel row RW4 of the first display area DA may be designed to detour to the fifth pixel row RW5 in the second display area CA.

A portion of the cathode corresponding to the light transmission region TA may be patterned to increase light transmittance. In addition, as described above, the first light-transmitting pattern corresponding to the light-transmitting region may also be formed on the polarizing plate to increase light transmittance.

Referring to fig. 22, the second light emitting element G1 may be disposed in the light transmission region TA instead of the fourth light emitting element G2. Alternatively, the second light emitting element G1 may be disposed adjacent to the light transmission region TA disposed at a lower side thereof, and the fourth light emitting element G2 may be disposed adjacent to the light transmission region TA disposed at an upper side thereof. In this case, the light emitting element may be disposed in the light transmission region TA, thereby improving image quality.

Referring to fig. 23, the fourth light emitting element G2 may be used as a dummy pixel for emitting light by being connected to the circuit section CT1 of the second light emitting element G1 without being controlled by the circuit section alone. In this case, a connection line XL1 connected between the fourth light emitting element G2 and the second light emitting element G1 may be further formed. The connection line XL1 may be manufactured as a transparent electrode, such as ITO, but the present disclosure is not necessarily limited thereto.

Fig. 24a is a view illustrating a pixel arrangement in a second display region according to a ninth embodiment of the present disclosure.

Referring to fig. 24a, a plurality of second pixel groups PG2 may be disposed to be spaced apart from each other in the first direction. In fig. 24a, the light transmission region TA is further provided between the plurality of second pixel groups PG2, compared to the second pixel groups PG2 continuously disposed in the first direction of fig. 20, and thus the number of pixels can be reduced by 1/2 compared to the second display region of fig. 20. Therefore, light can be sufficiently incident on the increased light transmission area TA.

Each of the subpixels disposed in the plurality of second pixel groups PG2 may be disposed on a square line inclined at 45 °. As an example, a plurality of first sub-pixels SP1 may be disposed on the first square line P1, a plurality of second sub-pixels SP2 may be disposed on the second square line P2, and a plurality of third sub-pixels SP3 may be disposed on the third square line P3.

Fig. 24b is a view illustrating a structure in which the area of the light transmitting region is changed in the second display region.

Referring to fig. 24b, the second display area CA may include: a first unit area CA2 having a smaller number of pixels than the first display area DA; and a second unit area CA1 having a smaller number of pixels than the first unit area CA 2. That is, the resolution may be different even in the second display area CA.

A plurality of electronic devices may be disposed under the second display area CA. As an example, the plurality of electronic devices may include an Ambient light sensor (Ambient light sensor) that determines Ambient brightness, a Proximity sensor (Proximity sensor), a camera module having an image sensor built therein, and an infrared sensor that receives infrared light. The camera module 42a includes an infrared filter to block light in an infrared band and receive visible light, and the infrared sensor 42b may receive light in the infrared band.

Here, the infrared sensor 42b can perform relatively accurate measurement even when the amount of light is small, as compared with the camera module 42 a. Thus, the number of pixels of the second unit area CA1 where the camera module 42a is disposed may be less than the number of pixels of the first unit area CA2 where the infrared sensor 42b is disposed.

As an example, the pixel pattern PA1 of the second unit area CA1 may have the pixel pattern shown in fig. 24a, and the pixel pattern PA2 of the first unit area CA2 may have the pixel pattern shown in fig. 20. As an example, the first unit area CA2 may be designed to have a light transmittance of 10% to 30%. Thus, the amount of incident light in the second unit area CA1 may be relatively large. However, such a pixel pattern is not necessarily limited thereto, and the pixel pattern described in the present application may be applied without limitation.

Fig. 25 is a view illustrating a pixel arrangement in a second display region according to a tenth embodiment of the present disclosure, fig. 26 is an enlarged view of fig. 25, and fig. 27 is a view illustrating a pixel arrangement in a second display region according to an eleventh embodiment of the present disclosure.

Referring to fig. 25, a plurality of second pixel groups PG2 may be disposed in the first pixel row RW1, and a plurality of light transmission areas TA may be disposed in the second pixel row RW 2. In this case, the number of pixels is reduced by 1/2 compared to the first display area DA so that a sufficient amount of light can be injected into the sensor.

The first to fourth sub-pixels SP1, SP2, SP3 and SP4 of the plurality of second pixel groups PG2 may be disposed on each of the square lines P1, P2, P3 and P4. According to this arrangement, since all the sub-pixels are uniformly disposed, even when some pixels are omitted as compared with the first display area DA, uniform image quality can be achieved. Further, the pixel pattern is not observed from the outside, so that the image quality can be improved.

Referring to fig. 26, a third virtual line FL3 connecting the second and fourth light emitting elements G1 and G2 may be parallel to the first direction. The pixel arrangement is the same as the pixel step of the first display region.

The line TS connected to each sub-pixel may be configured to avoid the light transmission area TA. As an example, the data line, the scan line, and the EM line connected to each sub-pixel may be designed to bypass the light transmission area TA as much as possible. In addition, a portion of the cathode corresponding to the light transmission region TA may be patterned to increase light transmittance.

Referring to fig. 27, a plurality of second pixel groups PG2 may be disposed to be spaced apart from each other in the first direction. The light transmission region TA is disposed between the plurality of second pixel groups PG2 of fig. 27, compared with the second pixel groups PG2 of fig. 25 which are continuously disposed in the first direction, and thus the number of pixels can be further reduced. Therefore, light can be sufficiently incident on the increased light transmission area TA.

Each of the sub-pixels SP1, SP2, SP3, and SP4 disposed in the plurality of second pixel groups PG2 may be disposed on a square line inclined at 45 °. As an example, a plurality of first sub-pixels SP1 may be disposed on the first square line P1, a plurality of second sub-pixels SP2 may be disposed on the second square line P2, a plurality of third sub-pixels SP3 may be disposed on the third square line P3, and a plurality of fourth sub-pixels SP4 may be disposed on the fourth square line P4.

Fig. 28 is a view illustrating a pixel arrangement in the second display region according to the twelfth embodiment of the present disclosure.

Fig. 28 illustrates a structure in which the fourth subpixel SP4 is omitted from the second pixel group PG2 of fig. 20. Accordingly, the first to third sub-pixels SP1 to SP3 may be implemented as real type pixels constituting one pixel, but the present disclosure is not necessarily limited thereto.

Fig. 29 is a view illustrating a pixel arrangement in a second display region according to a thirteenth embodiment of the present disclosure, and fig. 30 is a view illustrating a pixel arrangement in a second display region according to a fourteenth embodiment of the present disclosure.

Referring to fig. 29, a plurality of sub-pixels constituting the second pixel group PG2 may be disposed in two pixel rows RW1 and RW 2. As an example, the second and third sub-pixels SP2 and SP3 may be disposed in the first pixel row RW1, and the first and fourth sub-pixels SP1 and SP4 may be disposed in the second pixel row RW 2.

The light transmission area TA may be disposed between the second and third sub-pixels SP2 and SP3 in the first pixel row RW1 and between the first and fourth sub-pixels SP1 and SP4 in the second pixel row RW 2.

The plurality of second pixel groups PG2 may be disposed to be spaced apart from each other in the first direction, but may be disposed continuously in the second direction. However, the present disclosure is not necessarily limited thereto, and the plurality of second pixel groups PG2 may also be disposed to be spaced apart from each other in the second direction.

Referring to fig. 30, the plurality of second pixel groups PG2 may include a 2-1 pixel group PG21 and a 2-2 pixel group PG22 having different pixel arrangements.

As an example, in the 2-1 th pixel group PG21, the first and second sub-pixels SP1 and SP2 may be disposed in the second pixel row RW2, and the third and fourth sub-pixels SP3 and SP4 may be disposed in the third pixel row RW 3.

However, in the 2 nd-2 nd pixel group PG22, the second and third sub-pixels SP2 and SP3 may be disposed in the fourth pixel row RW4, and the first and fourth sub-pixels SP1 and SP4 may be disposed in the fifth pixel row RW5.

That is, the position of the green sub-pixel may be the same between the adjacent second pixel groups PG2, but the arrangement of the red and blue sub-pixels may be different. In this case, the same color sub-pixels may be disposed in the second diagonal direction D2. That is, the plurality of first sub-pixels SP1 may be disposed in the second diagonal direction D2, the plurality of second sub-pixels SP2 may be disposed in the second diagonal direction D2, the plurality of third sub-pixels SP3 may be disposed in the second diagonal direction D2, and the plurality of fourth sub-pixels SP4 may be disposed in the second diagonal direction D2.

Fig. 31 is a view illustrating a pixel arrangement in a second display region according to a fifteenth embodiment of the present disclosure, and fig. 32 is a view illustrating a pixel arrangement in a second display region according to a sixteenth embodiment of the present disclosure.

Referring to fig. 31, the positions of the red and blue sub-pixels are set opposite to those of fig. 30. Thus, the plurality of first sub-pixels SP1 may be disposed in the first diagonal direction D1, the plurality of second sub-pixels SP2 may be disposed in the first diagonal direction D1, the plurality of third sub-pixels SP3 may be disposed in the first diagonal direction D1, and the plurality of fourth sub-pixels SP4 may be disposed in the first diagonal direction D1. In addition, as shown in fig. 32, a plurality of second pixel groups PG2 may also be spaced apart from each other in the second direction.

Fig. 33 is a view illustrating an arrangement of pixels in a second display region according to a seventeenth embodiment of the present disclosure.

Referring to fig. 33, a plurality of subpixels constituting the second pixel group PG2 may be disposed in two pixel rows. As an example, the first and second sub-pixels SP1 and SP2 may be disposed in the first pixel row RW1, and the third and fourth sub-pixels SP3 and SP4 may be disposed in the second pixel row RW 2.

The first and second sub-pixels SP1 and SP2 may constitute the first unit pixel PIX1, and the third and fourth sub-pixels SP3 and SP4 may constitute the second unit pixel PIX2. Here, the first unit pixel PIX1 and the second unit pixel PIX2 may be disposed to be offset from each other so as not to overlap in the second direction.

Fig. 34 is a block diagram illustrating a display panel and a display panel driving unit according to an embodiment of the present disclosure, and fig. 35 is a schematic block diagram illustrating a configuration of a driver Integrated Circuit (IC).

Referring to fig. 34 and 35, the display device may include: a display panel 100 having a pixel array disposed on a screen, a display panel driving unit, and the like.

The pixel array of the display panel 100 may include data lines DL, gate lines GL crossing the data lines DL, and pixels P arranged in a matrix form defined by the data lines DL and the gate lines GL.

In the display panel 100, a screen reproducing an input image may include a first display area DA and a second display area CA.

The sub-pixels of each of the first and second display regions DA and CA may include pixel circuits. The pixel circuit may include: a driving element configured to supply a current to the light emitting element OLED, a plurality of switching elements configured to sample a threshold voltage of the driving element and switch a current path (current path) of the pixel circuit, a capacitor configured to hold a gate voltage of the driving element, and the like. The pixel circuit may be disposed under the light emitting element.

The second display area CA may include a light transmission area TA disposed between the pixel groups and a camera module 400 disposed under the second display area CA. In the imaging mode, the camera module 400 may photoelectrically convert light incident through the second display area CA using an image sensor and convert pixel data of an image output from the image sensor into digital data to output imaged image data.

The display panel driving unit may write pixel data of an input image to the pixels P. The pixel P may be interpreted as a pixel group comprising a plurality of sub-pixels.

The display panel driving unit may include: a data driving unit 306 configured to supply a data voltage of pixel data to the data lines DL, and a gate driving unit 120 configured to sequentially supply a gate pulse to the gate lines GL. The data driving unit 306 may be integrated into the driver IC 300. The display panel driving unit may further include a touch sensor driving unit omitted in the drawing.

The driver IC 300 may be attached to the display panel 100. The driver IC 300 receives pixel data and timing signals of an input image from the host system 200, supplies data voltages of the pixel data to the pixels, and synchronizes the data driving unit 306 with the gate driving unit 120.

The driver IC 300 may be connected to the data lines DL through a data output channel to supply data voltages of pixel data to the data lines DL. The driver IC 300 may output a gate timing signal for controlling the gate driving unit 120 through the gate timing signal output channel.

The Gate timing signal generated from the timing controller 303 may include a Gate start pulse (VST), a Gate shift Clock (CLK), and the like. The gate start pulse VST and the gate shift clock CLK may swing (swing) between the gate-on voltage VGL and the gate-off voltage VGH.

The gate timing signals (VST and CLK) output from the level shifter 307 may be applied to the gate driving unit 120 to control the shift operation of the gate driving unit 120.

The gate driving unit 120 may include a shift register (shift register) formed on a circuit layer of the display panel 100 together with the pixel array. The shift register of the gate driving unit 120 may sequentially supply the gate signals to the gate lines GL under the control of the timing controller. The gate signal may include a scan pulse and an EM pulse of the light emission signal.

The shift register may include: a scan driving unit configured to output a scan pulse, and an EM driving unit configured to output an EM pulse. In fig. 35, "GVST" and "GCLK" are signals included in the gate timing signals input to the scan driving unit. "EVST" and "ECLK" are signals included in the gate timing signals input to the EM driving unit.

The driver IC 300 may be connected to the host system 200, the first memory 301, and the display panel 100. The driver IC 300 may include a data receiving and calculating unit 308, a timing controller 303, a data driving unit 306, a gamma compensation voltage generating unit 305, a power supply unit 304, a second memory 302, and the like.

The data receiving and computing unit 308 may include: a receiving unit configured to receive pixel data input as a digital signal from the host system 200, and a data calculating unit configured to process the pixel data input through the receiving unit to improve image quality.

The data calculation unit may include: a data restoring unit configured to perform restoration by Decoding (Decoding) the compressed pixel data, an optical compensation unit configured to add a preset optical compensation value to the pixel data, and the like. The optical compensation value may be set to a value for correcting each piece of pixel data according to the luminance of the screen measured with reference to a camera image photographed in the manufacturing process.

The timing controller 303 may provide the data driving unit 306 with pixel data of an input image received from the host system 200. The timing controller 303 may generate a gate timing signal for controlling the gate driving unit 120 and a source timing signal for controlling the data driving unit 306 to control operation timings of the gate driving unit 120 and the data driving unit 306.

The data driving unit 306 may convert Digital data including pixel data received from the timing controller 303 into a gamma compensation voltage using a Digital to Analog converter (DAC) and output the data voltage. The data voltage output from the data driving unit 306 may be supplied to the data lines DL of the pixel array through an output buffer connected to the data channel of the driver IC 300.

The gamma compensation voltage generating unit 305 may generate a gamma compensation voltage for each gray scale by dividing a gamma reference voltage received from the power supply unit 304 through a voltage divider circuit. The gamma compensation voltage is an analog voltage in which a voltage is set for each gray scale of pixel data. The gamma compensation voltage output from the gamma compensation voltage generation unit 305 may be provided to the data driving unit 306.

The power supply unit 304 may generate power required to drive the driver IC 300, the gate driving unit 120, and the pixel array of the display panel 100 using a DC-DC Converter (DC-DC Converter). The DC-DC Converter may include a Charge pump (Charge pump), a Regulator (Regulator), a Buck Converter (Buck Converter), a Boost Converter (Boost Converter), and the like.

The power supply unit 304 may generate DC voltages, such as a gamma reference voltage, a gate-on voltage VGL, a gate-off voltage VGH, a pixel driving voltage VDD, a low potential power supply voltage VSS, an initialization voltage Vini, and the like, by adjusting a DC input voltage received from the host system 200.

The gamma reference voltage may be provided to the gamma compensation voltage generating unit 305. The gate-on voltage VGL and the gate-off voltage VGH may be provided to the level shifter 307 and the gate driving unit 120. Pixel power supply voltages such as a pixel driving voltage VDD, a low potential power supply voltage VSS, and an initialization voltage Vini may be commonly supplied to the pixels P.

The initialization voltage Vini may be set to a DC voltage lower than the pixel driving voltage VDD and lower than the threshold voltage of the light emitting element OLED to initialize the main node of the pixel circuit and suppress light emission of the light emitting element OLED.

When power is supplied to the driver IC 300, the second memory 302 may store compensation values, register setting data, and the like received from the first memory 301.

The compensation value may be applied to various algorithms for improving image quality. The compensation value may comprise an optical compensation value. The register setting data may define operations of the data driving unit 306, the timing controller 303, the gamma compensation voltage generating unit 305, and the like. The first memory 301 may include a Flash memory (Flash memory). The second memory 302 may include Static random access memory (Static RAM, SRAM).

The host system 200 may be implemented as an Application Processor (AP). The host system 200 may transfer pixel data of an input image to the driver IC 300 through a Mobile Industry Processor Interface (MIPI). The host system 200 may be connected to the driver IC 300 through, for example, a Flexible Printed Circuit (FPC).

In addition, the display panel may be implemented as a flexible panel applicable to a flexible display. The flexible display may have a screen of a size varying by winding, folding, or bending the flexible panel and may be easily manufactured in various designs.

The flexible display may be implemented as a rollable display (rollable display), a foldable display (foldable display), a bendable display (bendable display), a slidable display (slidable display), and the like.

The flexible panel may be manufactured as a so-called "plastic OLED panel". The plastic OLED panel may include a Back plate (Back plate) and a pixel array formed on an organic thin film attached to the Back plate. A touch sensor array can be formed over the pixel array.

The backsheet may be a Polyethylene terephthalate (PET) substrate. The pixel array and the touch sensor array may be formed on an organic thin film. The back plate may block moisture from penetrating into the organic thin film so that the pixel array is not exposed to moisture.

The organic thin film may be a Polyimide (PI) substrate. A multi-layer buffer film may be formed of an insulating material (not shown) on the organic thin film. The circuit layer 12 and the light emitting element layer 14 may be stacked on the organic thin film.

In the display device of the present disclosure, the pixel circuit and the gate driving unit disposed on the circuit layer 12 may include a plurality of transistors. The Transistor may be implemented as an Oxide Thin Film Transistor (Oxide TFT) including an Oxide semiconductor, an LTPS TFT including Low Temperature Polysilicon (LTPS), or the like. Each transistor may be implemented as a p-channel Thin Film Transistor (TFT) or an n-channel TFT. The following embodiments will be described focusing on an example in which the transistor of the pixel circuit is implemented as a p-channel TFT, but the present disclosure is not limited thereto.

The transistor is a three-electrode element including a gate (gate), a source (source), and a drain (drain). The source is an electrode which supplies carriers (carriers) to the transistor. Carriers in the transistor may flow from the source. The drain is an electrode for carriers to exit from the transistor to the outside.

In a transistor, carriers flow from the source to the drain. In the case of an n-channel transistor, the carriers are electrons (electrons), and thus the source voltage is lower than the drain voltage, so that electrons flow from the source to the drain. In the case of an n-channel transistor, current flows from the drain to the source.

In the case of a p-channel transistor (PMOS), the carriers are holes (holes), and thus the source voltage is higher than the drain voltage, so that holes flow from the source to the drain. In the case of a p-channel transistor, since holes flow from the source to the drain, a current flows from the source to the drain. It should be noted that the positions of the source and drain of the transistor are not fixed. For example, the source and drain may be interchanged depending on the applied voltage. Thus, the present disclosure is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as a first electrode and a second electrode.

The Gate pulse may swing (swing) between a Gate On Voltage (Gate On Voltage) and a Gate Off Voltage (Gate Off Voltage). The gate-on voltage may be set higher than a threshold voltage of the transistor, and the gate-off voltage may be set lower than the threshold voltage of the transistor.

The transistor may be turned on in response to a gate-on voltage and turned off in response to a gate-off voltage. In the case of an n-channel transistor, the Gate-on Voltage may be a Gate High Voltage (VGH), and the Gate-off Voltage may be a Gate Low Voltage (VGL). In the case of a p-channel transistor, the gate-on voltage may be VGL and the gate-off voltage may be VGH.

The driving element of the pixel circuit may be implemented as a transistor. The driving element should have uniform electrical characteristics among all pixels, but there may be a difference in electrical characteristics among pixels due to process variation and element characteristic variation, and the electrical characteristics may vary when display driving time elapses.

In order to compensate for the variation in the electrical characteristics of the driving element, the display device may include an internal compensation circuit and an external compensation circuit. An internal compensation circuit may be added to the pixel circuit in each sub-pixel to sample the threshold voltage Vth and/or mobility μ of the driving element that varies according to the electrical characteristics of the driving element and compensate for the variation in real time.

The external compensation circuit may transmit the threshold voltage and/or mobility of the driving element sensed through the sensing line connected to each sub-pixel to the external compensation unit. The compensation unit of the external compensation circuit may modulate pixel data of the input image reflecting the sensing result, thereby compensating for a variation in electrical characteristics of the driving element.

The voltage of the pixel, which varies according to the electrical characteristic of the external compensation driving element, may be sensed, and the data of the input image is modulated in the external circuit based on the sensed voltage, thereby compensating for the variation of the electrical characteristic of the driving element between the pixels.

Fig. 36 is a circuit diagram illustrating an example of a pixel circuit, and fig. 37 is a circuit diagram illustrating another example of a pixel circuit. Fig. 38 is a view illustrating a method of driving the pixel circuit shown in fig. 36 and 37.

The pixel circuits shown in fig. 36 and 37 can be similarly applied to the pixel circuits of the first display area DA and the second display area CA. A pixel circuit applicable to the present disclosure may be implemented as the circuits shown in fig. 36 and 37, but the present disclosure is not limited thereto.

Referring to fig. 36 to 38, the pixel circuit may include a light emitting element OLED, a driving element DT configured to supply a current to the light emitting element OLED, and an internal compensation circuit configured to sample a threshold voltage Vth of the driving element DT using a plurality of switching elements M1 to M6 and compensate a gate voltage of the driving element DT for the threshold voltage Vth of the driving element DT. Each of the driving element DT and the switching elements M1 to M6 may be implemented as a p-channel TFT.

The driving period of the pixel circuit using the internal compensation circuit may be divided into an initialization period Tini, a sampling period Tsam, a data writing period Twr, and an emission period Tem, as shown in fig. 38.

During the initialization period Tini, the nth-1 SCAN signal SCAN (N-1) is generated as a pulse of the gate-on voltage VGL, and a voltage of each of the nth SCAN signal SCAN (N) and the emission signal EM (N) is the gate-off voltage VGH. During the sampling period Tsam, the nth SCAN signal SCAN (N) is generated as a pulse of the gate-on voltage VGL, and the voltage of each of the N-1 th SCAN signal SCAN (N-1) and the emission signal EM (N) is the gate-off voltage VGH. During the data write period Twr, a voltage of each of the N-1 th SCAN signal SCAN (N-1), the nth SCAN signal SCAN (N), and the emission signal EM (N) is a gate-off voltage VGH. During at least a partial period of the emission period Tem, the emission signal EM (N) may be generated as the gate-on voltage VGL, and each of the N-1 th SCAN signal SCAN (N-1) and the nth SCAN signal SCAN (N) may be generated as the gate-off voltage VGH.

During the initialization period Tini, the fifth switching element M5 may be turned on according to the gate-on voltage VGL of the N-1 th SCAN signal SCAN (N-1) to initialize the pixel circuit. During the sampling period Tsam, the first and second switching elements M1 and M2 may be turned on according to the gate-on voltage VGL of the nth SCAN signal SCAN (N), so that the threshold voltage of the driving element DT may be sampled and stored in the storage capacitor Cst 1. Meanwhile, the sixth switching element M6 may be turned on during the sampling period Tsam to lower the voltage of the fourth node n4 to the reference voltage Vref, thereby suppressing light emission of the light emitting element OLED. During the data write period Twr, the first to sixth switching elements M1 to M6 may be maintained in an off state. During the light emission period Tem, the third and fourth switching elements M3 and M4 may be turned on, so that the light emitting element OLED emits light. In the emission period Tem, in order to precisely represent the luminance of the low gray scale with the duty ratio (duration) of the emission signal EM (N), the emission signal EM (N) may swing between the gate-on voltage VGL and the gate-off voltage VGH at a predetermined duty ratio to repeat the on or off of the third switching element M3 and the fourth switching element M4.

The light emitting element OLED may be implemented as an organic light emitting diode or an inorganic light emitting diode. Hereinafter, an example in which the light emitting element OLED is implemented as an organic light emitting diode will be described.

The light emitting element OLED may include an organic compound layer formed between an anode and a cathode. The organic compound layer may include a hole injection layer HIL, a hole transport layer HTL, an emission layer EML, an electron transport layer ETL, and an electron injection layer EIL, but the disclosure is not limited thereto. When a voltage is applied to the anode and the cathode of the OLED, holes passing through the hole transport layer HTL and electrons passing through the electron transport layer ETL move to the light emitting layer EML to generate excitons, and thus visible light may be emitted from the light emitting layer EML.

The anode of the light emitting element OLED may be connected to the fourth node n4 between the fourth and sixth switching elements M4 and M6. The fourth node n4 is connected to the anode of the light emitting element OLED, the second electrode of the fourth switching element M4, and the second electrode of the sixth switching element M6. The cathode of the light emitting element OLED may be connected to a VSS line PL3 to which a low potential power supply voltage VSS is applied. The light emitting element OLED can emit light using a current Ids flowing according to the gate-source voltage Vgs of the driving element DT. The third and fourth switching elements M3 and M4 may switch a current path of the light emitting element OLED.

The storage capacitor Cst1 may be connected between the VDD line PL1 and a first node n1. The storage capacitor Cst1 may be charged with the data voltage Vdata compensated for the threshold voltage Vth of the driving element DT. Since the data voltage Vdata in each sub-pixel is compensated for the threshold voltage Vth of the driving element DT, the characteristic deviation of the driving element DT in each sub-pixel may be compensated.

The first switching element M1 may be turned on in response to the gate-on voltage VGL of the nth SCAN signal SCAN (N) to connect the second node N2 to the third node N3. The second node n2 may be connected to the gate electrode of the driving element DT, the first electrode of the storage capacitor Cst1, and the first electrode of the first switching element M1. The third node n3 may be connected to the second electrode of the driving element DT, the second electrode of the first switching element M1, and the first electrode of the fourth switching element M4. A gate electrode of the first switching element M1 is connected to the first gate line GL1 to receive the nth SCAN signal SCAN (N). The first electrode of the first switching element M1 may be connected to the second node n2, and the second electrode of the first switching element M1 may be connected to the third node n3.

The first switching element M1 may be turned on in a very short horizontal period 1H in one frame period in which the nth SCAN signal SCAN (N) is generated as the gate-on voltage VGL, and thus may be maintained in an off state in about one frame period, and thus a leakage current may be generated in the off state of the first switching element M1. In order to suppress the leakage current of the first switching element M1, the first switching element M1 may be implemented as a dual-gate structure having two transistors M1a and M1b connected in series, as shown in fig. 37.

The second switching element M2 may be turned on in response to the gate-on voltage VGL of the nth SCAN signal SCAN (N) to supply the data voltage Vdata to the first node N1. A gate electrode of the second switching element M2 may be connected to the first gate line GL1 to receive the nth SCAN signal SCAN (N). A first electrode of the second switching element M2 may be connected to the first node n1. The second electrode of the second switching element M2 may be connected to the data line DL to which the data voltage Vdata is applied. The first node n1 may be connected to a first electrode of the second switching element M2, a second electrode of the third switching element M3, and a first electrode of the driving element DT.

The third switching element M3 may be turned on in response to the gate-on voltage VGL of the emission signal EM (N) to connect the VDD line PL1 to the first node N1. A gate electrode of the third switching element M3 may be connected to the third gate line GL3 to receive the emission signal EM (N). A first electrode of the third switching element M3 may be connected to the VDD line PL1. A second electrode of the third switching element M3 may be connected to the first node n1.

The fourth switching element M4 may be turned on in response to the gate-on voltage VGL of the light emission signal EM (N) to connect the third node N3 to the anode of the light emitting element OLED. A gate electrode of the fourth switching element M4 may be connected to the third gate line GL3 to receive the light emitting signal EM (N). A first electrode of the fourth switching element M4 may be connected to the third node n3, and a second electrode of the fourth switching element M4 may be connected to the fourth node n4.

The fifth switching element M5 may be turned on in response to the gate-on voltage VGL of the N-1 th SCAN signal SCAN (N-1) to connect the second node N2 to the Vini line PL2. The gate electrode of the fifth switching element M5 may be connected to the second gate line GL2 to receive the N-1 th SCAN signal SCAN (N-1). A first electrode of the fifth switching element M5 may be connected to the second node n2, and a second electrode of the fifth switching element M5 may be connected to the Vini line PL2. In order to suppress the leakage current of the fifth switching element M5, the fifth switching element M5 may be implemented as a double gate (structure, as shown in fig. 37) having two transistors M5a and M5b connected in series.

The sixth switching element M6 may be turned on in response to the gate-on voltage VGL of the nth SCAN signal SCAN (N) to connect the Vini line PL2 to the fourth node N4. A gate electrode of the sixth switching element M6 may be connected to the first gate line GL1 to receive the nth SCAN signal SCAN (N). A first electrode of the sixth switching element M6 may be connected to the Vini line PL2, and a second electrode of the sixth switching element M6 may be connected to the fourth node n4.

The driving element DT may adjust a current Ids flowing into the light emitting element OLED according to the gate-source voltage Vgs to drive the light emitting element OLED. The driving element DT may include a gate electrode connected to the second node n2, a first electrode connected to the first node n1, and a second electrode connected to the third node n3.

As shown in fig. 38, the N-1 th SCAN signal SCAN (N-1) is generated as the gate-on voltage VGL during the initialization period Tini. During the initialization period Tini, the nth SCAN signal SCAN (N) and the emission signal EM (N) may be maintained at the gate-off voltage VGH. Thus, during the initialization period Tini, the fifth switching element M5 may be turned on (turn-on), so that the second node n2 and the fourth node n4 may each be initialized to "Vini". The holding period Th may be set between the initialization period Tini and the sampling period Tsam. During the holding period Th, the gate signals SCAN (N-1), SCAN (N) and EM (N) may be held in their previous states.

The nth SCAN signal SCAN (N) may be generated as the gate-on voltage VGL during the sampling period Tsam. The nth SCAN signal SCAN (N) may be synchronized with the data voltage Vdata of the nth pixel line. The N-1 th SCAN signal SCAN (N-1) and the emission signal EM (N) may each be maintained at the gate-off voltage during the sampling period Tsam. Thus, during the sampling period Tsam, the first and second switching elements M1 and M2 may be turned on.

During the sampling period Tsam, the gate voltage DTG of the driving element DT may rise due to the current flowing through the first and second switching elements M1 and M2. When the driving element DT is turned off, the gate voltage DTG is Vdata | Vth |. In this case, the voltage of the first node n1 is also Vdata- | Vth |. During the sampling period Tsam, the gate-source voltage Vgs of the driving element DT is | Vgs | = Vdata- (Vdata- | Vth |) = | Vth |.

During the data writing period Twr, the nth SCAN signal SCAN (N) may be inverted to the gate-off voltage VGH. During the data writing period Twr, the N-1 th SCAN signal SCAN (N-1) and the emission signal EM (N) may each be maintained at the gate-off voltage VGH. Thus, during the data writing period Twr, all the switching elements M1 to M6 can be kept in the off state.

During the emission period Tem, the emission signal EM (N) may be generated as the gate-on voltage VGL. During the emission period Tem, in order to improve low gray-scale representation, the emission signal EM (N) may be turned on or off at a predetermined duty ratio to swing (swing) between the gate-on voltage VGL and the gate-off voltage VGH. Accordingly, the emission signal EM (N) may be generated as the gate-on voltage VGL during at least a part of the emission period Tem.

When the light emission signal EM (N) is at the gate-on voltage VGL, a current flows between "VDD" and the light emitting element OLED, so that the light emitting element OLED may emit light. During the light emission period Tem, the nth-1 SCAN signal SCAN (N-1) and the nth SCAN signal SCAN (N) may each be maintained at the gate off voltage VGH. During the emission period Tem, the third and fourth switching elements M3 and M4 may be repeatedly turned on and off according to the voltage of the emission signal EM (N). When the light emission signal EM (N) is at the gate-on voltage VGL, the third and fourth switching elements M3 and M4 are turned on, so that a current flows into the light emitting element OLED. In this case, "Vgs" of the driving element DT satisfies | Vgs | = VDD- (Vdata- | Vth |), and the current flowing into the light emitting element OLED is K (VDD-Vdata) 2."K" is a constant determined by the charge mobility, parasitic capacitance, and channel capacity of the driving element DT.

Fig. 39 is a sectional view illustrating in detail a sectional structure of a pixel region in a display panel according to an embodiment of the present disclosure, and fig. 40 illustrates a sectional structure of a pixel region and a light transmitting region according to an embodiment of the present disclosure.

The cross-sectional structure of the display panel 100 is not limited to the structure in fig. 39. In fig. 39, "TFT" represents a driving element DT of the pixel circuit.

Referring to fig. 39, a circuit layer, a light emitting element layer, and the like may be stacked on the substrates PI1 and PI2 in the pixel region PIX. The substrates PI1 and PI2 may include a first PI substrate PI1 and a second PI substrate PI2. The inorganic film IPD may be formed between the first PI substrate PI1 and the second PI substrate PI2. The inorganic film IPD may block the penetration of moisture.

The first buffer layer BUF1 may be formed on the second PI substrate PI2. The first metal layer may be formed on the first buffer layer BUF1, and the second buffer layer BUF2 may be formed on the first metal layer.

The first metal layer may be patterned by a Photolithography (Photolithography) process. The first metal layer may include a light shield pattern (BSM). The light blocking pattern BSM may block external light such that light cannot enter an active layer of the TFT, thereby preventing generation of a photo current of the TFT formed in the pixel region.

When the light blocking pattern BSM is formed of a metal having a low absorption coefficient for a laser wavelength used in the laser ablation process as compared to a metal layer (e.g., cathode electrode) to be removed from the second display area CA, the light blocking pattern BSM may also serve as a light blocking layer LS configured to block the laser beam LB in the laser ablation process.

Each of the first and second buffer layers BUF1 and BUF2 may be made of an inorganic insulating material and may be formed of one or more insulating layers.

The active layer ACT may be made of a semiconductor material deposited on the second buffer layer BUF2 and may be patterned by a photolithography process. The active layer ACT may include an active pattern of each of the TFT of the pixel circuit and the TFT of the gate driving unit. A portion of the active layer ACT may be metallized by ion doping. The metallized portions may be used as a jumper pattern (pumper pattern) connecting metal layers at some nodes of the pixel circuit to connect components of the pixel circuit.

The gate insulating layer GI may be formed on the second buffer layer BUF2 to cover the active layer ACT. The gate insulating layer GI may be made of an inorganic insulating material.

A second metal layer may be formed on the gate insulating layer GI. The second metal layer may be patterned by a photolithography process. The second metal layer may include a GATE line, a GATE electrode pattern GATE, a lower electrode of the storage capacitor Cst1, a skip pattern connecting the pattern of the first metal layer and the third metal layer, and the like.

A first interlayer insulating layer ILD1 may be formed on the gate insulating layer GI to cover the second metal layer. A third metal layer may be formed on the first interlayer insulating layer ILD1, and the second interlayer insulating layer ILD2 may cover the third metal layer. The third metal layer may be patterned by a photolithography process. The third metal layer may include a metal pattern TM, such as an upper electrode of the storage capacitor Cst 1. The first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 may each include an inorganic insulating material.

A fourth metal layer may be formed on the second interlayer insulating layer ILD2, and the inorganic insulating layer PAS1 and the first planarization layer PLN1 may be stacked on the fourth metal layer. A fifth metal layer may be formed on the first planarization layer PLN 1.

Some patterns of the fourth metal layer may be connected to the third metal layer through Contact holes (contacts) passing through the first planarization layer PLN1 and the inorganic insulating layer PAS 1. The first planarizing layer PLN1 and the second planarizing layer PLN2 may each be made of an organic insulating material capable of flattening their surfaces.

The fourth metal layer may include a first electrode and a second electrode of the TFT connected to the active pattern of the TFT through contact holes passing through the second interlayer insulating layer ILD 2. The data line DL and the power line may be implemented using the pattern SD1 of the fourth metal layer or the pattern SD2 of the fifth metal layer.

An anode AND (a first electrode layer of the light emitting element OLED) may be formed on the second interlayer insulating layer ILD 2. The anode AND may be connected to an electrode of the TFT serving as a switching element or a driving element through a contact hole passing through the second planarization layer PLN 2. The anode AND may be made of a transparent or semi-transparent electrode material.

The pixel defining film BNK may cover the anode AND of the light emitting element OLED. The pixel defining film BNK may be formed in a pattern defining a light emitting region (or an opening region) through which light passes from each pixel to the outside. The spacer SPC may be formed on the pixel defining film BNK. The pixel defining film BNK and the spacer SPC may be integrated by the same organic insulating material. The spacer SPC may secure a gap (gap) between a Fine Metal Mask (FMM) AND the anode AND so that the FMM does not contact the anode AND during a deposition process of the organic compound EL.

The organic compound EL can be formed in the light emitting region of each pixel defined by the pixel defining film BNK. The cathode CAT (a second electrode layer of the light emitting element OLED) may be formed on the entire surface of the display panel 100 so as to cover the pixel defining film BNK, the spacer SPC, and the organic compound EL. The cathode CAT may be connected to the VSS line PL3 formed of any one of the following metal layers. The cap layer CPL may cover the cathode CAT. The cap layer CPL may be made of an inorganic insulating material to block permeation of air (air) and gases released (out scattering) from the organic insulating material applied on the cap layer CPL to protect the cathode CAT. The inorganic insulating layer PAS2 may cover the cap layer CPL, and the planarization layer PCL may be formed on the inorganic insulating layer PAS 2. The planarization layer PCL may include an organic insulating material. The inorganic insulating layer PAS3 of the encapsulation layer may be formed on the planarization layer PCL.

A polarizing plate 18 may be disposed on the inorganic insulating layer PAS3 to improve outdoor visibility of the display device. The polarizing plate 18 may reduce reflection of light from the surface of the display panel 100 and block light reflected from the metal of the circuit layer 12, thereby improving the brightness of the pixel.

Referring to fig. 40, a partial area of each of the anode AND the light emitting element EL disposed in the second display area CA may extend to the light transmission area TA. Thus, the brightness of the light transmission region TA can be increased and uniform image quality can be achieved.

In addition, in the light transmission region TA, the first light transmission pattern 18d may be formed in the polarizing plate 18. The first light-transmitting pattern 18d may be formed by discoloring the polarizer 18b using a laser, or the first light-transmitting pattern 18d may be formed by partially removing the polarizer 18 b.

In the light transmission region TA, an opening H1 may be formed in the cathode CAT. The opening H1 may be formed by forming the cathode CAT on the pixel defining film BNK and then etching the cathode CAT and the pixel defining film BNK at the same time. Accordingly, the first trench RC1 may be formed in the pixel defining film BNK, and the opening H1 of the cathode CAT may be formed on the first trench RC 1. However, the present disclosure is not necessarily limited thereto, and the cathode CAT may be disposed on the second planarization layer PLN2 without forming the pixel defining film in the light transmission area TA.

In the light transmission region TA, the first light transmission pattern 18d is formed in the polarizing plate 18, and the opening H1 is formed in the cathode, so that the light transmittance can be improved. Thus, a sufficient amount of light may enter the camera module 400 so that camera performance may be improved. In addition, noise of the imaged image data can be reduced.

Referring to fig. 41, since the PPI of the second display region CA is relatively lower than the PPI of the first display region DA, the data driving unit may increase the range of the data voltage Vdata applied to the pixels of the second display region CA compared to the range of the data voltage Vdata applied to the pixels of the first display region DA.

Claims

1. A display device, comprising:

a first display region including a plurality of first pixel groups; and

a second display region including a plurality of second pixel groups and a plurality of light transmission regions,

wherein each of the plurality of second pixel groups includes a plurality of sub-pixels, and

in any one of the plurality of sub-pixels, a light emitting element is disposed in the light transmitting region.

2. The display device according to claim 1, wherein the second display region includes a first pixel row in which the plurality of second pixel groups are successively arranged in a first direction, and a second pixel row in which the plurality of light-transmitting regions are successively arranged in the first direction,

wherein the first pixel rows and the second pixel rows are alternately arranged in a second direction crossing the first direction.

3. The display device of claim 2, wherein the plurality of sub-pixels comprises: a first sub-pixel including a first light emitting element, a second sub-pixel including a second light emitting element, a third sub-pixel including a third light emitting element, and a fourth sub-pixel including a fourth light emitting element,

wherein a partial region of at least one of the second light emitting element and the fourth light emitting element is disposed in the light transmission region.

4. The display device according to claim 3, wherein the second light-emitting element and the fourth light-emitting element are green light-emitting elements.

5. The display device according to claim 3, wherein a first virtual line connecting centers of each of the second light-emitting element and the fourth light-emitting element intersects the first direction and the second direction.

6. The display device according to claim 5, wherein each of the plurality of first pixel groups includes a first green light-emitting element and a second green light-emitting element,

wherein a virtual line connecting centers of each of the first green light emitting element and the second green light emitting element is parallel to the first direction.

7. The display device according to claim 3, wherein a second virtual line passing through a center of each of the first light-emitting element and the third light-emitting element is taken as a reference,

the second light emitting element is disposed at one side of the second virtual line, and

the fourth light emitting element is disposed at the other side of the second virtual line.

8. The display device according to claim 3, wherein the first to fourth light-emitting elements of the plurality of second pixel groups have a structure in which light-emitting elements of the same color are provided in a quadrangular shape.

9. The display device according to claim 3, wherein the fourth light-emitting elements of the plurality of second pixel groups are provided along each of a plurality of square lines, and

the first light emitting element, the second light emitting element, and the third light emitting element are disposed inside each of the plurality of square lines.

10. The display device according to claim 1, wherein a resolution of the second display region is lower than a resolution of the first display region.

11. The display device according to claim 1, comprising lines provided in the first display region and the second display region,

wherein the line is disposed to bypass the light transmissive region.

12. The display device according to claim 1, comprising a cathode provided in the first display region and the second display region,

wherein the cathode includes an opening corresponding to the light-transmitting region.

13. The display device according to claim 1, wherein a shape of a light-emitting element of the first pixel group is different from a shape of a light-emitting element of the second pixel group.

14. A display device, comprising:

a first display region including a plurality of first pixel groups; and

wherein the plurality of second pixel groups comprise a plurality of sub-pixels,

the plurality of second pixel groups include a first light emitting element configured to emit red light, a third light emitting element configured to emit blue light, and a second light emitting element and a fourth light emitting element configured to emit green light, and

a first virtual line connecting centers of each of the second and fourth light emitting elements intersects a second virtual line connecting centers of each of the first and third light emitting elements.

15. The display device according to claim 14, wherein the second virtual line is used as a reference,

16. The display device according to claim 14, wherein the second display region includes a first pixel row in which the plurality of second pixel groups are continuously provided, and a second pixel row in which the plurality of light-transmitting regions are continuously provided.

17. The display device according to claim 14, wherein a part of at least one of the second light-emitting element and the fourth light-emitting element is provided in the light-transmitting region.

18. The display device according to claim 14, wherein the number of the plurality of second pixel groups provided in the second display region is smaller than the number of the plurality of first pixel groups provided in the first display region.

19. A display device, comprising:

a first display region including a plurality of first pixel groups; and

wherein the second display area comprises: a first unit region having a smaller number of pixels than the first display region; and a second unit region having a smaller number of pixels than the first unit region.

20. The display device according to claim 19, wherein

An image sensor is disposed in the first unit area, and

an infrared sensor is disposed in the second unit area.