CN115800728A - Clock charge pump circuit with output voltage configuration - Google Patents
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Abstract
A clocked charge pump circuit configured to output a voltage, comprising: the circuit comprises a voltage configuration unit, a clock generation unit, a charge pump unit and a switch sampling unit; wherein, the voltage configuration unit is used for controlling the output voltage V of the charge pump unit based on the initial charge amount of the internal parallel capacitor of the voltage configuration unit b The level state of (a); a clock generation unit for controlling the voltage V based on the switch c Generating a two-phase non-overlapping clock signal P for a charge pump cell A And P B And inputting it into the charge pump unit; a charge pump unit for generating a two-phase non-overlapped clock signal P based on the clock generation unit and the voltage configuration unit A And P B An output voltage V b To pump the power supply voltage, generate and output the starting voltage V of the switching tube Cbst (ii) a A switch sampling unit connected with the charge pump unit and based on the input voltage V in And starting voltage V of switching tube Cbs Obtaining a sampled voltage V sample 。
Description
Technical Field
The present invention relates to the field of integrated circuits, and more particularly, to a clock charge pump circuit for configuring an output voltage.
Background
At present, a switched capacitor sampling circuit is widely applied to various low-voltage low-power-consumption integrated circuits, when the power supply voltage in the circuit is very low, the on-resistance of a switching tube made of a CMOS tube is very high, so that an RC equivalent circuit is formed between the switching tube and a capacitor connected to the switching tube. The RC equivalent circuit will greatly influence the time for the signal to build up on the capacitor, especially when the gate voltage of the switching tube is around one-half of the supply voltage, and even charging and discharging over a half period of time will not build up the voltage on the capacitor to the desired value. At lower gate voltages the switch cannot even actually be turned on at all.
In the prior art, in order to prevent the occurrence of such a problem, a charge pump is often used to enhance the gate control voltage of the switching tube. For example, a lower power supply voltage is input into the charge pump, and twice amplification of the voltage value is achieved, so that the on-resistance of the switching tube is reduced under the action of a larger gate voltage, and the on-time is shortened. Therefore, the switched capacitor sampling circuit can still realize normal conduction even under the action of a very small input voltage by the method, and the conduction time is short enough.
However, the conventional charge pump circuit is used to realize the switched capacitor sampling circuit, and the gate voltage of the switching tube can only be modulated to be a fixed multiple of the power supply voltage. Due to the large variation of the power supply voltage, the floating may be performed in a wide range, for example, sometimes the power supply voltage may be low, and sometimes the power supply voltage may be close to the highest voltage allowed by the chip or circuit process. Many times, the power supply voltage is less than the maximum voltage allowed by the circuit technology. This makes the pump-up multiple of the charge pump contradictory to the actual value of the supply voltage. For example, when the charge pump is twice the charge pump, the power supply voltage may be closer to half of the highest voltage allowed by the chip or circuit process and exceed half of the highest voltage. For example, when the power supply voltage is floating in a small range of more than half of the maximum allowable voltage, if a charge pump is used, the actual voltage is higher than the maximum voltage, and the gate oxide of the switching tube breaks down at high voltage, thereby failing. At this time, if a charge pump is not used, the conventional power supply voltage cannot sufficiently drive the switching tube to be turned on, or the turn-on time delay is too long.
In view of the above, a new configuration circuit is needed to adjust the output multiple of the charge pump at any time according to the state of the power supply voltage or the requirement of the circuit designer.
Disclosure of Invention
In order to solve the defects in the prior art, an object of the present invention is to provide a clock charge pump circuit configured with an output voltage, wherein the output multiple of the charge pump is regulated and controlled by the initial charging states of N capacitors in a voltage configuration unit, so that a switched capacitor sampling circuit can provide a fast and accurate output of a sampling voltage.
The invention adopts the following technical scheme.
A clocked charge pump circuit configured to output a voltage, comprising: the circuit comprises a voltage configuration unit, a clock generation unit, a charge pump unit and a switch sampling unit; the voltage configuration unit is connected with the charge pump unit and used for controlling the output voltage V of the charge pump unit based on the initial charge amount of the capacitor connected in parallel in the voltage configuration unit b The level state of (1); a clock generation unit connected with the charge pump unit for controlling the voltage V based on the switch c Generating a two-phase non-overlapping clock signal P for a charge pump cell A And P B And inputting it into the charge pump unit; a charge pump unit respectively connected with the logic control unit, the voltage configuration unit and the switch unit for generating a two-phase non-overlapping clock signal P based on the clock signal P A And P B Output voltage V b To pump the power supply voltage, generate and output the starting voltage V of the switching tube Cb (ii) a A switch sampling unit connected with the charge pump unit and based on the input voltage V in And starting voltage V of switching tube Cbs Obtaining a sampled voltage V sample 。
Preferably, the voltage configuration unit comprises N configuration capacitors C B1 、C B2 To C BN (ii) a N configuration capacitors C B1 、C B2 To C BN One end of the MOS transistor Mn2 is connected with the source electrode of the MOS transistor Mn2 in the charge pump unit, and the other end of the MOS transistor Mn2 is respectively connected with the output end P in the clock generation unit B1 、P B2 To P BN And (4) connecting.
Preferably, it isThe clock generating unit comprises a first inverter, a second inverter, a first NAND gate, a second NAND gate, a first buffer, a second buffer, a first AND gate, a second NAND gate, a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a fifth AND gate and a sixth AND gate; wherein, the input end of the first phase inverter and the switch control voltage V c The output end of the first NAND gate is connected with the first input end of the first NAND gate and the second input end of the second NAND gate; the output end of the first NAND gate outputs a clock signal P after passing through the first buffer B The output end of the second NAND gate outputs a clock signal P after passing through the second buffer A The output end of the first buffer is connected with the first input end of the second buffer, and the output end of the second buffer is connected with the second input end of the first buffer; the input end of the first buffer is respectively connected with the input end of the second phase inverter and the second input ends of the first to Nth AND gates; the first input ends of the first to Nth AND gates are respectively connected with the enabling signals V of the N capacitors C1 、V C2 To V CN The output ends of the first to Nth AND gates are respectively used as the output end P of the clock generation unit B1 、P B2 To P BN (ii) a The output end of the second inverter outputs an inverted clock signal
Preferably, the charge pump unit comprises first to third NMOS tubes Mn1, mn2 and Mn3, a PMOS tube Mp1, and a capacitor C A (ii) a The grid electrode of the first NMOS transistor Mn1 is connected with the source electrode of the second NMOS transistor Mn2, and the drain electrode is connected with a power supply voltage V dd Connection of source to capacitor C A One end of the second NMOS tube Mn2 is connected with the grid electrode of the second NMOS tube Mn 2; capacitor C A The other end receives a clock signal P from a clock generation unit A (ii) a The grid electrode of the second NMOS tube Mn2 is connected with the source electrode of the first NMOS tube Mn1, and the drain electrode is connected with a power supply voltage V dd The source electrode is connected with N configuration capacitors in the voltage configuration unit; the source electrode of the PMOS tube Mp1 and the source electrode of the NMOS tube Mn2, and the voltage configuration unit comprise N configuration capacitors C B1 、C B2 To C BN Respectively connected to the drain of the NMOS transistor Mn3 and the input of the switch sampling unit, and the gate of the NMOS transistor Mn3 and the gate thereof respectively receiving the inverse from the clock generation unitPhase clock signal
The source electrode of the NMOS tube Mn3 is grounded, and the drain electrode of the NMOS tube is used as the output end of the charge pump unit.
Preferably, the switch sampling unit comprises a switch tube Mn sample And a switched capacitor C sample (ii) a Wherein, the switch tube Mn sample The grid electrode of the charge pump unit receives a switching tube starting voltage V output by the charge pump unit Cbst The drain electrode receives an input voltage V in Grid and switch capacitor C sample Connected and output a sampled voltage V sample (ii) a The other end of the switch capacitor is grounded.
Preferably, the enable signals V of N capacitors C1 、V C2 To V CN Based on switching tube starting voltage V Cbst Is set to the preset range.
Preferably, N configuration capacitors C B1 、C B2 To C BN All the capacitance values are equal.
Preferably, when M driving signals exist among the driving signals of the N capacitors, the level of the M driving signals is the power supply voltage V dd The level of N-M driving signals is always 0V, and the output voltage V of the charge pump unit is b The level state of the charge pump circuit is stabilized after the charge pump circuit works normally
Wherein M = [1,2,. -, N]。
Compared with the prior art, the clock charge pump circuit for configuring the output voltage has the advantages that the regulation and control of the output multiple of the charge pump can be realized through the initial charging states of the N capacitors in the voltage configuration unit, so that the switched capacitor sampling circuit can provide rapid and accurate output of the sampling voltage. The circuit structure is simple, the circuit structure is not required to be changed, the adaptation to different power supply voltage conditions can be met according to the flexible adjustment of a plurality of driving signals, and the output accuracy degree is high.
Drawings
FIG. 1 is a prior art switched capacitor sampling circuit with a charge pump according to the present invention;
FIG. 2 is a schematic diagram of a main circuit portion of a clock charge pump circuit configured with an output voltage according to the present invention;
FIG. 3 is a schematic diagram of a clock generation unit in a clock charge pump circuit configured with an output voltage according to the present invention;
FIG. 4 is a timing waveform diagram illustrating a start-up process of a clock charge pump circuit configured with an output voltage according to the present invention.
Detailed Description
The present application is further described below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present application is not limited thereby.
Fig. 1 is a prior art switched capacitor sampling circuit with a charge pump according to the present invention. As shown in fig. 1, a CMOS clock charge pump circuit used in the prior art can realize multiple outputs of power supply voltage by alternately turning on and off two cross-connected NMOS transistors. Specifically, the charge pump circuit in the prior art includes NMOS transistors Mn1 and Mn2, in which the source of one is connected to the gate of the other, and the drains thereof both receive the power supply voltage. In addition, the sources of the two NMOS transistors Mn1 and Mn2 are respectively connected with a capacitor, namely C A And C B Respectively connected to the control signals P of the charge pumps A And P B The above.
Similar to the control signal for the charge pump in the prior art, P A And P B Which may typically be implemented by non-overlapping clock signals. After two non-overlapped clock signals are input to two ends of the charge pump together, the MOS tube can be controlled to be switched on and switched off.
The principle of the charge pump in the present invention is illustrated by way of example. If the charge pump starts at a time, P A Is a supply voltage, P B When the input of (3) is 0, the position of the A point in the circuit can be deduced according to the element connection relation in FIG. 1, and the A point passes through the capacitor C A Then, the voltage is raised to the power supply voltage, and the position of the B point passes through a capacitor C B Then, the voltage is still 0V, and Mn2 is turned on by the voltage at point A, while Mn1 is turned off by the voltage at point B. Therefore, mn2 is turned on, raising the voltage at point B to the power supply voltage.
After the circuit passes a half period of the control signal, the two-phase non-overlapped clock signal P A And P B The switching of high and low levels is realized, so that P A Input of (2) is switched to 0, P B Is switched to the supply voltage. At this time, since the voltages at the two points AB at the previous time are both changed to the power supply voltage, the signals P follow A And P B The voltage difference between the two ends of the capacitor is not changed instantaneously, the voltage of the point A is switched to be 0V in the period, and the voltage of the point B can continuously rise on the basis of the power supply voltage in the period, so that the circuit realizes twice the power supply voltage on the point B.
The description continues with the subsequent circuit portions of the charge pump. Since the drain and gate of the two Mp1 and Mn3 tubes are connected to each other, and the source of Mp1 is connected to point B in the circuit, when the charge pump is started and P is P A Is a supply voltage, P B When the input of (B) is 0, the gate voltages of the two transistors are the power supply voltage, at this time Mp1 is turned off, mp3 is turned on, and the voltage at point B cannot be output to the subsequent circuit of the charge pump.
After the circuit passes a half period of the control signal, the two-phase non-overlapped clock signal P A And P B The switching of high and low levels is realized, the grid voltage of the two tubes is reduced at the moment, the Mp1 is conducted, and in the conducting process, the charge of a point B with the voltage increased to 2 times of the power supply voltage is output through the source-drain current of the Mp 1. At this time, since the on-resistance of the Mp1 tube is small, the voltage at the gate of the Mp1 tube can be considered to be equal to the voltage at point B.
Because the output end of the 2-time charge pump circuit is directly connected with the switched capacitor selection circuit, the starting voltage of the switched capacitor selection circuit is also changed into twice of the power supply voltage. At this time, the switching tube realizes the output of the sampling voltage along with the input voltage of the drain electrode of the switching tube. Because the switch can receive twice power supply voltage as the on-state control signal, even if the power supply voltage is lower at this moment, the resistance of the switch tube can be ensured not to be large, namely the RC equivalent circuit at the output end of the switch tube can not enable the on-state duration of the switch tube to be too long.
However, as described in the background section, the amplification factor of the charge pump with respect to the input voltage is very fixed, and the change of the power supply voltage with respect to the full scale is not fixed, so that the power supply voltage is too small to turn on the circuit when the charge pump is not used; with charge pumps, the supply voltage is excessive causing the circuit to overshoot.
Therefore, in view of the above problems, the present invention provides a clock charge pump circuit that configures an output voltage.
FIG. 2 is a schematic diagram of a main circuit of a clock charge pump circuit configured with an output voltage according to the present invention. As shown in fig. 2, the clock charge pump circuit for configuring an output voltage in the present invention includes a voltage configuration unit, a clock generation unit, a charge pump unit, and a switch sampling unit; a voltage configuration unit connected with the charge pump unit for controlling the output voltage V of the charge pump unit based on the initial charge amount of the internal parallel capacitor of the voltage configuration unit b High state of (2); a clock generation unit connected with the charge pump unit for controlling the voltage V based on the switch c Generating a two-phase non-overlapping clock signal P for a charge pump cell A And P B And inputting it into the charge pump unit; a charge pump unit respectively connected with the logic control unit, the voltage configuration unit and the switch unit for generating a two-phase non-overlapping clock signal P based on the clock signal P A And P B Output voltage V b To pump the power supply voltage, generate and output the starting voltage V of the switching tube Cbst (ii) a A switch sampling unit connected with the charge pump unit and based on the input voltage V in And starting voltage V of switching tube Cbst Obtaining a sampled voltage V sample 。
It will be appreciated that the circuit in the present invention is made up of multiple parts. In short, the charge pump unit in the present invention, very similar to the charge pump power supply commonly used in the prior art, includes a capacitor, an NMOS transistor, and Mp1 and Mp3, which are symmetrically arranged. Different from the content in the prior art, in the invention, N configuration capacitors exist at the position of a B point of a charge pump circuit, the configuration capacitors can be respectively connected with a plurality of different drive signal control ends directly or indirectly, and the charging and discharging states of the N capacitors can be controlled by controlling an input signal of the circuit, so that the high and low levels of the B point are configured. After the high and low levels of the point B are configured, the voltage of the point B can be transferred to the drain electrode of the Mp1 by the method, so that a proper grid voltage is provided for the switching tube.
Preferably, the voltage configuration unit comprises N configuration capacitors C B1 、C B2 To C BN (ii) a N configuration capacitors C B1 、C B2 To C BN One end of the MOS transistor is connected with the source electrode of the MOS transistor Mn2 in the charge pump unit, and the other end of the MOS transistor is respectively connected with the output end P in the clock generation unit B1 、P B2 To P BN And (4) connecting.
It can be understood that the N configuration capacitors in the present invention are all connected to the point B in the circuit, and the other end is based on the control signal P outputted by the clock generation unit B1 、P B2 To P BN The control of the capacitor voltage is realized. It is easy to think that the method in the present invention can set the initial states of a plurality of capacitors by a plurality of control signals, so that the voltage at the position of the B point in the circuit is determined by the plurality of capacitors in common.
Preferably, N configuration capacitors C B1 、C B2 To C BN All of the capacitance values of (a) are equal. It is understood that the capacitance values of the N configuration capacitors in the present invention can be set to be identical, thereby facilitating the calculation and the control of the actually generated voltage in the present invention.
Fig. 3 is a schematic diagram of a clock generation unit in a clock charge pump circuit configured with an output voltage according to the present invention. As shown in fig. 3, the clock generation unit preferably includes first and second inverters, first and second nand gates, first and second buffers,first to Nth AND gates; wherein, the input end of the first phase inverter and the switch control voltage V c The output end of the first NAND gate is connected with the first input end of the first NAND gate and the second input end of the second NAND gate; the output end of the first NAND gate outputs a clock signal P after passing through the first buffer B The output end of the second NAND gate outputs a clock signal P after passing through the second buffer A The output end of the first buffer is connected with the first input end of the second buffer, and the output end of the second buffer is connected with the second input end of the first buffer; the input end of the first buffer is respectively connected with the input end of the second phase inverter and the second input ends of the first to Nth AND gates; the first input ends of the first to Nth AND gates are respectively connected with the enabling signals V of the N capacitors C1 、V C2 To V CN The output ends of the first to Nth AND gates are respectively used as the output end P of the clock generation unit B1 、P B2 To P BN (ii) a The output end of the second inverter outputs an inverted clock signal
The generation mode of the clock control signal in the invention is similar to that of the non-overlapping clock generation circuit generally adopted in the prior art, and the circuit can be formed by adopting a logic gate mode. Wherein the output P A Is substantially the same as the high-low level of the control signal at the input terminal, and the output P B The phase is opposite to that of the control signal. In addition, a transit signal P B An inverted clock signal obtained after inversion
Is in phase with the control signal, and the drive signal P for a plurality of capacitors B1 、P B2 To P BN It will vary according to the variation of the enable signal at the input.
Preferably, the charge pump unit includes first to third NMOSMn1, mn2 and Mn3, PMOS tube Mp1, capacitor C A (ii) a The grid electrode of the first NMOS transistor Mn1 is connected with the source electrode of the second NMOS transistor Mn2, and the drain electrode is connected with a power supply voltage V dd Connection, source and capacitor C A One end of the second NMOS tube Mn2 is connected with the grid electrode of the second NMOS tube Mn 2; capacitor C A The other end of the first and second receiving circuits receives a clock signal P from a clock generating unit A (ii) a The grid electrode of the second NMOS tube Mn2 is connected with the source electrode of the first NMOS tube Mn1, and the drain electrode is connected with a power supply voltage V dd The source electrode is connected with N configuration capacitors in the voltage configuration unit; the source electrode of the PMOS tube Mp1 and the source electrode of the NMOS tube Mn2, the voltage configuration unit comprises N configuration capacitors C B1 、C B2 To C BN Respectively connected to the drain of the NMOS transistor Mn3 and the input of the switch sampling unit, and the gate of the NMOS transistor Mn3 and the gate thereof respectively receiving the inverted clock signal from the clock generating unit
The source electrode of the NMOS pipe Mn3 is grounded, and the drain electrode of the NMOS pipe Mn3 serves as the output end of the charge pump unit.
In the present invention, the specific structure of the charge pump unit is very similar to the structure of the charge pump unit in the prior art, and is not described herein again.
Preferably, the switch sampling unit comprises a switch tube Mn sample And a switched capacitor C sample (ii) a Wherein, the switch tube Mn sample The grid electrode of the charge pump unit receives a switching tube starting voltage V output by the charge pump unit Cbst The drain electrode receives an input voltage V in Grid and switch capacitor C sample Connect and output the sampling voltage V sample (ii) a The other end of the switch capacitor is grounded.
Through the control of the charge pump unit, the voltage configuration unit and the clock generation unit, the circuit can effectively realize the control of the grid voltage in the switch sampling unit, so that the circuit can effectively realize the sampling output.
Preferably, the drive signal V of N capacitors C1 、V C2 To V CN Based on switching tube starting voltage V Cbst Is set to the preset range.
In the invention, the enabling of the N capacitance driving signals can be flexibly realized based on the magnitude of the power supply voltage, and can also be designed in advance according to the requirement of a designer and stored in a circuit in advance.
It is understood that in the present invention, the capacitor C B The driving voltage of the lower polar plate can control the specific value of the output level of the circuit.
After the charge pump unit starts working, enabling signals V of a plurality of capacitors C1 、V C2 To V CN Respectively and the driving signal P B Enabling signals V acting on a plurality of capacitors together C1 、V C2 To V CN Part of the drive signal P may be divided B1 、P B2 To P BM Remains high and the other part of the driving signal is intercepted. With continued charging of the drive signals for the multiple capacitors, regardless of the state of the enable signal, C A And N of C B All will be charged with a total charge of NCV of the capacitors at point B in the circuit dd 。
The control signal P of the lower plate of each capacitor can not change suddenly A And P B Will make the voltage of the point A and the point B in the circuit change continuously, wherein the voltage of the point B will be at M P numbers as the function of the capacitance B When the voltage is at a high level, the voltage is increased in a certain proportion according to the change of the voltage of the lower polar plate, and the configuration of the output voltage is realized in this way.
Preferably, when the level of M driving signals in the lower plate driving signals of the N capacitors is changed from 0V to the power supply voltage V dd If the level of N-M driving signals is always 0V, the switch tube starts to operate at a voltage V B Is stable in the state after the charge pump normally works
Wherein M = [1, 2., N =]。
The calculation of the above formula can be made by saying that the start-up of the circuit in the present invention is to the process of achieving the steady stateAnd (5) clearing. FIG. 4 is a timing waveform diagram illustrating a start-up process of a clock charge pump circuit configured with an output voltage according to the present invention. The description of the above process can be further explained with reference to the voltage variation at each position in fig. 4. During the first period when the switch controls the voltage V c Two-phase non-overlapping clock signal P in circuit when in high level state A And P B Respectively 0V and V dd Since the charge pump circuit has not been started, the voltages at points a and B in the circuit are also 0. Meanwhile, M of the driving signals of the N capacitors are controlled to set enable states based on the magnitude of the power supply voltage or the advanced design of a circuit user, namely, the N capacitors can be driven by a clock, and C B1 ，C B1 ...C M ＝V dd (ii) a Enable of N-M drive signals is set to 0V, C M+1 ，C M+2 ...C N ＝0V。
For example, in one embodiment of the present invention, P may be set B1 、P B2 To P BM Has a driving signal thereon, and is provided with P BM+1 、P BM+2 To P BN The voltage on is 0. In other words, according to the setting of the clock generation unit, C is connected through N AND gates B1 、C B2 To C BM Based on a clock signal P B1 、P B2 To P BM Is driven to drive C BM+1 、C BM+2 To C BN Clock signal P BM+1 、P BM+ To P BN And carrying out corresponding shielding. In the first period, the voltage at the point B in the circuit is raised to V along with the control of a plurality of driving signals dd . This turns on the MOS transistor Mn1 and raises the voltage at point A to V dd 。
In the second time interval, when the circuit is in working state, the circuit is switched to high or low level for the first time, and the switch controls the voltage V c From the mains voltage V dd First switched to 0V, and then two-phase non-overlapped clock signals P are generated under the action of the clock generation circuit A And P B Hopping is also performed separately. Wherein the signal P B From the mains voltage V dd First switching to 0V, signal P A First switching from 0VTo the supply voltage V dd . Under the action of the switching process, the voltage of the point AB in the circuit changes along with the switching process, and the voltage of the point A is instantaneously increased to 2 times of the power supply voltage 2V due to the fact that the potential difference between the two ends of the capacitor is basically constant dd . The voltage at point B is momentarily lowered to 0V.
In this case, according to the voltages at points AB and AB, the MOS transistor Mn1 is turned off, the MOS transistor Mn2 is turned on, and since Mn1 is in the off state, the voltage at point a can be kept at the power supply voltage V during this period dd And is not changed. Since Mn2 is in the on state, the voltage at point B will gradually increase with the supply voltage of the drain of Mn2, and finally increase to the supply voltage V dd 。
After the second period of time is stabilized, the charge amounts in the capacitors at the point a and the point B in the circuit are respectively summed up, and charge amount data in the capacitors can be obtained. Specifically, the charge amount of the A point capacitor is the product of the voltage difference at two sides of the A point and the A point capacitor, and then
On the other hand, N capacitors C are connected to the point B of the circuit B1 、C B2 To C BN Therefore, the charge amount of the capacitor connected at the point B is the total charge amount of the N capacitors. The charge of the capacitor at point B is the product of the voltage difference between two ends of the capacitor and the capacitance of the capacitor, and has
It should be noted that, during the second period of operation of the circuit, the clock signal is inverted
Is switched to V dd Therefore, the MOS transistor Mp1 cannot be turned on, and the voltage at the B point is not transmitted to the gate of the switching transistor. In addition, only M capacitors are connected among N capacitors connected to the point BBoth ends have a voltage difference, while both ends of the other N-M capacitors do not have a voltage difference, so the circuit initially charges only the M capacitors. Over time, the N-M capacitors are charged by the M capacitors, i.e., the M capacitors discharge charge to the N-M capacitors, thereby leaving the N capacitors fully charged. Therefore, the total charge amount at the point B is known as V dd ·N·C B 。
In a third period, after the charge pump cell is turned off from the state where phase A, mn2, is on, it jumps to phase B, i.e. the two-phase non-overlapping clock signal P A And P B A flip occurs. This is due to the switch control voltage V in the circuit c Has been turned over again, jumps back to the power supply voltage V again from 0V dd So that the signal P at this time A At 0V, signal P B At a supply voltage V dd . According to signal P A And P B Will also vary the voltage at points a and B on the other side of the capacitor, the voltage at point a being derived from the supply voltage V dd Is momentarily pulled down to 0V, and the voltage at point B is derived from the supply voltage V dd Momentarily rises above the supply voltage. Specific values of the voltage at the point B will be described later.
However, according to the voltage state of the two points AB, the on-off states of the MOS transistors Mn1 and Mn2 are switched, the MOS transistor Mn1 is turned on, and the MOS transistor Mn2 is switched to the off state, at this time, the voltage at the point B remains unchanged due to the off of the MOS transistor Mn2, and the voltage at the point a is rapidly increased again to the power supply voltage V with the on of the MOS transistor Mn1 dd . Therefore, the charge amounts at the two points a and B can be confirmed by the following formulas. In the method, because the point a is not in a floating state any more, but a charge charging path exists, that is, mn1 is turned on, the charge amount at the point a changes, that is, the charge amount at the point a changes
Because Mn2 is cut off, the point B is in a floating state, and the charge quantity of the point B has no charge-discharge path, the point B is not kept before and after the state switchingAnd (6) changing. Specifically, the voltage at point B is compared with the power supply voltage V of the previous stage dd Is increased due to the driving signal at the other end of the N capacitors connected to the point B, i.e. P B1 、P B2 To P BN Is caused by the change in (c). Specifically, in the third period, the control signal P B1 、P B2 To P BM Pumping charge by M C B The voltage of the lower plate of (a) rises, so that the voltage causing the voltage rise at the point B can be calculated.
Suppose that at this time, the voltage in the circuit changes to V B (t 3 )，
Because point B is in a floating state, the charge remains unchanged, and therefore
Substitution into
And
can solve the lifted V B (t 3 )
In the third period, due to the inverted clock signal
Leads to the conduction of the MOS transistor Mp1, thereby enabling the gate voltage V of the switching tube connected to the drain of the MOS transistor Mp1 Cbst Equal to the voltage at point B in the period
When the MOS transistor Mn2 is not conducted in the third period, the point B is always in a suspended state, and the voltage of the point B is not changed and is always kept at
The above. In the fourth period, when the two AB points in the circuit are inverted again, P A The point potential being the supply voltage, P B The dot is 0V. Under ideal conditions without considering parasitic capacitance, charge leakage and the like, there is a point voltage V A Is instantaneously increased to 2 times of power supply voltage, voltage V at point B B Is momentarily pulled low. At this time, the Mn1 tube is turned off, and the Mn2 tube is turned on. And, with the conduction and the cutoff of the tube, the voltage of the point AB also changes, and the voltage of the point B is finally stabilized at the power voltage. The amount of charge at point A is
The charge amount of the B point is
At this time, the clock signal is inverted
Is increased again to V dd At this time, the Mp1 transistor is not turned on, and the gate voltage of the switching transistor is pulled down to 0V by Mn3, so that the switching transistor is not broken down or other unsafe factors occur due to the continuous accumulation of the gate voltage.
After the four time periods are finished, the circuit enters a stable working state and circularly switches between the third time period and the fourth time period, so that the stable conduction of the switching tube is ensured. The voltage at point A is switched between a power supply voltage 2 times and a power supply voltage 1 times at high and low levels, respectively, and the voltage at point B is switched between a power supply voltage 2 times and a power supply voltage 1 times at high and low levels, respectively
The power supply voltage is switched between 1 time and 1 time, so that the starting voltage V of the switching tube received by the grid electrode of the switching tube Cbst Respectively at high and low levels of
The power supply voltage is continuously switched between 0V and multiple times.
Therefore, the method of the invention can arbitrarily determine the starting voltage V of the switching tube Cbst Is higher than the power supply voltage and makes the switch tube start voltage V Cbst The power supply voltage can be adapted to the size of the power supply voltage, the voltage cannot be too large on the basis of providing the action of the charge pump, and the safety of the whole circuit is ensured.
For the
The multiple is analyzed, and the starting voltage V of the switching tube can be changed by changing the value of M Cbst The size of (2). Specifically, assuming that the power supply voltage is in a fixed state, when M =0, there is a switching tube start voltage V that is output Cbst High level state and supply voltage V dd Are equal in size. When M = N/2, the switch tube starts the voltage V Cbst Is equal to the supply voltage V dd 1.5 times of the total weight of the composition. When M = N, the high level state of the starting voltage of the switch tube is equal to the power voltage V dd 2 times of the total weight of the powder.
Compared with the prior art, the clock charge pump circuit with the output voltage has the advantages that the output multiple of the charge pump can be regulated and controlled through the initial charging states of the N capacitors in the voltage configuration unit, so that the switched capacitor sampling circuit can provide rapid and accurate output of the sampling voltage. The circuit structure is simple, the circuit structure is not required to be changed, the adaptation to different power supply voltage conditions can be met according to the flexible adjustment of a plurality of driving signals, and the output accuracy degree is high.
The present applicant has described and illustrated embodiments of the present invention in detail with reference to the accompanying drawings, but it should be understood by those skilled in the art that the above embodiments are merely preferred embodiments of the present invention, and the detailed description is only for the purpose of helping the reader to better understand the spirit of the present invention, and not for limiting the scope of the present invention, and on the contrary, any improvement or modification made based on the spirit of the present invention should fall within the scope of the present invention.
Claims (8)
1. A clocked charge pump circuit configured to output a voltage, comprising:
the circuit comprises a voltage configuration unit, a clock generation unit, a charge pump unit and a switch sampling unit; wherein the content of the first and second substances,
the voltage configuration unit is connected with the charge pump unit and used for controlling the output voltage V of the charge pump unit based on the initial charge quantity of the internal parallel capacitor of the voltage configuration unit b The level state of (a);
the clock generation unit is connected with the charge pump unit and used for controlling the voltage V based on the switch c Generating a two-phase non-overlapping clock signal P of the charge pump cell A And P B And input it into the charge pump unit;
the charge pump unit is respectively connected with the logic control unit, the voltage configuration unit and the switch unit and is used for generating a two-phase non-overlapping clock signal P based on the clock signal P which is respectively input by the clock generation unit and the voltage configuration unit A And P B An output voltage V b To pump the power supply voltage, generate and output the starting voltage V of the switching tube Cbst ；
The switch sampling unit is connected with the charge pump unit and is based on the input voltage V in And starting voltage V of switching tube Cbst Obtaining a sampled voltage V sample 。
2. A clocked charge pump circuit for configuring an output voltage as claimed in claim 1, wherein:
the voltage configuration unit comprises N configuration capacitors C B1 、C B2 To C BN ；
N configuration capacitors C B1 、C B2 To C BN One end of the MOS transistor Mn2 is connected with the source electrode of the MOS transistor Mn2 in the charge pump unit, and the other end of the MOS transistor Mn2 is respectively connected with the output end P in the clock generation unit B1 、P B2 To P BN And (4) connecting.
3. A clocked charge pump circuit for configuring an output voltage as claimed in claim 2, characterized in that:
the clock generation unit comprises a first inverter and a second inverter, first and second NAND gates, first and second buffers, and first to Nth AND gates; wherein, the first and the second end of the pipe are connected with each other,
an input terminal of the first inverter and the switch control voltage V c The output end of the first NAND gate is connected with the first input end of the first NAND gate and the second input end of the second NAND gate;
the output end of the first NAND gate outputs a clock signal P after passing through a first buffer B The output end of the second NAND gate outputs a clock signal P after passing through the second buffer A The output end of the first buffer is connected with the first input end of the second buffer, and the output end of the second buffer is connected with the second input end of the first buffer;
the input end of the first buffer is respectively connected with the input end of the second phase inverter and the second input ends of the first to Nth AND gates;
the first input ends of the first to Nth AND gates are respectively connected with the enabling signals V of the N capacitors C1 、V C2 To V CN The output ends of the first to Nth AND gates are respectively used as the output end P of the clock generation unit B1 、P B2 To P BN ；
The output end of the second phase inverter outputs an inverted clock signal
4. A clocked charge pump circuit for configuring an output voltage as claimed in claim 3, characterized in that:
the charge pump unit comprises first to third NMOS tubes Mn1, mn2 and Mn3, a PMOS tube Mp1 and a capacitor C A (ii) a Wherein the content of the first and second substances,
the grid electrode of the first NMOS tube Mn1 is connected with the source electrode of the second NMOS tube Mn2, and the drain electrode of the first NMOS tube is connected with a power voltage V dd Connected to source and said capacitor C A One end of the second NMOS tube Mn2 is connected with the grid electrode of the second NMOS tube Mn 2;
the capacitor C A The other end of the first and second receiving circuits receives a clock signal P from the clock generating unit A ；
The grid electrode of the second NMOS tube Mn2 is connected with the source electrode of the first NMOS tube Mn1, and the drain electrode is connected with a power supply voltage V dd The source electrode of the voltage configuration unit is connected with the N configuration capacitors in the voltage configuration unit;
the source electrode of the PMOS tube Mp1, the source electrode of the NMOS tube Mn2 and the voltage configuration unit comprise N configuration capacitors C B1 、C B2 To C BN Respectively connected to the drain of the NMOS transistor Mn3 and the input of the switch sampling unit, and the gate of the NMOS transistor Mn3 and the gate thereof respectively receive the inverted clock signal from the clock generation unit
And the source electrode of the NMOS tube Mn3 is grounded, and the drain electrode is used as the output end of the charge pump unit.
5. A clocked charge pump circuit for configuring an output voltage as claimed in claim 4, wherein:
the switch sampling unit comprises a switch tube Mn sample And a switched capacitor C sample (ii) a Wherein the content of the first and second substances,
the switch tube Mn sample The grid electrode of the charge pump unit receives the starting electricity of the switching tube output by the charge pump unitPressure V Cbs The drain electrode receives an input voltage V in Grid and said switched capacitor C sample Connected and output a sampled voltage V sample ；
And the other end of the switch capacitor is grounded.
6. A clocked charge pump circuit for configuring an output voltage as claimed in claim 5, characterized in that:
enabling signals V of the N capacitors C1 、V C2 To V CN Based on the starting voltage V of the switch tube Cbst Is set to the preset range.
7. A clocked charge pump circuit for configuring an output voltage as claimed in claim 6, wherein:
the N configuration capacitors C B1 、C B2 To C BN All the capacitance values are equal.
8. A clocked charge pump circuit for configuring an output voltage as claimed in claim 7, characterized in that:
when the level of M drive signals in the drive signals of the N capacitors is the power supply voltage V dd And if the level of the N-M driving signals is always 0V, the output voltage V of the charge pump unit is b Is stabilized in a state after the clock charge pump circuit normally works
Wherein M = [1, 2., N ].
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| CN202111061967.7A CN115800728A (en) | 2021-09-10 | 2021-09-10 | Clock charge pump circuit with output voltage configuration |
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| CN202111061967.7A CN115800728A (en) | 2021-09-10 | 2021-09-10 | Clock charge pump circuit with output voltage configuration |
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