CN115799326A

CN115799326A - P-type electrode structure and preparation method and application thereof

Info

Publication number: CN115799326A
Application number: CN202211588328.0A
Authority: CN
Inventors: 李利哲; 王国斌
Original assignee: Jiangsu Third Generation Semiconductor Research Institute Co Ltd
Current assignee: Jiangsu Third Generation Semiconductor Research Institute Co Ltd
Priority date: 2022-12-09
Filing date: 2022-12-09
Publication date: 2023-03-14

Abstract

The invention discloses a P-type electrode structure and a preparation method and application thereof. The P-type electrode structure comprises a work function metal layer which is arranged on the first surface of the P-type semiconductor layer and forms ohmic contact with the P-type semiconductor layer; and the amorphous metal oxide grid electrode is arranged on the work function metal layer and is electrically combined with the work function metal layer, and a local area on the surface of the work function metal layer is exposed out of the meshes of the amorphous metal oxide grid electrode. The P-type electrode structure provided by the invention adopts a double-layer conductive structure, and can effectively reduce the contact resistance with a P-type semiconductor layer.

Description

P-type electrode structure and preparation method and application thereof

Technical Field

The invention particularly relates to a P-type electrode structure and a preparation method and application thereof, and belongs to the technical field of semiconductors.

Background

Wide Bandgap (WBG) semiconductors, such as silicon carbide SiC and gallium nitride GaN, are considered to be the most potential materials in next generation power electronics devices. The wide-bandgap semiconductor has excellent semiconductor characteristics of wide bandgap, high breakdown, high frequency and the like, and compared with a Si-based semiconductor, the breakdown field intensity of the GaN material is more than 10 times, so that the excellent performance of the GaN material has wide application prospects in the fields of radio frequency microwave, power electronic laser and illumination.

However, the application of gallium nitride devices in various fields requiresThe ohmic contact electrode with excellent performance is taken as a solid foundation. One important factor causing poor performance of LEDs, lasers, HEMT devices, etc. of GaN material systems is poor ohmic contact quality of the source/drain of P-GaN devices or P-type gallium nitride layers, since P-GaN materials have a large work function (7.5 eV) and no suitable metal forms excellent ohmic contact; the hole concentration of the Mg-doped p-GaN material is difficult to improve, and the ohmic contact specific contact resistivity of the p-GaN material is difficult to be made into 10 of the n-GaN material ^-6 ～10 ^-8 Ω·cm ² The level of (c). Many common ohmic contact electrode systems for p-GaN materials are proposed: ni/Au, cr/Au, pt/Au, pd/Au, pt/Ni/Au, pd/Ni/Au, and having a specific contact resistivity of 10 ^-4 ～10 ^-5 Ω·cm ² Is 1-2 orders of magnitude higher than the n-GaN contact resistivity. Therefore, an electrode structure for reducing the contact resistance of P-type gan is urgently needed.

Disclosure of Invention

The invention mainly aims to provide a P-type electrode structure and a preparation method and application thereof, so that the defects in the prior art are overcome.

In order to achieve the purpose, the technical scheme adopted by the invention comprises the following steps:

in one aspect, the present invention provides a P-type electrode structure, including:

a work function metal layer disposed on a first surface of the P-type semiconductor layer and forming an ohmic contact with the P-type semiconductor layer;

and the amorphous metal oxide grid electrode is arranged on the work function metal layer and is electrically combined with the work function metal layer, and a local area on the surface of the work function metal layer is exposed out of the meshes of the amorphous metal oxide grid electrode.

Further, the first surface of the P-type semiconductor layer is non-flat.

Further, the region of the work function metal layer in contact with the first surface of the P-type semiconductor layer is non-planar.

Furthermore, the area of the first surface of the P-type semiconductor layer, which is in contact with the work function metal layer, is provided with at least one protruding structure and/or at least one pit structure, and part of the work function metal layer is wrapped on the surface of the protruding structure and/or part of the work function metal layer is filled in the pit structure.

Further, the convex structures and/or the concave structures are distributed in dislocation or defect areas of the first surface of the P-type semiconductor layer.

Further, the width of the protruding structures and/or the pit structures is 60-150nm, the height of the protruding structures is 60-150nm, and the depth of the pit structures is 60-150nm.

Further, the material of the work function metal layer includes any one of Au and Ni or an alloy formed by two metals, but is not limited thereto.

Furthermore, the thickness of the work function metal layer is 100-200nm.

Further, the total mesh area of the amorphous metal oxide grid electrode accounts for 65-80% of the surface of the amorphous metal oxide grid electrode.

Further, the material of the amorphous metal oxide mesh electrode includes amorphous Indium Zinc Oxide (IZO) and the like, but is not limited thereto.

Further, the thickness of the amorphous metal oxide grid electrode is 80-150nm.

Further, the amorphous metal oxide grid electrode is transparent.

The invention also provides a preparation method of the P-type electrode structure, which comprises the following steps:

forming a work function metal layer on a selected area of the first surface of the P-type semiconductor layer, and electrically combining the work function metal layer with the P-type semiconductor layer, wherein the selected area of the first surface of the P-type semiconductor layer is non-flat;

and forming an amorphous metal oxide grid electrode on the work function metal layer, electrically combining the amorphous metal oxide grid electrode with the work function metal layer, and exposing a local area on the surface of the work function metal layer from meshes of the amorphous metal oxide grid electrode.

Further, the preparation method specifically comprises the following steps: and arranging a mask on the first surface of the P-type semiconductor layer, exposing the selected area from the mask, performing plasma bombardment on the selected area to etch the defect part of the selected area to form a pit structure, forming the work function metal layer on the selected area, and forming the amorphous metal oxide grid electrode on the work function metal layer.

Further, the preparation method specifically comprises the following steps: and filling part of the work function metal layer in the pit structure, so that the region of the work function metal layer, which is in contact with the P-type semiconductor layer, is formed into a non-flat structure.

Further, the plasma used for the plasma bombardment includes inert gas plasma and the like.

Further, the time of the plasma bombardment is 20-150s.

Further, the pit structures are distributed in dislocation or defect areas of the first surface.

Furthermore, the width of the pit structure is 60-150nm, and the depth is 60-150nm.

Furthermore, the thickness of the work function metal layer is 100-200nm.

Further, the material of the amorphous metal oxide grid electrode includes amorphous Indium Zinc Oxide (IZO), but is not limited thereto.

Furthermore, the thickness of the amorphous metal oxide grid electrode is 80-150nm.

Further, the amorphous metal oxide mesh electrode may be transparent, i.e. light-transmissive.

Further, the preparation method also comprises the following steps: and removing the mask after the amorphous metal oxide grid electrode is formed, and carrying out annealing treatment so as to enable the work function metal layer and the P-type semiconductor layer to form ohmic contact.

Further, the temperature of the annealing treatment does not exceed 500 ℃.

Further, the temperature of the annealing treatment is 400-480 ℃.

Further, the time of the annealing treatment is 60s-15min.

Further, the annealing treatment is performed under an oxidizing gas atmosphere.

Further, the oxidizing gas includes oxygen, etc., but is not limited thereto.

The annealing treatment is performed on the P-type electrode structure and the P-type semiconductor layer, and the annealing can activate the doping ions of the P-type semiconductor layer and form an ohmic contact structure on the P-type electrode structure and the P-type semiconductor layer.

Further, the preparation method also comprises the following steps: and forming a passivation layer on the first surface of the P-type semiconductor layer after the annealing treatment is completed.

The invention also provides a semiconductor device comprising the P-type electrode structure or the P-type electrode structure obtained by the preparation method.

Further, the semiconductor device comprises a gallium nitride-based radio frequency device, a power device or a light-emitting device.

Compared with the prior art, the invention has the advantages that:

1) The P-type electrode structure provided by the invention adopts a double-layer conductive structure, so that the contact resistance between the P-type electrode structure and a P-type semiconductor layer can be effectively reduced;

2) According to the P-type electrode structure, the transparent amorphous IZO with the latticed structure is used as the amorphous metal oxide grid electrode, so that the light transmission performance can be improved, hydrogen can be easily escaped, and the influence of Mg-H bonds on the Mg carrier concentration is reduced;

3) According to the preparation method of the P-type electrode structure, the passivation layer is formed after the ohmic contact electrode is formed, more P-type semiconductor layers can be exposed in an annealing environment during annealing, mg ions are excited, and the existence of Mg-H bonds is reduced.

Drawings

FIG. 1a is a schematic diagram of a P-type electrode structure provided in an exemplary embodiment of the present invention;

FIG. 1b isbase:Sub>A cross-sectional view taken along line A-A' of FIG. 1base:Sub>A;

FIG. 1c is an enlarged partial schematic view of FIG. 1b at Structure A;

FIG. 1d is a schematic structural diagram of an amorphous metal oxide grid electrode in a P-type electrode structure according to an exemplary embodiment of the present invention;

FIGS. 2 a-2 g are schematic structural diagrams illustrating a method for fabricating a P-type electrode structure according to an exemplary embodiment of the present invention;

FIG. 3a is a schematic cross-sectional view of the structure of FIG. 2c at structure B;

FIG. 3B is a top view at structure B in FIG. 2 c;

FIG. 4 is a cross-sectional view taken along line B-B' of FIG. 2 e;

FIG. 5 is a schematic structural diagram of a grid mask structure employed in the present invention;

fig. 6 is a schematic flow chart of a method for manufacturing a P-type electrode structure according to an exemplary embodiment of the present invention.

Detailed Description

In view of the deficiencies in the prior art, the inventors of the present invention have made extensive studies and extensive practices to provide technical solutions of the present invention. The embodiments, implementations, principles, and so on of the present invention will be further explained with reference to the drawings and the embodiments, and unless otherwise specified, the deposition process equipment, the plasma bombardment equipment, the annealing equipment, the etching process and equipment, and so on of the present invention are well known to those skilled in the art.

Example 1

Referring to fig. 1a to 1d, a P-type electrode structure includes an ohmic contact electrode 200 disposed on a P-type semiconductor layer 100, where the ohmic contact electrode 200 includes a work function metal layer 210 and an amorphous metal oxide mesh electrode 220 sequentially stacked on a first surface of the P-type semiconductor layer 100, the work function metal layer 210 forms an ohmic contact with the P-type semiconductor layer 100, and the amorphous metal oxide mesh electrode 220 is electrically coupled to the work function metal layer 210.

In this embodiment, the ohmic contact electrode 200 is disposed in a second region (the second region may also be referred to as an electrode region, i.e., the aforementioned selected region, the same below) 112 of the first surface of the P-type semiconductor layer 100, the second region of the first surface of the P-type semiconductor layer 100 is a non-flat structure having at least one protrusion structure and/or at least one pit structure regularly or irregularly distributed, and a portion of the work function metal layer 210 is wrapped on the surface of the protrusion structure and/or a portion of the work function metal layer 210 and is filled in the pit structure, i.e., a contact region between the work function metal layer 210 and the P-type semiconductor layer 100 is also non-flat, so as to increase a contact area between the P-type semiconductor layer 100 and the work function metal layer 210, and increase a contact strength between the work function metal layer 210 and the P-type semiconductor layer 100, so that a bonding strength between the two is higher, and peeling is not easy to occur.

In the present embodiment, the protrusion structures and/or the pit structures are distributed on the dislocation or defect regions of the first surface of the P-type semiconductor layer 100, mainly because the dislocation or defect regions are fragile and easier to process, compared to the dislocation-free or defect-free regions.

In this embodiment, the width (which may be understood as a width or a maximum width or an average width at a certain position) of the protrusion structures and/or the pit structures is 60 to 150nm, the height (which may be understood as a height or a maximum height or an average height at a certain position) of the protrusion structures is 60 to 150nm, and the depth (which may be understood as a depth or a maximum depth or an average depth at a certain position) of the pit structures is 60 to 150nm, wherein the shapes of the protrusion structures and the pit structures are not limited herein.

In the embodiment, the material of the work function metal layer 210 includes any one of Au and Ni or an alloy formed by two metals, but is not limited thereto, and the thickness of the work function metal layer 210 is 100 to 200nm.

In the present embodiment, referring to fig. 1d again, the amorphous metal oxide grid electrode 220 is a grid structure having a plurality of meshes 221, and at least a local area of the surface of the work function metal layer 210 is exposed from the meshes 221, wherein the grid structure can increase/increase the contact point between the amorphous metal oxide grid electrode 220 and the work function metal layer 210, thereby reducing the contact resistance.

In this embodiment, the total mesh area of the amorphous metal oxide mesh electrode occupies 65-80% of the second surface of the amorphous metal oxide mesh electrode, which is disposed opposite to the first surface.

In this embodiment, the material of the amorphous metal oxide mesh electrode 220 includes amorphous Indium Zinc Oxide (IZO), and the thickness of the amorphous metal oxide mesh electrode 220 is 80-150nm.

In this embodiment, when the P-type electrode structure is applied to an optoelectronic device, the amorphous metal oxide mesh electrode 220 may be transparent.

As known to those skilled in the art, since the P-type semiconductor layer 100 is formed by Mg doping, hydrogen in a reaction gas (the reaction gas includes a nitrogen source (ammonia gas) for forming gallium nitride and a gallium source (trimethyl gallium) gas, the P-type doping source gas is cyclopentadienyl magnesium, and since the reaction gas contains organic matters, free hydrogen elements are generated) and can form Mg-H bonds with Mg, so as to influence the concentration of Mg carriers, which results in that the activation rate of Mg is reduced, the carrier concentration is lower, and the contact resistance is increased. Therefore, the present invention uses a metal with a higher work function, such as Au, ni or an alloy material thereof, as the ohmic contact layer (i.e., the work function metal layer) of the P-type semiconductor layer 100 to reduce the contact resistance, whereas the amorphous IZO has a higher work function (5.0 eV work function of amorphous IZO, 4.7eV work function of ITO), higher mobility, and adjustable composition compared to ITO, etc., and is more suitable as a P-type electrode contact layer (i.e., an amorphous metal oxide mesh electrode).

The P-type electrode structure in the invention has a double-layer conductive structure (i.e. the ohmic contact electrode), wherein the bottom layer is a work function metal layer formed by a metal or a metal alloy with a high work function, the contact surface between the work function metal layer and the P-type semiconductor layer is a non-flat structure with protrusions and/or pits, the work function metal layer corresponds to the uneven surface of the P-type semiconductor layer to reduce the contact resistance with the P-type semiconductor layer, the upper layer is a transparent amorphous metal oxide grid electrode formed by amorphous IZO, the amorphous IZO has a higher work function, the grid structure is favorable for breaking Mg-H bonds in the P-type semiconductor layer in a high-temperature environment, and hydrogen contained in a covered region in the P-type semiconductor layer is more easily reacted and escaped compared with a thicker bulk electrode material, so that the carrier concentration in the P-type semiconductor layer can be increased.

In this embodiment, referring to fig. 1a and fig. 1b again, a passivation layer 300 is further covered on the first surface of the P-type semiconductor layer 100, the passivation layer 300 is disposed in a first region of the first surface, the first region is disposed around the second region 112, wherein a material, a thickness, and the like of the passivation layer 300 are not limited in this embodiment.

The P-type electrode structure provided by the invention can be used for gallium nitride-based radio frequency devices, power devices or light emitting devices, such as lasers, LEDs, HEMT devices and the like, namely the P-type semiconductor layer can be P-type gallium nitride and the like.

In some embodiments of the present invention, referring to fig. 2a to fig. 2g and fig. 6, a method for manufacturing a P-type electrode structure may include the following steps:

s1) providing a base structure, wherein the uppermost layer of the base structure is a P-type semiconductor layer 100, as shown in fig. 2a, a first region 111 and a second region 112 are located on a first surface of the P-type semiconductor layer 100, and the first region 111 is disposed around the second region 112.

In this embodiment, the basic structure includes different layer structures according to the type of the device to be prepared, for example, when the device to be prepared is a laser, the basic structure may include a substrate (the substrate may be gallium nitride, sapphire substrate) and an n-type confinement layer, a lower waveguide layer, a quantum well active region, an upper waveguide layer, a P-type electron blocking layer, a P-type confinement layer, a P-type ohmic contact layer (doped P-type gallium nitride, i.e., P-type semiconductor layer 100) sequentially disposed on the substrate; when the device is an LED, the base structure may include a substrate (the substrate may be sapphire, silicon carbide, or gallium nitride), an n-type layer (n-type gallium nitride layer), an active layer (multi-layer quantum well layer), and a P-type semiconductor layer 100 (P-type gallium nitride layer, i.e., P-type semiconductor layer 100) stacked in this order; the invention focuses on the P-type electrode structure, and the specific structure, formation mode, doping concentration and the like of the basic structure are not further limited.

S2) forming a photoresist layer 400 on the first surface of the P-type semiconductor layer 100 of the basic structure, and then exposing and developing the photoresist layer in a second region corresponding to the ohmic contact electrode to expose the second region 112 of the first surface of the P-type semiconductor layer 100 at the bottom and leave the photoresist layer in the first region 111, as shown in fig. 2 b.

In this embodiment, the material of the photoresist layer 400 may be a positive photoresist or a negative photoresist, and when forming the photoresist layer, a layer of photoresist may be formed by spin coating, and then dried and cured, so as to form the photoresist layer.

It should be noted that after forming the base structure having the P-type semiconductor layer, in the prior art, a passivation layer is usually formed on the P-type semiconductor layer, the passivation layer covers the P-type surface, then an opening is formed in the passivation layer through photolithography and etching processes, and a P-type metal contact electrode is formed at the opening. However, such a forming step has a great disadvantage because a P-type semiconductor layer (usually P-type gallium nitride: P-GaN) is formed by Mg doping, hydrogen in a reaction gas can form Mg-H bonds with Mg, which affects the carrier concentration of Mg, and usually high-temperature annealing is required, the annealing temperature is 400 to 900 ℃, and the Mg-H bonds can be opened by annealing treatment, so as to increase the Mg carrier concentration, but because a passivation layer is formed in the existing process first and a P-type metal contact electrode is formed at an opening of the passivation layer and then the annealing treatment is performed, at this time, the P-type semiconductor layer is in a wrapping state of the passivation layer and the P-type metal contact electrode, although the temperature can be conducted into the P-type semiconductor layer during the high-temperature annealing to perform heat treatment on the P-type semiconductor layer, and the Mg-H bonds are broken during the heat treatment, but H in the P-type semiconductor layer in a sealing state does not disappear, and chemical bonds can be easily formed with the interaction between Mg element and H hydrogen element during the temperature reduction process, that a part of Mg-H bonds still exist after annealing, so that the carrier concentration cannot be increased.

S3) then performing plasma bombardment on the exposed second region of the first surface of the P-type semiconductor layer 100, thereby forming a plurality of pit structures in the second region of the first surface of the P-type semiconductor layer 100, as shown in fig. 2 c.

In this embodiment, the step S3) specifically includes: a base structure with an open photoresist layer (or a base structure with a photoresist layer covering a first area of a first surface) is fed into a plasma processing chamber, an inert gas is fed into the plasma processing chamber, at least part of the inert gas is converted into plasma, and an accelerating voltage is applied to make the plasma bombard a second area exposed on the first surface of the P-type semiconductor layer 100 so as to etch and form a plurality of pit structures 101 at surface defects of the second area of the first surface of the P-type semiconductor layer 100, as shown in fig. 3a and 3 b.

In this embodiment, the flow rate of the inert gas can be controlled to be 50-150sccm, the accelerating voltage is 400-600KeV, and the plasma bombardment time is 20-150s.

In this embodiment, since there are many dislocation structures or defects on the surface of the P-type semiconductor layer (e.g., P-type gallium nitride), the crystal arrangement of the dislocation or defect region is unstable and is fragile relative to the dislocation or defect-free region, when the bombardment is performed by using the inert gas plasma, scattered pit structures are more easily formed where the dislocations and defects are concentrated, the depth and the aperture of the pit structures are both in the nanometer level, generally several tens to several hundreds of nanometers, and for example, the depth and the aperture of the pit structures are both 60 to 150nm, and of course, the aperture and the depth of the pit structures can be controlled by controlling the bombardment time and the like.

S4) forming a work function metal layer 210 on the second region (i.e. the electrode region or the electrode forming region) 112 exposed on the first surface of the P-type semiconductor layer, and electrically bonding the work function metal layer 210 and the P-type semiconductor layer, as shown in fig. 2 d.

In this embodiment, after the plasma bombardment, a metal with a high work function is deposited in the second region of the first surface of the P-type semiconductor layer by using a conventional sputtering or electron beam evaporation method in the art, and a portion of the metal is filled in the pit structure of the first surface of the P-type semiconductor layer, so as to form a work function metal layer, where the thickness of the work function metal layer is 100-200nm.

In this embodiment, the contact resistance can be reduced by using a metal having a high work function, such as Au, ni, or an alloy thereof, as the work function metal layer of the P-type semiconductor layer; in addition, the first surface of the P-type semiconductor layer has the pit structures which are irregularly distributed after being bombarded by the plasma, and the deposited metal is distributed on the pit structures 101 and the first surface of the P-type semiconductor layer 100, so that the contact area between the work function metal layer and the P-type semiconductor layer 100 is increased, on one hand, the adhesion and the bonding strength between the work function metal layer and the P-type semiconductor layer are improved, the risk of separation between the work function metal layer and the P-type semiconductor layer due to stress is reduced, and on the other hand, the contact resistance between the work function metal layer and the P-type semiconductor layer is also reduced.

S5) forming an amorphous metal oxide mesh electrode 220 formed by amorphous IZO on the work function metal layer 210 by using a radio frequency magnetron sputtering method, wherein the thickness of the amorphous metal oxide mesh electrode 220 is 80-150nm, as shown in fig. 2e and 5.

In this embodiment, step S5) may specifically include:

5.1 In, zn targets with In molar contents of 55-80% can be used, bombarded with an inert gas plasma (Ar or Xe or a mixture thereof) which causes the metal atoms (e.g. In, zn) constituting the target to be dislodged from the target surface, mixing a reactive component of oxygen to the targetForming a mixed gas of an inert gas (e.g., neon, argon, kr, and Xe) and O in the mixed gas ₂ The content of the metal is 5-8%, and the metal atoms react with oxygen to form IZO before deposition and deposit the IZO in a designated area;

5.2 Using a mask structure having a mesh shape (as shown in fig. 4), amorphous IZO having a mesh structure is deposited on the work function metal layer 210 at a temperature of 220 to 300 c, thereby forming an amorphous metal oxide mesh electrode 220.

In this example, conductivity was measured by subjecting IZO of different crystal forms to conductivity test, wherein conductivity is the reciprocal of resistivity, and in international units, conductivity is expressed in siemens/meter (S/cm) and is expressed herein in siemens/centimeter (S/cm), and the greater the conductivity, the better the conductivity and vice versa. The amorphous IZO was tested to have a conductivity of 2000-2700S/cm, while the polycrystalline IZO has a conductivity of 1500-1800S/cm, and the difference In conductivity of the amorphous or polycrystalline IZO depends on the ratio of In or Zn In the IZO, which can be adjusted by adjusting the ratio of In or Zn, but the conductivity of the polycrystalline IZO is generally lower than that of the amorphous IZO.

In the embodiment, the electrode with the grid-shaped structure can increase the transparency to light, increase the contact point between the electrode and the work function metal layer, further improve the conductivity, and reduce the shielding of the P-type semiconductor layer below the ohmic contact electrode, thereby being more beneficial to the escape of hydrogen when the Mg-H bond in the P-type semiconductor layer is broken.

S6) removing the photoresist layer 400, annealing the formed electrode structure and the P-type semiconductor layer, and making the work function metal layer and the P-type semiconductor layer form ohmic contact, and activating the doping ions of the P-type semiconductor layer, as shown in fig. 2 f.

In this embodiment, the annealing temperature is 400-480 ℃ and the time is 60S-15min, it should be noted that the annealing temperature cannot exceed 500 ℃, and if the annealing temperature is higher than 500 ℃, the IZO crystal form is transformed, and the carrier mobility is reduced.

In this embodiment, the atmosphere of the annealing treatment is an oxygen atmosphere, on one hand, H broken in the oxygen atmosphere is easily combined with oxygen and easily removed at a high temperature; on the other hand, when annealing is carried out in the oxygen atmosphere, the crystalline state of IZO is maintained in the annealing step in the oxygen atmosphere, and hydrogen can be prevented from diffusing into the IZO layer to passivate the defects of the IZO layer, so that the carrier mobility is improved; it should be noted that, when annealing is performed in an oxygen atmosphere, the material of the work function metal layer, such as Au or Ni, is not oxidized below 500 ℃, and the conductivity of the electrode is not affected.

In this embodiment, the photoresist layer may be removed by a stripping or ashing process commonly used in the art, and the P-type semiconductor layer is exposed after the photoresist layer is removed, and at this time, annealing treatment is performed, which is more favorable for breaking Mg — H bonds.

S7) depositing a passivation layer 300 on the first region of the first surface of the P-type semiconductor layer 100, as shown in fig. 2 g.

In this embodiment, the material of the passivation layer 300 may be silicon oxide, silicon nitride, or the like, and it should be noted that the thickness of the passivation layer is consistent with the thickness of the ohmic contact electrode 200, for example, the thickness of the passivation layer 300 is 150 to 300nm, so as to obtain a P-type electrode structure, and the P-type electrode structure obtained in embodiment 1 is denoted as sample 1.

Comparative example 1

The structure and the manufacturing method of the P-type electrode structure in comparative example 1 are substantially the same as those of example 1 except that: in comparative example 1, an amorphous IZO layer of a planar structure was used as an amorphous metal oxide grid electrode, and the P-type electrode structure obtained in comparative example 1 was designated as sample 2.

Comparative example 2

The structure and the manufacturing method of the P-type electrode structure in comparative example 2 are substantially the same as those of example 1 except that: in comparative example 2, a polycrystalline IZO layer having a lattice-like structure was used as an amorphous metal oxide grid electrode, and the P-type electrode structure obtained in comparative example 2 was denoted as sample 3.

Comparative example 3

The structure and the manufacturing method of the P-type electrode structure in comparative example 3 are substantially the same as those of example 1 except that: in comparative example 3, a passivation layer is formed on a P-type semiconductor layer, the passivation layer covers the surface of the P-type semiconductor layer, then an opening is formed in the passivation layer through photolithography and etching processes, and an ohmic contact electrode is formed at the opening, the P-type electrode structure obtained in comparative example 3 is denoted as sample 4, and it should be noted that the processes of forming the passivation layer and etching the passivation layer are known to those skilled in the art and are not specifically limited herein.

Comparative example 4

The structure and the manufacturing method of the P-type electrode structure in comparative example 4 are substantially the same as those of example 1 except that: the regions where the P-type semiconductor layer 100 and the work function metal layer 210 were in contact with each other in comparative example 4 were flat, and the P-type electrode structure obtained in comparative example 4 was denoted as sample 5.

Specific contact resistance (Ω · cm) to sample 1, sample 2, sample 3 and sample 4 by hall test ² ) The results of the tests are shown in Table 1.

Table 1 shows the results of specific contact resistance measurements of sample 1, sample 2, sample 3, sample 4 and sample 5

As can be seen from the comparison of the specific contact resistances shown in table 1, by comparing sample 1 and sample 2, the grid-structured IZO layer can be obtained, compared to the plane-structured IZO layer, because the grid-structured IZO electrode can expose the metal at the bottom, and when annealing is performed in the oxygen atmosphere, the hydrogen in the P-type semiconductor layer can diffuse into the work function metal layer, and then react in the oxygen atmosphere to reduce the presence of hydrogen, while in the plane-structured IZO layer, after diffusing into the work function metal layer, the hydrogen is passivated with the defects such as grain boundaries in the IZO layer and is not easily removed, and the resistance is also increased; as can be understood from comparison between samples 1 and 3, the conductivity of polycrystalline IZO is lower than that of amorphous IZO and is higher than the contact resistance; comparing samples 1-3 with sample 4, it can be known that the passivation layer is formed first, which is not beneficial to the diffusion of the subsequent hydrogen element, and the Mg-H bond is formed after the temperature is reduced, which affects the contact resistance, while the P-type semiconductor layer and the work function metal layer with smooth surfaces are easy to warp, which leads to the reduction of the contact area between the two, and further leads to the increase of the specific contact resistance, and because the surfaces of the P-type semiconductor layer 100 and the work function metal layer 210 in sample 5 are flat, the contact area is small relative to the contact area of sample 1, and the contact resistance is relatively large.

It should be understood that the above-mentioned embodiments are merely illustrative of the technical concepts and features of the present invention, which are intended to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and therefore, the protection scope of the present invention is not limited thereby. All equivalent changes and modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.

Claims

1. A P-type electrode structure, comprising:

2. The P-type electrode structure of claim 1, wherein: the first surface of the P-type semiconductor layer is non-flat; preferably, a region of the work function metal layer in contact with the first surface of the P-type semiconductor layer is non-flat;

preferably, the region of the first surface of the P-type semiconductor layer, which is in contact with the work function metal layer, has at least one protruding structure and/or at least one recessed structure, and a part of the work function metal layer is coated on the surface of the protruding structure and/or a part of the work function metal layer is filled in the recessed structure;

preferably, the raised structures and/or the pit structures are distributed in dislocation or defect regions of the first surface of the P-type semiconductor layer;

preferably, the width of the protruding structures and/or the pit structures is 60-150nm, the height of the protruding structures is 60-150nm, and the depth of the pit structures is 60-150nm.

3. The P-type electrode structure of claim 1 or 2, wherein: the material of the work function metal layer comprises any one metal or alloy formed by two metals of Au and Ni;

and/or the thickness of the work function metal layer is 100-200nm.

4. The P-type electrode structure of claim 1, wherein: the total mesh area of the amorphous metal oxide grid electrode accounts for 65-80% of the surface of the amorphous metal oxide grid electrode;

preferably, the material of the amorphous metal oxide grid electrode comprises amorphous indium zinc oxide;

preferably, the thickness of the amorphous metal oxide grid electrode is 80-150nm;

preferably, the amorphous metal oxide grid electrode is transparent.

5. A preparation method of a P-type electrode structure is characterized by comprising the following steps:

6. The preparation method according to claim 5, comprising: arranging a mask on the first surface of the P-type semiconductor layer, exposing the selected area from the mask, performing plasma bombardment on the selected area to etch the defect part of the selected area to form a pit structure, forming the work function metal layer on the selected area, and forming the amorphous metal oxide grid electrode on the work function metal layer;

preferably, a part of the work function metal layer is filled in the pit structure, so that a non-flat structure is formed in a contact area of the work function metal layer and the P-type semiconductor layer;

preferably, the plasma used for plasma bombardment comprises a noble gas plasma; preferably, the time of the plasma bombardment is 20-150s;

preferably, the width of the pit structure is 60-150nm, and the depth is 60-150nm.

7. The production method according to claim 5 or 6, characterized in that: the material of the work function metal layer comprises any one metal or alloy formed by two metals of Au and Ni;

and/or the thickness of the work function metal layer is 100-200nm;

and/or the total mesh area of the amorphous metal oxide grid electrode accounts for 65-80% of the surface of the amorphous metal oxide grid electrode;

and/or the amorphous metal oxide grid electrode is transparent.

8. The method of claim 5, further comprising: removing the mask after the amorphous metal oxide grid electrode is formed, and carrying out annealing treatment so as to enable the work function metal layer and the P-type semiconductor layer to form ohmic contact;

preferably, the temperature of the annealing treatment does not exceed 500 ℃;

preferably, the temperature of the annealing treatment is 400-480 ℃;

preferably, the time of the annealing treatment is 60s-15min;

preferably, the annealing treatment is performed under an oxidizing gas atmosphere, and preferably, the oxidizing gas includes oxygen.

9. The method of manufacturing according to claim 8, further comprising: and forming a passivation layer on the first surface of the P-type semiconductor layer after the annealing treatment is completed.

10. A semiconductor device characterized by comprising: the P-type electrode structure of any one of claims 1 to 4 or obtained by the production method of any one of claims 5 to 9; preferably, the semiconductor device comprises a gallium nitride-based radio frequency device, a power device or a light emitting device.