CN115799296A

CN115799296A - III-nitride diode device and manufacturing method and application thereof

Info

Publication number: CN115799296A
Application number: CN202111062410.5A
Authority: CN
Inventors: 魏星; 张晓东; 赵德胜; ***
Original assignee: Guangdong Zhongke Semiconductor Micro Nano Manufacturing Technology Research Institute; Suzhou Institute of Nano Tech and Nano Bionics of CAS
Current assignee: Guangdong Zhongke Semiconductor Micro Nano Manufacturing Technology Research Institute; Suzhou Institute of Nano Tech and Nano Bionics of CAS
Priority date: 2021-09-10
Filing date: 2021-09-10
Publication date: 2023-03-14

Abstract

The invention discloses a III-nitride diode device and a manufacturing method and application thereof. The group III-nitride diode device includes: a group III nitride heterojunction having a two-dimensional electron gas formed therein; the first electrode and the second electrode are electrically connected through the two-dimensional electron gas; the group III-nitride diode device further includes: and a plurality of third semiconductors, wherein the plurality of third semiconductors are matched with the heterojunction, any two adjacent third semiconductors are arranged at intervals, each third semiconductor can exhaust the two-dimensional electron gas at the part below the third semiconductor, and the plurality of third semiconductors are respectively in electrical contact with the first electrode. The manufacturing method provided by the invention reduces the influence of the starting voltage and the interface state of the device, improves the dynamic characteristic and the reliability of the device, and has simple process and easy integration.

Description

III-nitride diode device and manufacturing method and application thereof

Technical Field

The invention relates to a diode, in particular to a III-nitride diode device and a manufacturing method and application thereof, and belongs to the technical field of semiconductors.

Background

Group III nitrides (e.g., gallium nitride GaN) have excellent material properties such as large forbidden bandwidth, high breakdown field strength, high electron mobility, high electron saturation drift velocity, and are considered to be very suitable for the application of next-generation power electronic systems. Gallium nitride transistors based on p-GaN/AlGaN/GaN structures have been commercialized and are being developed toward monolithic integration to take advantage of the high switching frequency and high conversion efficiency of GaN devices. In power electronic systems, diodes are indispensable components, but the conventional diodes are schottky diodes prepared by schottky contacts, the conventional process for preparing GaN schottky diodes in p-GaN/AlGaN/GaN structures is quite complex, the depth, roughness and uniformity are difficult to control, and the GaN schottky diodes have a large number of problems including high turn-on voltage, large reverse leakage, low reverse withstand voltage, metal selection and the like.

Disclosure of Invention

The main objective of the present invention is to provide a III-nitride diode device, and a method for manufacturing the same and an application thereof, so as to overcome the disadvantages of the prior art.

In order to achieve the purpose, the technical scheme adopted by the invention comprises the following steps:

an embodiment of the present invention provides 1a group III nitride diode device, including:

the semiconductor device comprises a first semiconductor and a second semiconductor, wherein the first semiconductor and the second semiconductor are matched to form a heterojunction, and two-dimensional electron gas is formed in the heterojunction;

the first electrode and the second electrode are electrically connected through the two-dimensional electron gas;

wherein the III-nitride diode device further comprises:

and the plurality of third semiconductors are matched with the heterojunction, any two adjacent third semiconductors are arranged at intervals, each third semiconductor can exhaust the two-dimensional electron gas at the part below the third semiconductor, and the plurality of third semiconductors are respectively in electrical contact with the first electrode.

In a specific embodiment, the first electrode comprises:

a first portion in electrical contact with the two-dimensional electron gas of a first type;

a second portion in electrical contact with a plurality of said third semiconductors of a second type;

and the first part is electrically connected with the second part.

In one embodiment, the first type of electrical contact comprises an ohmic contact and the second type of electrical contact comprises an ohmic contact or a schottky contact.

In one embodiment, any two adjacent third semiconductors are electrically isolated by the high-resistance material, and/or a plurality of the third semiconductors are electrically isolated from the second electrode by the high-resistance material.

In one embodiment, the high-resistance material is formed by converting a continuous first region of a third semiconductor layer, and a plurality of the third semiconductor layers are distributed in a second region of the third semiconductor layer;

or, the plurality of third semiconductors are formed by converting a continuous second area of the high-resistance material layer, and the high-resistance material is distributed in the first area of the high-resistance material layer.

In one embodiment, the third semiconductor is a p-type semiconductor.

In one embodiment, the material of the third semiconductor includes a p-type wide bandgap semiconductor.

In one embodiment, the p-type wide bandgap semiconductor comprises a p-type group iii nitride.

In one embodiment, the p-type group iii nitride comprises p-type GaN, p-type AlGaN, p-type InGaN, or p-type InN, among others.

In one embodiment, the p-type wide bandgap semiconductor comprises p-NiO.

In one embodiment, the high-resistivity material is high-resistivity GaN, high-resistivity AlGaN, or high-resistivity Ga ₂ O ₃ High resistance InGaN, high resistance InN, or the like.

In a specific embodiment, a plurality of the third semiconductors are distributed in a continuous third semiconductor layer, a fourth semiconductor is further disposed on a region of the third semiconductor layer between any two adjacent third semiconductors, and the fourth semiconductor and the third semiconductor layer cooperate to form a pn junction.

In one embodiment, the fourth semiconductor is an n-type semiconductor, and the material of the n-type semiconductor includes n-type GaN and n-type Ga ₂ O ₃ N-type In ₂ O ₃ N-type InGaN, n-type InN, or the like.

In one embodiment, the first electrode and the second electrode are an anode and a cathode, respectively.

In one embodiment, the first semiconductor, the second semiconductor, and the third semiconductor are sequentially stacked, the first portion of the first electrode and the second electrode are disposed on the second semiconductor, and the second portion of the first electrode is disposed on the first portion and the plurality of third semiconductors.

In a specific embodiment, the second portion of the first electrode completely masks the plurality of third semiconductors.

In a specific embodiment, the plurality of third semiconductors are sequentially arranged at intervals along a designated direction, wherein two ends of any one of the third semiconductors are respectively directed to the first portion of the first electrode and the second electrode.

In a specific embodiment, the width of the third semiconductor is not less than 2 μm, the length is 10nm to 10 μm, and the distance between two adjacent third semiconductors is 1nm to 10 μm.

In a specific embodiment, the third semiconductor has a thickness of 10nm to 1 μm.

In one embodiment, the first semiconductor and the second semiconductor are made of materials selected from group iii nitrides.

In one embodiment, the material of the first semiconductor includes GaN.

In one embodiment, the material of the second semiconductor includes Al _x Ga _(1-x) N, alInGaN or In _x Al _(1-x) N，0＜x≤1。

In a specific embodiment, the ill-nitride diode device further comprises a field plate.

The embodiment of the invention also provides a manufacturing method of the III-nitride diode device, which comprises the following steps:

manufacturing a first semiconductor and a second semiconductor, wherein the first semiconductor and the second semiconductor are matched to form a heterojunction, and two-dimensional electron gas is formed in the heterojunction;

a step of manufacturing a first electrode and a second electrode, wherein the first electrode and the second electrode are electrically connected through the two-dimensional electron gas;

the manufacturing method further comprises the following steps:

and a step of manufacturing a plurality of third semiconductors, wherein the plurality of third semiconductors are matched with the heterojunction, any two adjacent third semiconductors are arranged at intervals, each third semiconductor can exhaust the two-dimensional electron gas at the part below the third semiconductor, and the plurality of third semiconductors are respectively in electrical contact with the first electrode.

In a specific embodiment, the manufacturing method specifically includes:

sequentially forming a first semiconductor, a second semiconductor and a continuous third semiconductor layer, the third semiconductor layer comprising a first region and a second region,

performing conversion treatment on the first region to form a high-resistance material, and enabling the high-resistance material to electrically isolate the plurality of third semiconductors distributed in the second region from each other;

or sequentially forming a first semiconductor, a second semiconductor and a continuous high-resistance material layer, wherein the high-resistance material layer comprises a first region and a second region,

and performing conversion treatment on the second region to form a plurality of third semiconductors, and enabling the high-resistance material distributed in the first region to electrically isolate the third semiconductors from each other.

In a specific embodiment, the manufacturing method further includes: the high-resistance material electrically isolates the third semiconductors from the second electrode.

In a specific embodiment, the method for performing the conversion treatment includes any one or a combination of more of H ion implantation, H plasma treatment, H doping annealing, N ion implantation, F ion implantation, ar ion implantation, fe ion implantation, and oxygen plasma treatment, but is not limited thereto.

In a specific embodiment, the manufacturing method specifically includes:

sequentially forming a first semiconductor and a second semiconductor;

and epitaxially growing a plurality of the third semiconductors on the second semiconductor upper regions.

In a specific embodiment, the manufacturing method specifically includes:

sequentially forming a first semiconductor and a second semiconductor;

and epitaxially growing a plurality of the third semiconductors and the high-resistance materials on the second semiconductor upper region, and electrically isolating any two adjacent third semiconductors from each other by the high-resistance materials.

In a specific embodiment, the manufacturing method specifically includes:

sequentially forming a first semiconductor, a second semiconductor and a continuous third semiconductor layer, wherein the third semiconductor layer comprises a plurality of third semiconductors;

and growing a fourth semiconductor on the region of the third semiconductor layer between any two adjacent third semiconductors, and enabling the fourth semiconductor to be matched with the third semiconductor layer to form a pn junction.

In one embodiment, the third semiconductor is a p-type semiconductor.

In a specific embodiment, the p-type wide bandgap semiconductor comprises a p-type group iii nitride.

In one embodiment, the p-type wide bandgap semiconductor comprises p-NiO.

An embodiment of the present invention also provides a group III nitride semiconductor device, including:

a first electrode and a second electrode electrically connected by the two-dimensional electron gas;

the source electrode and the drain electrode are also electrically connected through the two-dimensional electron gas, and the grid electrode is arranged between the source electrode and the drain electrode;

the group III nitride semiconductor device further includes:

a plurality of third semiconductors disposed in cooperation with the heterojunction, wherein any two adjacent third semiconductors are spaced apart from each other, each third semiconductor is capable of depleting the two-dimensional electron gas in a portion located thereunder, and the plurality of third semiconductors are further in electrical contact with the first electrode, respectively;

and the first electrode is also electrically connected with the source electrode.

In a specific embodiment, the group III nitride semiconductor device further includes a fifth semiconductor that is disposed between the gate and the heterojunction, and that is capable of depleting a portion of the two-dimensional electron gas located therebelow.

In one embodiment, the fifth semiconductor is electrically isolated from the source and the drain by a high resistance material, the high resistance material is formed by transforming a continuous first region of the fifth semiconductor layer, and the fifth semiconductor is distributed in a second region of the fifth semiconductor layer; or the fifth semiconductor is formed by converting a continuous second area of the high-resistance material layer, and the high-resistance material is distributed in the first area of the high-resistance material layer.

In a specific embodiment, the first electrode comprises:

and the first part is electrically connected with the second part.

In one embodiment, the second portion of the first electrode is partially disposed between the source and drain electrodes.

In one embodiment, the high-resistance material is formed by converting a continuous first region of a third semiconductor layer, and a plurality of the third semiconductor layers are distributed in a second region of the third semiconductor layer; or, the plurality of third semiconductors are formed by converting a continuous second region of the high-resistance material layer, and the high-resistance material is distributed in the first region of the high-resistance material layer.

In a specific embodiment, the third semiconductor and the fifth semiconductor are both p-type semiconductors.

In one embodiment, the third semiconductor and the fifth semiconductor are made of p-type wide bandgap semiconductors.

In one embodiment, the p-type wide bandgap semiconductor comprises p-NiO.

In one embodiment, the fourth semiconductor is an n-type semiconductor, and the material of the n-type semiconductor includes n-type GaN and n-type Ga ₂ O ₃ N-type In ₂ O ₃ N-type InGaN, or n-type InN.

In one embodiment, the first semiconductor, the second semiconductor, and the third semiconductor are sequentially stacked, the first portion of the first electrode and the second electrode are both disposed on the second semiconductor, and the second portion of the first electrode is disposed on the first portion and the plurality of third semiconductors.

Compared with the prior art, the invention has the advantages that:

1) According to the III-group nitride diode device provided by the embodiment of the invention, the strip-shaped p-GaN array mixed anode structure can flexibly adjust the starting voltage by adjusting the widths of different p-GaN and HR-GaN, so that a diode with low starting voltage is obtained;

2) According to the III-nitride diode device provided by the embodiment of the invention, the breakdown voltage and the on-resistance of the device can be improved by expanding the transverse size of the p-GaN array part;

3) According to the manufacturing method of the III-nitride diode device, provided by the embodiment of the invention, the anode region of the device is not required to be etched, so that the problems of uniformity, repeatability and introduced damage caused by an etching process are solved;

4) According to the manufacturing method of the III-nitride diode device, provided by the embodiment of the invention, the influence of the interface state of the device is reduced, and the reliability of the device is improved;

5) The manufacturing method of the III-nitride diode device provided by the embodiment of the invention also reduces the influence of parasitic capacitance and improves the frequency characteristic of the device.

6) The manufacturing method of the III-nitride diode device provided by the embodiment of the invention has the advantages of simple process, good repeatability, compatibility with the p-GaN-gate HEMT device process and easiness in integration.

Drawings

Fig. 1a and 1b are schematic structural diagrams of a group iii nitride diode device according to an exemplary embodiment of the present invention;

fig. 2-5 are schematic diagrams illustrating a process flow for fabricating a group iii nitride diode device according to an exemplary embodiment of the present invention;

fig. 6a, 6b, 6c, 6d, and 6e are graphs showing 2DEG concentration variations of a group iii nitride diode device provided in an exemplary embodiment of the present invention at different p-GaN stripe array sizes;

fig. 7a, 7b, 7c, and 7d are simulation test results of forward characteristics of a group iii nitride diode device according to an exemplary embodiment of the present invention;

fig. 8a is a schematic diagram of a group iii-nitride diode device integrated with a GaN HEMT in accordance with an exemplary embodiment of the present invention;

fig. 8b is a schematic diagram of an integrated electrode structure of a group iii nitride diode device and a GaN HEMT according to an exemplary embodiment of the present invention;

FIGS. 9a and 9b are schematic structural diagrams of a current sensor provided in an exemplary embodiment of the present invention;

fig. 9c is a test plot of a current sensor provided in an exemplary embodiment of the invention.

Detailed Description

In view of the deficiencies in the prior art, the inventors of the present invention have made extensive studies and extensive practices to provide technical solutions of the present invention. The technical solution, its implementation and principles, etc. will be further explained as follows.

As shown in fig. 1a and 1b, in the present invention, a p-GaN array (i.e., formed by regularly arranging a plurality of third semiconductors arranged at intervals, and of course, the material of the third semiconductors may also be p-type semiconductor material such as p-AlGaN) is formed on a iii-nitride heterojunction, and a device structure as shown in fig. 1a is fabricated, where an epitaxial structure of the device is compatible with a commercially available enhanced p-GaN gate GaN High Electron Mobility Transistor (HEMT), that is, the requirement for integrating a HEMT and the diode on the same wafer is satisfied.

In one aspect, an anode of the iii-nitride diode includes two different metals, one of which is a metal a (i.e., the first portion of the first electrode, the same applies below) forming an ohmic contact with a two-dimensional electron gas (2 DEG), and the other of which is a metal B (i.e., the second portion of the first electrode, the same applies below) forming an ohmic contact or a schottky contact with p-GaN (i.e., the third semiconductor, the same applies below), and the metal B connects the metal a and the p-GaN.

In the group iii nitride diode provided by the embodiment of the present invention, the p-GaN layers connected to the anode are in a discontinuous structure in a direction along the width of the anode (or along the radius direction of the anode if the anode of the device is circular), which can be understood as that the p-GaN layers are aligned along the width direction of the anode, and a high resistance material can be further disposed between two adjacent p-GaN layers and p-GaN layers, and the high resistance material can be HR-GaN, etc.

Specifically, the inventors of the present invention have found that the structure of the group iii nitride diode provided in the embodiments of the present invention does not damage the reverse breakdown voltage characteristics of the device, and the structure is compatible with a transistor device, thereby facilitating the integration of the device.

The core design idea of the group III nitride diode device provided by the embodiment of the invention is to adopt H plasma treatment (hereinafter referred to as H treatment) or H treatment and annealing or NH carrying treatment ₃ Annealing the p-GaN under the atmosphere condition and manufacturing the p-GaN into a strip-shaped p-GaN array mixed anode planar structure, wherein the anode structure can realize low starting voltage and adjustable starting voltage, and can improve the breakdown voltage of the device.

Compared with the traditional etching material technology, the manufacturing method of the III-nitride diode device provided by the embodiment of the invention has the advantages that the p-type semiconductor material is processed in an H plasma mode to form the p-type semiconductor array in the oriented arrangement, the etching is not needed, and the complex surface repairing process is not needed. Compared with the groove etching technology, the invention firstly provides the strip-shaped p-GaN array mixed anode plane structure, the process difficulty is small, the reliability is high, and the preparation process is compatible with GaN HEMT and easy to integrate.

The embodiments, implementations, principles, and so on of the present invention will be further explained with reference to the drawings and the embodiments, and unless otherwise specified, the epitaxial growth, etching, and so on of semiconductors used in the embodiments of the present invention may be known to those skilled in the art.

Referring to fig. 1a and 1b, a III-nitride diode device includes: the semiconductor device comprises a buffer layer and a group III nitride heterojunction which are sequentially arranged on a substrate, wherein two-dimensional electron gas is formed in the group III nitride heterojunction; and

a cathode, an anode, a p-type semiconductor array, and a high resistance material, wherein the anode includes a first portion and a second portion electrically connected to each other, the first portion and the cathode are electrically connected to a two-dimensional electron gas in the group III nitride heterojunction, the second portion forms an ohmic contact or a Schottky contact with the third semiconductor array and completely covers the p-type semiconductor array,

the p-type semiconductor array comprises a plurality of p-type semiconductors arranged on a group III nitride heterojunction, the p-type semiconductors are sequentially arranged at intervals along the width direction of a first part of an anode, two ends of each p-type semiconductor point to the first part of the anode and a cathode respectively, and the high-resistance materials are arranged between two adjacent p-type semiconductors and between the p-type semiconductors and the cathodes.

Specifically, the first portion of the anode, the second portion of the anode, and the cathode may be metal electrodes, the first portion of the anode and the cathode may be the same metal, for example, the first portion of the anode and the cathode may be metal a, the second portion of the anode and the first portion of the anode may be different metals, for example, the second portion of the anode may be metal B.

Specifically, the working principle and the simulation test result of the group III nitride diode device provided by the embodiment of the present invention are as follows:

in the group III nitride diode device provided in the embodiment of the present invention, the 2DEG concentration of the channel portion is controlled by the p-GaN strip array structure under the metal electrode B, and when no anode bias is applied, the 2DEG of the channel portion is depleted or partially depleted, and the device is in an "off" state; when an anode forward bias is applied, since p-GaN/AlGaN/GaN can be regarded as a "pin" diode, a depletion region of a channel portion becomes narrow, 2DEG is restored, and a device starts to be turned "on" in a forward direction; when an anode reverse bias is applied, the 'pin' diode is turned off, a depletion region is widened, and the device is in a 'turn-off' state at the moment; the forward-direction starting voltage of the device structure can be regarded as the HEMT device threshold voltage of the p-GaN strip array grid structure.

The inventor tests the group III nitride diode device through Silvaco-TCAD simulation software, and the test result shows that the change of the 2DEG concentration under different p-GaN strip array sizes is shown in the figures 6a, 6b, 6c and 6 d.

The inventor also carries out simulation test on the forward characteristics of the III-nitride diode device, and the test result shows that the change of the turn-on voltage of the device is shown in fig. 7a, 7b and 7c under different p-GaN strip array sizes; from the data, the diode with p-GaN stripe array anodes has a lower turn-on voltage and higher current density than a diode with a full p-GaN anode, meaning a significant improvement in device performance.

The inventor tests the group III nitride diode device through Silvaco-TCAD simulation software, and the test result shows that the change of the 2DEG concentration under different p-GaN strip array sizes is shown in the figures 6a, 6b, 6c, 6d and 6 e. Under different p-GaN strip array sizes, the 2DEG concentration is different, and the larger the size is, the higher the concentration is; the smaller the size, the lower the concentration. A suitably high concentration of 2DEG helps to achieve a low turn-on voltage.

The inventor also carries out simulation test comparison of the forward characteristics of the III-nitride diode device and the device in the comparative example 1, and the results show that the turn-on voltage of the device in the comparative example 1 is about 1.23V (current density is 1 mA/mm), the turn-on voltage of the III-nitride diode device in the present case is less than 0.3V, the turn-on voltage of the device is continuously reduced along with the increase of the size of the p-GaN stripe array (the turn-on voltage of the device with the size of 2 μm is lower than 0.16V), and the turn-on voltage of the device is changed as shown in FIGS. 7a, 7b, 7c and 7 d; from the data, the diode with p-GaN stripe array anodes has a lower turn-on voltage and higher current density than a diode with a full p-GaN anode, meaning a significant improvement in device performance.

Referring to fig. 2-5, a method for fabricating a III-nitride diode device may include the following steps:

1) Growing a substrate/buffer layer/group III nitride heterojunction/p-type semiconductor material structure by adopting an epitaxial technology such as Metal Organic Chemical Vapor Deposition (MOCVD), molecular Beam Epitaxy (MBE) or Hydride Vapor Phase Epitaxy (HVPE);

it should be noted that, the substrate may be selected from Si, SOI, siC, gaN, sapphire, etc., and the thickness of the substrate may be from 100 μm to 10mm; the buffer layer can be high-resistance GaN and the like, and the thickness of the buffer layer can be from 100nm to 1mm; the III group nitride heterojunction can be AlGaN/GaN heterojunction, alInN/GaN heterojunction, alGaN/InGaN/GaN heterojunction, alGaN/AlN/GaN heterojunction and the like; the thickness of the group iii nitride heterojunction may be from 10nm to 10 μm; the p-type semiconductor can be p-GaN, p-AlGaN or other p-type semiconductor materials, and the thickness can be from 10nm to 1 μm;

2) Removing the p-type semiconductor material (such as p-GaN) and part or all of the barrier layer (such as AlGaN) in the cathode region and the anode region by adopting dry or wet etching technologies such as reactive ion etching and ion beam etching; the etching area can be determined by photoetching or mask transfer technology; it should be noted that in this step, heavily doped n-GaN can be secondarily epitaxially grown in the etching region;

3) Manufacturing a metal electrode A in a cathode region and an anode region by adopting metal deposition technologies such as electron beam evaporation or sputtering, and then annealing the metal electrode A to form good ohmic contact, wherein the annealing treatment region can be determined by technologies such as photoetching and mask transfer;

4) Providing a device capable of generating hydrogen (H) plasma, which is not limited to a device such as reactive ion etching (ICP, RIE) and the like, performing H plasma treatment on a p-type semiconductor positioned in an anode region by adopting H plasma, and simultaneously performing H plasma treatment on the p-type semiconductor between a cathode region and an anode region to form a high-resistance material, wherein the aim is to release electrons at a channel so as to form a plurality of p-type semiconductors distributed at intervals in the anode region, the p-type semiconductors can exhaust two-dimensional electron gas distributed below the p-type semiconductors, and the two-dimensional electron gas distributed below the high-resistance material is reserved to form the channel;

the H plasma processing area can be determined by the technologies of photoetching, mask transfer and the like, and the plane geometric shapes of the p-type semiconductors are regular shapes or irregular shapes; the shapes of the parallel channels can be the same or different, and the number of the channels can be adjusted (can be more than 1); the width of the channel can be from several nanometers to several micrometers, namely the range of 1nm-10 μm, and of course, the surface of the channel can also be optimized by annealing treatment, wet etching or surface oxidation and the like, so as to reduce surface defects and passivate the surface defect state;

5) And manufacturing a metal electrode B by adopting a metal deposition technology such as electron beam evaporation or sputtering, and enabling the metal electrode B to cover the plurality of p-type semiconductors and the metal electrode A in the anode region, wherein the contact between the metal electrode B and the p-type semiconductors can be Schottky contact, or metal-insulating layer-semiconductor contact or metal-oxide layer-semiconductor contact can be adopted in order to further reduce the gate leakage current or increase the breakdown voltage of the device.

It can be understood that, in the above description, which is only a typical manufacturing method of a group III nitride diode device in the embodiment of the present invention, for the interconversion between a p-type semiconductor and a high-resistance material, the present inventors further adopt other methods such as doping or ion implantation to process the p-type semiconductor material to form the high-resistance material, and of course, H plasma processing and then annealing may be performed to form high-resistance gallium nitride (HR-GaN), and then O plasma processing may be performed to achieve the purpose of the present invention; of course, the object of the present invention can also be achieved by forming a high-resistance material on the group III nitride by epitaxy, and then forming a plurality of p-type semiconductors arranged at intervals by activating the selection region, or by directly extending a p-type semiconductor material or an HR semiconductor material through the selection region; further, the objects of the present invention may also be achieved by epitaxially growing an n-type semiconductor material on selected regions of a p-type semiconductor material.

It should be noted that the size of the metal electrode B is submicron or larger, the contact between the metal electrode B and the p-type semiconductor may be a schottky contact, or a metal-insulating layer-semiconductor contact or a metal-oxide layer-semiconductor contact may be used to further reduce the gate leakage current or increase the breakdown voltage of the device.

Specifically, in the channel array distributed among the p-type semiconductors in the anode region, the planar geometry of the channel may be regular or irregular, the parallel channel may be the same or different, the channel may be a single channel or a plurality of channels, and the channel width may be from several nanometers to several micrometers, i.e., 1nm to 10 μm.

Specifically, the apparatus for generating H plasma is not limited to the apparatus for reactive ion etching (ICP/RIE/NLD) and the like, and any apparatus for generating H plasma can be used, and it is needless to say that the present invention is not limited to the use of H treatment, and H ion implantation, H annealing, N ion implantation and the like can be used, and the main purpose is to make p-GaN highly resistant GaN, and the position of the H plasma treatment region can be freely adjusted. The planar shape of the processing region may be a regular shape or an irregular shape. The parallel channels are of the same shape or of different shapes. The processing area can be single or multiple, and the width can be adjusted freely according to the distance between the cathode and the anode of the device.

Specifically, in the embodiment of the present invention, the diode in the present invention may be integrated with a GaN HEMT, and the structure of the integrated device is as shown in fig. 8a, and the diode in the present invention is embedded in a HEMT device and applied to a GaN switching power supply;

referring to fig. 8a and 8b, a group III nitride semiconductor device includes a first semiconductor and a second semiconductor, the first semiconductor and the second semiconductor cooperating to form a group III nitride heterojunction, the group III nitride heterojunction having a two-dimensional electron gas formed therein;

an anode and a cathode electrically connected by the two-dimensional electron gas;

the group III nitride semiconductor device further includes:

a plurality of p-type semiconductors disposed in cooperation with the heterojunction, wherein any two adjacent p-type semiconductors are spaced apart from each other, each p-type semiconductor is capable of depleting the two-dimensional electron gas in a portion located therebelow, and the p-type semiconductors are further in electrical contact with the anodes, respectively;

and the anode is also electrically connected with the source electrode.

Specifically, the group III nitride semiconductor device further includes a high-resistance semiconductor which is provided between the gate electrode and the heterojunction and which is capable of depleting the two-dimensional electron gas in a portion located therebelow.

Specifically, the high-resistance semiconductor is electrically isolated from the source electrode and the drain electrode through a high-resistance material, the high-resistance material is formed by converting a first area of a continuous high-resistance semiconductor layer, and the high-resistance semiconductor is distributed in a second area of the high-resistance semiconductor layer; or the high-resistance semiconductor is formed by converting a continuous second area of the high-resistance material layer, and the high-resistance material is distributed in the first area of the high-resistance material layer.

Specifically, the second portion of the anode is partially disposed between the source and the drain.

Specifically, the first type of electrical contact includes an ohmic contact, and the second type of electrical contact includes an ohmic contact or a schottky contact.

Specifically, any two adjacent p-type semiconductors are electrically isolated by a high-resistance material, and/or a plurality of p-type semiconductors are electrically isolated from the cathode by a high-resistance material.

Of course, the diode of the present invention may be embedded in a HEMT device and may also be used as a current sensor, the structure of the current sensor is shown in fig. 9a and 9b, and the performance test result of the integrated device is shown in fig. 9c, wherein, because the diode of the sensor electrode portion has a smaller on-voltage, a higher sensitivity may be obtained, and the potential of the collector portion may be used to obtain the drain output current.

Certainly, the diode in the invention is embedded in an HEMT device and can also be used as a current sensor, the structure of the current sensor is shown in fig. 9a and 9b, the electrode of the sensor is positioned between the grid and the drain, the potential change can be sensed in the normal working process of the device, the potential change and the output current of the device can form a one-to-one dynamic relation, and the current of the device at the moment can be known by obtaining the potential. The performance test result of the integrated device is shown in fig. 9c, the solid curve is the output current of the device, the scattered curve is the potential change obtained by the sensor, and the two curves are well matched, namely, the integrated device has good current sensing working characteristics.

Wherein, because the diode of the electrode part of the sensor has smaller turn-on voltage, thus can obtain higher sensitivity, can adopt the electric potential of the electrode part, get the drain output current.

It should be noted that, the purpose of the present invention can also be achieved by replacing GaN with other materials capable of providing a heterojunction; of course, a dielectric layer can also be added at the interface of the p-type semiconductor and the gate metal.

Example 1

A method of fabricating a group III nitride diode device, comprising the steps of:

1) Growing the epitaxial structure shown in fig. 2 by Metal Organic Chemical Vapor Deposition (MOCVD);

wherein, the substrate is Si (111), the buffer layer is high-resistance GaN, and the thickness is 3-5 μm; the thickness of a GaN channel layer in the AlGaN/GaN heterojunction is 150-300nm, the thickness of an AlGaN barrier layer is 20-30nm, and the Al component is 0.15-0.25; p-GaN is selected as the p-type semiconductor material, and the thickness is 50-100 nm;

2) Removing p-GaN and partial AlGaN layer in the cathode region and the anode region by reactive ion etching, respectively forming metal A (Ti/Al/Ni/Au) in the cathode region and the anode region by electron beam evaporation, and then forming metal A in nitrogen (N) ₂ ) Annealing for 30-40 s under the condition of atmosphere and 800-900 ℃;

3) Defining an array of strip-shaped channels using an electron beam lithography machine, using SiO ₂ As a subsequent etch mask, siO ₂ The thickness is 50-200 nm;

4) Treating selected regions of p-GaN with H plasma using a reactive ion etching (ICP) apparatus, followed by N ₂ Annealing for 3-5 minutes at 300-500 ℃ in the atmosphere to form a strip-shaped channel array, wherein the residual p-GaN forms a p-GaN array comprising a plurality of p-GaN which are arranged and distributed in an oriented mode;

5) Manufacturing metal B (Ni/Au) by adopting an electron beam evaporation technology, wherein the metal B is electrically connected with metal A in an anode region and forms ohmic contact or Schottky contact with p-GaN, and the metal B completely covers the p-GaN array;

6) Growing a 300nm SiN passivation layer on the surface of the epitaxial structure;

7) And processing to form openings in the cathode region and the anode region of the passivation layer, and forming a metal interconnection structure to finish integration.

Comparative example 1

A group III nitride diode device of comparative example 1 was fabricated in substantially the same manner as example 1, except that comparative example 1 formed an integral p-GaN in the anode region, i.e., the anode region did not have a channel array.

The inventors also performed a comparison of simulation tests on the forward characteristics of the III-nitride diode device in example 1 and the device in comparative example 1, and the results show that the turn-on voltage of the device in comparative example 1 is about 1.23V (current density 1 mA/mm), while the turn-on voltage of the III-nitride diode device in example 1 is less than 0.3V, and the turn-on voltage of the device decreases with the increase of the size of the p-GaN stripe array (the turn-on voltage of the device with the size of 2 μm is further as low as 0.16V), and the turn-on voltage of the device changes as shown in fig. 7a, 7b and 7 c; from the data, the diode with p-GaN stripe array anodes has a lower turn-on voltage and higher current density than a diode with a full p-GaN anode, meaning a significant improvement in device performance.

The manufacturing method of the III-nitride diode device provided by the embodiment of the invention has the advantages of simple process and good repeatability, and the manufacturing method of the III-nitride diode device provided by the embodiment of the invention is compatible with the p-GaN-gate HEMT device process and is easy to integrate;

according to the manufacturing method of the III-nitride diode device, provided by the embodiment of the invention, the anode region of the device is not required to be etched, so that the problems of uniformity, repeatability and introduced damage caused by an etching process are solved; the manufacturing method of the III-nitride diode device provided by the embodiment of the invention reduces the interface state influence of the device and improves the reliability of the device; in addition, the manufacturing method of the group III nitride diode device provided by the embodiment of the invention also reduces the influence of parasitic capacitance and improves the frequency characteristic of the device.

The strip-shaped p-GaN array hybrid anode structure in the III-group nitride diode device provided by the embodiment of the invention can flexibly adjust the starting voltage by designing different widths of p-GaN and HR-GaN, and can greatly reduce the starting voltage of the diode; and, the group III nitride diode device provided by the embodiments of the present invention can also improve the performance (breakdown voltage, on-resistance) of the device by expanding the lateral dimension of the p-GaN array portion.

According to the III-nitride diode device provided by the embodiment of the invention, due to the introduction of the channel, the current of a single channel is much smaller than that of a traditional device, so that the heat dissipation is better than that of the traditional device, and the self-heating effect existing in the traditional heterojunction field effect transistor can be effectively inhibited.

The group III nitride diode device provided by the embodiment of the present invention can be implemented by using a conventional semiconductor micromachining technology, and the applicable equipment includes a lithography system (such as equipment for electron beam lithography, ion beam lithography, immersion lithography, distributed exposure, and optical exposure), a nanoimprint technology, etching equipment (RIE, ICP, NLD, etc.), ion implantation equipment, and the like.

It should be understood that the above-mentioned embodiments are merely illustrative of the technical concepts and features of the present invention, which are intended to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and therefore, the protection scope of the present invention is not limited thereby. All equivalent changes and modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.

Claims

1. A group III-nitride diode device, comprising:

wherein the III-nitride diode device further comprises:

2. The ill-nitride diode device of claim 1, wherein the first electrode comprises:

and the first part is electrically connected with the second part.

3. The group III nitride diode device of claim 2, wherein: the first type of electrical contact comprises an ohmic contact and the second type of electrical contact comprises an ohmic contact or a schottky contact.

4. The group III nitride diode device of claim 1, wherein: any two adjacent third semiconductors are electrically isolated by a high-resistance material; and/or the plurality of third semiconductors are electrically isolated from the second electrode by a high-resistance material.

5. The group III nitride diode device of claim 4, wherein:

the high-resistance material is formed by converting a continuous first region of a third semiconductor layer, and a plurality of third semiconductors are distributed in a second region of the third semiconductor layer;

or, a plurality of the third semiconductors are formed by converting a continuous second region of the high-resistance material layer, and the high-resistance material is distributed in the first region of the high-resistance material layer;

preferably, the third semiconductor is a p-type semiconductor; preferably, the material of the third semiconductor comprises a p-type wide bandgap semiconductor; more preferably, the p-type wide bandgap semiconductor comprises a p-type group iii nitride; more preferably, the p-type group iii nitride comprises p-type GaN, p-type AlGaN, p-type InGaN, or p-type InN; more preferably, the p-type wide bandgap semiconductor comprises p-NiO;

preferably, the high-resistance material is high-resistance GaN, high-resistance AlGaN or high-resistance Ga ₂ O ₃ High resistance InGaN, or high resistance InN.

6. The group III nitride diode device of claim 4, wherein:

the plurality of third semiconductors are distributed in a continuous third semiconductor layer, a fourth semiconductor is further arranged on a region, located between any two adjacent third semiconductors, of the third semiconductor layer, and the fourth semiconductor and the third semiconductor layer are matched to form a pn junction;

preferably, the fourth semiconductor is an n-type semiconductor, and the material of the n-type semiconductor includes n-type GaN and n-type Ga ₂ O ₃ N-type In ₂ O ₃ N-type InGaN, or n-type InN.

7. The group III nitride diode device of claim 1, wherein: the first electrode and the second electrode are respectively an anode and a cathode.

8. The group III nitride diode device of claim 1, wherein: the first semiconductor, the second semiconductor and the third semiconductor are sequentially stacked, a first part of the first electrode and the second electrode are arranged on the second semiconductor, and a second part of the first electrode is arranged on the first part and the plurality of third semiconductors;

preferably, the second portion of the first electrode completely masks the plurality of third semiconductors;

preferably, the plurality of third semiconductors are sequentially arranged at intervals along a designated direction, wherein two ends of any one of the third semiconductors point to the first part of the first electrode and the second electrode respectively;

preferably, the width of the third semiconductor is not less than 2 μm, the length of the third semiconductor is 10nm-10 μm, and the distance between two adjacent third semiconductors is 1nm-10 μm;

preferably, the thickness of the third semiconductor is 10nm to 1 μm;

preferably, the materials of the first semiconductor and the second semiconductor are selected from group III nitrides; preferably, the material of the first semiconductor includes GaN; preferably, the secondThe semiconductor material comprises Al _x Ga _(1-x) N, alInGaN or In _x Al _(1-x) N，0＜x≤1。

9. The group III nitride diode device of claim 1, wherein: the ill-nitride diode device also includes a field plate.

10. A method of fabricating a group III nitride diode device, comprising:

the manufacturing method is characterized by further comprising the following steps:

11. The manufacturing method according to claim 10, characterized by specifically comprising:

12. The method of manufacturing according to claim 11, further comprising: the high-resistance material electrically isolates the third semiconductors from the second electrode.

13. The method of manufacturing according to claim 11, wherein: the method for carrying out the conversion treatment comprises any one or combination of H ion implantation, H plasma treatment, H doping annealing, N ion implantation, F ion implantation, ar ion implantation, fe ion implantation and O plasma treatment.

14. The manufacturing method according to claim 10, characterized by specifically comprising:

sequentially forming a first semiconductor and a second semiconductor;

15. The manufacturing method according to claim 10, characterized by specifically comprising:

sequentially forming a first semiconductor and a second semiconductor;

and epitaxially growing a plurality of third semiconductors and high-resistance materials on the second semiconductor upper area, and electrically isolating any two adjacent third semiconductors from each other by the high-resistance materials.

16. The manufacturing method according to claim 10, characterized by specifically comprising:

growing a fourth semiconductor on a region of the third semiconductor layer between any two adjacent third semiconductors, and enabling the fourth semiconductor and the third semiconductor layer to be matched to form a pn junction;

17. A group III nitride semiconductor device comprising:

characterized in that the group III nitride semiconductor device further comprises:

a plurality of third semiconductors, wherein the plurality of third semiconductors are matched with the heterojunction, any two adjacent third semiconductors are arranged at intervals, each third semiconductor can exhaust the two-dimensional electron gas of the part positioned below the third semiconductor, and the plurality of third semiconductors are respectively in electrical contact with the first electrode;

18. A group III nitride semiconductor device according to claim 17, characterized by further comprising a fifth semiconductor which is provided between the gate and the heterojunction, and which is capable of depleting the two-dimensional electron gas of a portion located therebelow;

preferably, the fifth semiconductor is electrically isolated from the source and the drain by a high-resistance material, the high-resistance material is formed by converting a first region of a continuous fifth semiconductor layer, and the fifth semiconductor is distributed in a second region of the fifth semiconductor layer; or the fifth semiconductor is formed by converting a continuous second region of the high-resistance material layer, and the high-resistance material is distributed in the first region of the high-resistance material layer.

19. The group III nitride semiconductor device according to claim 17, characterized in that: the first electrode includes:

and the first part is electrically connected with the second part.

20. The group III nitride semiconductor device according to claim 19, wherein: the second portion of the first electrode is partially disposed between the source and drain electrodes.

21. The group III nitride semiconductor device according to claim 19, wherein: the first type of electrical contact comprises an ohmic contact and the second type of electrical contact comprises an ohmic contact or a schottky contact.

22. The group III nitride semiconductor device according to claim 17, characterized in that: any two adjacent third semiconductors are electrically isolated by a high-resistance material; and/or the third semiconductors and the second electrodes are electrically isolated by high-resistance materials.

23. The group III nitride semiconductor device according to claim 19, wherein:

the high-resistance material is formed by converting a continuous first region of a third semiconductor layer, and a plurality of third semiconductors are distributed in a second region of the third semiconductor layer; or, the plurality of third semiconductors are formed by converting a continuous second region of the high-resistance material layer, and the high-resistance material is distributed in the first region of the high-resistance material layer.

24. The group III nitride semiconductor device according to claim 19, wherein: the plurality of third semiconductors are distributed in a continuous third semiconductor layer, a fourth semiconductor is further arranged on a region, located between any two adjacent third semiconductors, of the third semiconductor layer, and the fourth semiconductor and the third semiconductor layer are matched to form a pn junction;

preferably, the third semiconductor and the fifth semiconductor are p-type semiconductors; preferably, the third semiconductor and the fifth semiconductor are made of p-type wide bandgap semiconductors; more preferably, the p-type wide bandgap semiconductor comprises a p-type group iii nitride; more preferably, the p-type group iii nitride comprises p-type GaN, p-type AlGaN, p-type InGaN, or p-type InN; more preferably, the p-type wide bandgap semiconductor comprises p-NiO;

25. The group III nitride semiconductor device according to claim 17, characterized in that: the first electrode and the second electrode are respectively an anode and a cathode.

26. The group III nitride semiconductor device according to claim 17, characterized in that: the first semiconductor, the second semiconductor and the third semiconductor are sequentially stacked, a first part of the first electrode and the second electrode are arranged on the second semiconductor, and a second part of the first electrode is arranged on the first part and the plurality of third semiconductors;

preferably, the plurality of third semiconductors are sequentially arranged at intervals along a designated direction, wherein both ends of any one of the third semiconductors point to the first portion of the first electrode and the second electrode, respectively.