CN115799173B

CN115799173B - Semiconductor structure and manufacturing method thereof

Info

Publication number: CN115799173B
Application number: CN202310102361.6A
Authority: CN
Inventors: 吴润平; 陈美卉; 朱磊
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Xinqiao Storage Technology Co ltd
Priority date: 2023-02-13
Filing date: 2023-02-13
Publication date: 2023-04-11
Anticipated expiration: 2043-02-13
Also published as: CN115799173A

Abstract

The embodiment of the disclosure discloses a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure comprises: a substrate including a first insulating layer; a first trench in the first insulating layer and defining a dummy active region extending in a first direction in the first insulating layer; a second insulating layer filling the first trench; a second trench penetrating the dummy active region and the second insulating layer and extending in a second direction crossing the first direction, including a first sub-trench in the dummy active region and a second sub-trench in the second insulating layer, a bottom surface of the first sub-trench being higher than a bottom surface of the second sub-trench; the transistor comprises a channel material layer, a gate dielectric layer and a gate conducting layer, wherein the channel material layer covers the first sub-groove along with the shape, the top surfaces of the pseudo active regions, which are positioned at two sides of the first sub-groove, and the side walls of the pseudo active regions, which are exposed by the second sub-groove, at least part of the gate dielectric layer and the gate conducting layer are positioned in the first groove, and the channel material layer, which is positioned on the side walls of the pseudo active regions, which are exposed by the second sub-groove, is covered by the gate dielectric layer and the gate conducting layer.

Description

Semiconductor structure and manufacturing method thereof

Technical Field

The present disclosure relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for manufacturing the same.

Background

Semiconductor structures, such as Dynamic Random Access Memories (DRAMs), typically include a substrate, transistors located on the substrate, a word line structure buried in the substrate for controlling the switching of the transistors, and a capacitor structure for storing data. The material of the substrate typically includes a semiconductor material such as silicon, and the source, drain, and channel regions of the transistor are formed by performing a doping process on the substrate.

As semiconductor structures continue to be miniaturized and highly integrated, further reduction in the size of word lines leads to increased leakage current, degrading current drivability of transistors, thereby degrading the performance of semiconductor structures.

Disclosure of Invention

An embodiment of the present disclosure provides a semiconductor structure, including:

a substrate comprising a first insulating layer;

a first trench located within the first insulating layer and defining a dummy active region extending in a first direction within the first insulating layer;

a second insulating layer filling the first trench;

a second trench passing through the dummy active region and the second insulating layer and extending in a second direction, the second trench including a first sub-trench in the dummy active region and a second sub-trench in the second insulating layer, a bottom surface of the first sub-trench being higher than a bottom surface of the second sub-trench, the second direction crossing the first direction;

the transistor comprises a channel material layer, a gate dielectric layer and a gate conducting layer, wherein the channel material layer covers the first sub-groove along the shape, the top surfaces of the pseudo active regions, which are positioned on two sides of the first sub-groove, and the side walls, exposed by the second sub-groove, of the pseudo active regions, the gate dielectric layer and the gate conducting layer are at least partially positioned in the second groove, and the channel material layer, which is positioned on the side walls, exposed by the second sub-groove, of the pseudo active regions, is covered by the gate dielectric layer and the gate conducting layer.

In some embodiments, the material of the channel material layer includes at least one of indium oxide, tin oxide, an In-Zn based oxide, a Sn-Zn based oxide, an Al-Zn based oxide, an In-Ga-Zn based oxide, an In-Al-Zn based oxide, an In-Sn-Zn based oxide, a Sn-Ga-Zn based oxide, an Al-Ga-Zn based oxide, a Sn-Al-Zn based oxide, or a combination thereof.

In some embodiments, the etching selection ratio of the material of the dummy active region to the material of the second insulating layer ranges from 1.2 to 1.

In some embodiments, the material of the dummy active region is an oxide, and the material of the second insulating layer is a nitride.

In some embodiments, the dummy active region is an island structure, and two transistors are formed based on one dummy active region; alternatively, the dummy active region may be a wall-like structure continuously extending in the first direction, and two or more transistors may be formed based on one dummy active region.

In some embodiments, the gate dielectric layer and the gate conductive layer are located in the second trench, the gate dielectric layer covers at least a surface of the channel material layer located in the second trench, and the gate conductive layer covers at least a surface of the gate dielectric layer and fills the second trench.

In some embodiments, the gate dielectric layer includes a first sub-layer and a second sub-layer, the first sub-layer covers at least a surface of the channel material layer located in the second trench, the second sub-layer covers the channel material layer and a portion of a top surface of the second insulating layer located on two sides of the second trench, the gate conductive layer includes a first sub-portion and a second sub-portion, the first sub-portion covers at least a surface of the first sub-layer and fills the second trench, and the second sub-portion covers the second sub-layer and the first sub-portion.

The embodiment of the present disclosure further provides a method for manufacturing a semiconductor structure, including:

providing a substrate comprising a first insulating layer;

etching the first insulating layer to form a pseudo active region extending along a first direction and a first groove defining the pseudo active region;

forming a second insulating layer filling the first trench;

etching the dummy active region and the second insulating layer to form a second trench extending along a second direction, wherein the second trench includes a first sub-trench located in the dummy active region and a second sub-trench located in the second insulating layer, a bottom surface of the first sub-trench is higher than a bottom surface of the second sub-trench, and the second direction crosses the first direction;

and forming a transistor, wherein the transistor comprises a channel material layer, a gate dielectric layer and a gate conducting layer, the channel material layer covers the first sub-groove, the top surfaces of the pseudo active regions, which are positioned at two sides of the first sub-groove, and the side walls of the pseudo active regions, which are exposed by the second sub-groove, in a shape-following manner, the gate dielectric layer and the gate conducting layer are at least partially positioned in the second groove, and the channel material layer positioned on the side walls of the pseudo active regions, which are exposed by the second sub-groove, is covered by the gate dielectric layer and the gate conducting layer.

In some embodiments, forming a second trench within the substrate includes:

and etching the pseudo active region and the second insulating layer in a one-step etching process to form the second groove, wherein the bottom surface of the first sub-groove is higher than the bottom surface of the second sub-groove by controlling the etching selection ratio of the pseudo active region to the second insulating layer.

In some embodiments, an etching selection ratio of the dummy active region to the second insulating layer ranges from 1.2 to 1.

In some embodiments, etching the first insulating layer to form a dummy active region extending in a first direction and a first trench defining the dummy active region includes:

forming a first mask layer on the substrate, wherein the first mask layer comprises a plurality of wall-shaped mask patterns continuously extending along the first direction;

and etching the first insulating layer by taking the first mask layer as a mask to form a wall-shaped structure continuously extending along the first direction, wherein the wall-shaped structure is defined as the pseudo active region, and a gap between the adjacent pseudo active regions is defined as a first groove.

forming a first mask layer on the substrate, wherein the first mask layer comprises a plurality of wall-shaped mask patterns which continuously extend along the first direction;

etching the first insulating layer by taking the first mask layer as a mask to form a wall-shaped structure continuously extending along the first direction;

and etching the wall-shaped structure, cutting the wall-shaped structure into a plurality of island-shaped structures, defining the island-shaped structures as pseudo active regions, and defining gaps among the pseudo active regions as first grooves.

In some embodiments, forming the channel material layer comprises:

conformally forming an initial channel material layer;

forming a third mask layer by using the same photomask for preparing the first mask layer, wherein the third mask layer comprises a plurality of wall-shaped mask patterns continuously extending along the first direction;

forming a third insulating layer, wherein the third insulating layer covers the side wall of the wall-shaped mask pattern;

etching the initial channel material layer by taking the third insulating layer and the third mask layer as masks to form a plurality of discrete strip channel material layers;

and breaking the strip-shaped channel material layer into a plurality of discrete island-shaped channel material layers, wherein the island-shaped channel material layers are defined as channel material layers.

forming a second mask layer on the substrate, wherein the second mask layer comprises a plurality of island-shaped mask patterns;

and etching the first insulating layer by taking the second mask layer as a mask to form a plurality of island-shaped structures, wherein the island-shaped structures are defined as the pseudo active regions, and gaps among the pseudo active regions are defined as first grooves.

In some embodiments, forming the channel material layer comprises:

conformally forming an initial channel material layer;

forming a fourth mask layer by using the same photomask for preparing the second mask layer, wherein the fourth mask layer comprises a plurality of island-shaped mask patterns;

forming a fourth insulating layer covering sidewalls of the island-shaped mask pattern;

and etching the initial channel material layer by taking the fourth insulating layer and the fourth mask layer as masks to form a plurality of discrete island-shaped channel material layers, wherein the island-shaped channel material layers are defined as channel material layers.

In some embodiments, forming the gate dielectric layer and the gate conductive layer includes:

forming a gate dielectric material layer in a shape, removing the gate dielectric material layer outside the second groove, and defining the gate dielectric material layer remained in the second groove as a gate dielectric layer;

forming a gate conductive material layer which covers the top surface of the second insulating layer and the surface of the channel material layer and fills the second groove;

and removing the gate conductive material layer outside the second groove, wherein the gate conductive material layer remained in the second groove is defined as a gate conductive layer.

In some embodiments, forming the gate dielectric layer and the gate conductive layer comprises:

forming a gate dielectric material layer in a shape, removing part of the gate dielectric material layer outside the second groove, defining the gate dielectric material layer remained in the second groove as a first sub-layer of the gate dielectric layer, and defining the channel material layer remained on two sides of the second groove and the gate dielectric material layer on the second insulating layer as a second sub-layer of the gate dielectric layer;

forming a gate conductive material layer which covers the channel material layer and the top surface of the second insulating layer and fills the second groove;

and etching the gate conductive material layer to form a plurality of gate conductive layers extending along the second direction, wherein each gate conductive layer comprises a first sub-portion and a second sub-portion, the first sub-portion covers the first sub-layer and fills the second groove, and the second sub-portion covers the first sub-portion and the second sub-layer.

The embodiment of the present disclosure provides a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure includes: a substrate including a first insulating layer; a first trench in the first insulating layer and defining a dummy active region extending in a first direction in the first insulating layer; a second insulating layer filling the first trench; a second trench passing through the dummy active region and the second insulating layer and extending in a second direction, the second trench including a first sub-trench in the dummy active region and a second sub-trench in the second insulating layer, a bottom surface of the first sub-trench being higher than a bottom surface of the second sub-trench, the second direction crossing the first direction; the transistor comprises a channel material layer, a gate dielectric layer and a gate conducting layer, wherein the channel material layer covers the first subslot in a shape-following mode, the top surfaces of the pseudo active regions, which are located on two sides of the first subslot, and the side walls of the pseudo active regions, which are exposed by the second subslot, are at least partially located in the first groove, and the channel material layer, which is located on the side walls of the pseudo active regions, which are exposed by the second subslot, is covered by the gate dielectric layer and the gate conducting layer. In the embodiment of the disclosure, the second trench includes the first sub-trench and the second sub-trench, and the bottom surface of the first sub-trench is higher than the bottom surface of the second sub-trench, so that the second sub-trench exposes a part of the sidewall of the dummy active region, and the channel material layer and the gate conductive layer of the transistor cover the sidewall of the dummy active region exposed by the second sub-trench, so that the leakage phenomenon can be effectively alleviated or eliminated, and the on-off current ratio and the current drivability of the transistor can be improved, thereby improving the driving capability of the gate conductive layer to the transistor, reducing the power consumption, and improving the performance of the semiconductor structure. In addition, compared with the case of using a semiconductor material such as silicon as a substrate, the substrate in the embodiment of the disclosure includes the first insulating layer, so that the manufacturing process of the semiconductor structure is more flexible, the gate conductive layer is allowed to be formed after the capacitor structure is formed, and a leakage phenomenon caused by the substrate made of the semiconductor material such as silicon between the transistors can be avoided.

The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features and advantages of the disclosure will be apparent from the description and drawings, and from the claims.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.

Fig. 1a is a schematic top view of a semiconductor structure provided by an embodiment of the present disclosure;

FIG. 1B isbase:Sub>A schematic cross-sectional view taken along lines A-A ', B-B' of FIG. 1base:Sub>A;

fig. 2a is a schematic top view of a semiconductor structure according to another embodiment of the present disclosure;

FIG. 2B isbase:Sub>A schematic cross-sectional view taken along lines A-A ', B-B' of FIG. 2base:Sub>A;

fig. 3a is a schematic top view of a semiconductor structure according to yet another embodiment of the present disclosure;

FIG. 3B isbase:Sub>A schematic cross-sectional view taken along lines A-A ', B-B' of FIG. 3base:Sub>A;

fig. 4 is a block flow diagram of a method of fabricating a semiconductor structure provided by an embodiment of the present disclosure;

fig. 5a is a first process flow diagram of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

FIG. 5b is a second process flow diagram of a method of fabricating a semiconductor structure according to an embodiment of the present disclosure;

fig. 6a is a third process flow diagram of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

fig. 6b is a fourth process flow diagram of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

fig. 7a is a process flow diagram of a method for fabricating a semiconductor structure according to an embodiment of the disclosure;

fig. 7b is a sixth process flow diagram of a method of fabricating a semiconductor structure according to an embodiment of the present disclosure;

fig. 8a is a process flow diagram seven of a method of fabricating a semiconductor structure provided by an embodiment of the present disclosure;

fig. 8b is a process flow diagram eight of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

fig. 9a is a process flow diagram nine of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

fig. 9b is a process flow diagram ten of a method of fabricating a semiconductor structure provided by an embodiment of the present disclosure;

fig. 10a is an eleventh process flow diagram of a method of fabricating a semiconductor structure according to an embodiment of the present disclosure;

fig. 10b is a process flow diagram twelve of a method of fabricating a semiconductor structure according to an embodiment of the present disclosure;

fig. 11a is a thirteenth process flow diagram of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

fig. 11b is a fourteenth process flow diagram of a method for fabricating a semiconductor structure according to an embodiment of the disclosure;

fig. 12a is a process flow diagram fifteen of a method of fabricating a semiconductor structure provided in an embodiment of the disclosure;

fig. 12b is a process flow diagram sixteen of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

fig. 13a is a process flow diagram seventeenth of a method of fabricating a semiconductor structure according to an embodiment of the present disclosure;

fig. 13b is a process flow chart eighteen of a method of fabricating a semiconductor structure provided by an embodiment of the present disclosure;

fig. 14a is a nineteenth process flow diagram of a method of fabricating a semiconductor structure according to an embodiment of the disclosure;

fig. 14b is a process flow diagram twenty of a method of fabricating a semiconductor structure provided by an embodiment of the present disclosure;

fig. 15a is a process flow diagram twenty-one of a method for manufacturing a semiconductor structure according to an embodiment of the disclosure;

fig. 15b is a process flow diagram twenty-two of a method of fabricating a semiconductor structure provided by an embodiment of the present disclosure;

fig. 16a is a twenty-third process flow diagram of a method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

fig. 16b is a twenty-four process flow diagram of a method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

fig. 17a is a twenty-five process flow diagram of a method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

fig. 17b is a twenty-sixth process flow diagram of a method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

fig. 18a is a twenty-seventh process flow diagram of a method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

fig. 18b is a process flow diagram twenty-eight of a method of fabricating a semiconductor structure according to another embodiment of the present disclosure;

fig. 19a is a process flow diagram of a method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

fig. 19b is a thirty-third process flow diagram of a method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

fig. 20a is a thirty-one process flow diagram of a method of fabricating a semiconductor structure according to another embodiment of the present disclosure;

fig. 20b is a process flow chart thirty-two of a method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

fig. 21a is a thirty-three process flow diagram of a method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

fig. 21b is a thirty-four process flow diagram of a method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

fig. 22a is a thirty-five process flow diagram of a method of fabricating a semiconductor structure according to another embodiment of the present disclosure;

fig. 22b is a thirty-six process flow diagram of a method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

fig. 23a is a thirty-seven process flow diagram of a method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

fig. 23b is a thirty-eight process flow diagram of a method for fabricating a semiconductor structure according to another embodiment of the present disclosure;

fig. 24a is a thirty-nine process flow diagram of a method of fabricating a semiconductor structure according to yet another embodiment of the present disclosure;

figure 24b is a process flow diagram forty of a method of fabricating a semiconductor structure according to yet another embodiment of the present disclosure;

fig. 25a is a process flow diagram forty one of a method of fabricating a semiconductor structure according to yet another embodiment of the present disclosure;

FIG. 25b is a process flow diagram forty-two of a method of fabricating a semiconductor structure according to yet another embodiment of the present disclosure;

fig. 26a is a process flow diagram forty-three of a method of fabricating a semiconductor structure according to yet another embodiment of the present disclosure;

fig. 26b is a forty-four process flow diagram of a method of fabricating a semiconductor structure according to yet another embodiment of the present disclosure;

fig. 27a is a process flow diagram forty-five of a method of fabricating a semiconductor structure according to yet another embodiment of the present disclosure;

fig. 27b is a forty-six process flow diagram of a method of fabricating a semiconductor structure according to yet another embodiment of the present disclosure;

FIG. 28a is a forty-seven process flow diagram of a method of fabricating a semiconductor structure according to yet another embodiment of the present disclosure;

fig. 28b is a process flow diagram forty-eight of a method of fabricating a semiconductor structure according to yet another embodiment of the present disclosure;

fig. 29a is a process flow diagram forty-nine of a method of fabricating a semiconductor structure according to yet another embodiment of the present disclosure;

FIG. 29b is a process flow diagram fifty of a method of fabricating a semiconductor structure according to yet another embodiment of the present disclosure;

fig. 30a is a process flow diagram fifty one of a method of fabricating a semiconductor structure according to yet another embodiment of the present disclosure;

fig. 30b is a process flow diagram of a method for fabricating a semiconductor structure according to yet another embodiment of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art, that the present disclosure may be practiced without one or more of these specific details. In other instances, well-known features of the art have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.

In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on … …," "adjacent … …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent … …," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. And the discussion of a second element, component, region, layer or section does not necessarily imply that the first element, component, region, layer or section is necessarily present in the disclosure.

Spatial relationship terms such as "under … …", "under … …", "under … …", "over … …", "over", and the like, may be used herein for ease of description to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Semiconductor structures, such as Dynamic Random Access Memories (DRAMs), typically include a substrate, transistors located on the substrate, a wordline structure embedded in the substrate for controlling the switching of the transistors, and a capacitor structure for storing data. The material of the substrate typically includes a semiconductor material such as silicon, and the source, drain, and channel regions of the transistor are formed by performing a doping process on the substrate.

As semiconductor structures continue to be miniaturized and highly integrated, further reduction in the size of word lines leads to increased gate-induced drain leakage current, degrading the current drivability of transistors, thereby degrading the performance of semiconductor structures.

Based on this, the following technical solutions of the embodiments of the present disclosure are proposed. The following detailed description of specific embodiments of the present disclosure is provided in connection with the accompanying drawings. In describing the embodiments of the present disclosure in detail, the drawings are not to be taken as being generally to scale, and are for illustrative purposes only and should not be taken as limiting the scope of the present disclosure.

Fig. 1base:Sub>A isbase:Sub>A schematic top view ofbase:Sub>A semiconductor structure provided by an embodiment of the present disclosure, and fig. 1B isbase:Sub>A schematic cross-sectional structure taken along linesbase:Sub>A-base:Sub>A 'and B-B' of fig. 1base:Sub>A; the semiconductor structure provided by the embodiments of the present disclosure is further described with reference to fig. 1a to 1 b.

As shown, the semiconductor structure includes: a substrate 10, the substrate 10 comprising a first insulating layer 101; a first trench T1 located in the first insulating layer 101 and defining a dummy active region 12 extending in a first direction in the first insulating layer 101; a second insulating layer 13 filling the first trench T1; a second trench T2 passing through the dummy active region 12 and the second insulating layer 13 and extending in a second direction, the second trench T2 including a first sub-groove T21 in the dummy active region 12 and a second sub-groove T22 (see fig. 1 a) in the second insulating layer 13, a bottom surface of the first sub-groove T21 being higher than a bottom surface of the second sub-groove T22 (see fig. 1 b), the second direction crossing the first direction; the transistor T comprises a channel material layer 14, a gate dielectric layer 17 and a gate conducting layer 18, the channel material layer 14 covers the first sub-groove T21, the top surfaces of the dummy active regions 12, located on two sides of the first sub-groove T21, and the side walls SW, exposed by the second sub-groove T22, of the dummy active regions 12, the gate dielectric layer 17 and the gate conducting layer 18 are located at least partially in the second groove T2, and the channel material layer 14, located on the side walls SW, exposed by the second sub-groove T22, of the dummy active regions 12, is covered by the gate dielectric layer 17 and the gate conducting layer 18.

In practical operation, the semiconductor structure provided by the embodiments of the present disclosure may be a three-dimensional dynamic random access memory (3D DRAM), but is not limited thereto, and the semiconductor structure may also be any semiconductor structure having a buried gate. It should be understood that the first trenches T1 and the second insulating layer 13 filling the first trenches T1 may define one or more discrete dummy active regions 12 within the first insulating layer 101; the number of the second trenches T2 may be one or more, and the number of the channel material layers 14 may be one or more.

In the embodiment of the present disclosure, the second trench T2 includes the first sub-trench T21 and the second sub-trench T22, and the bottom surface of the first sub-trench T21 is higher than the bottom surface of the second sub-trench T22, so that the second sub-trench T22 exposes a portion of the sidewall of the dummy active region 12, and the channel material layer 14 and the gate conductive layer 18 of the transistor T cover the sidewall SW of the dummy active region 12 exposed by the second sub-trench T22, so that the leakage phenomenon can be effectively alleviated or eliminated, and the on-off current ratio and the current drivability of the transistor T are improved, thereby improving the driving capability of the gate conductive layer 18 to the transistor T, reducing power consumption, and improving the performance of the semiconductor structure.

In practical operation, the second trench T2 may be formed by etching the dummy active region 12 and the second insulating layer 13 through a one-step etching process, and the feature that the bottom surface of the first sub-trench T21 is higher than the bottom surface of the second sub-trench T22 is obtained by controlling the etching selection ratio of the dummy active region 12 to the second insulating layer 13. For example, the etching selection ratio of the material of the dummy active region 12 (i.e., the material of the first insulating layer 101) to the material of the second insulating layer 13 ranges from 1.2 to 1, such as 1.2: 1.2:1, 2.5, 1, 3:1, and thus, the formation of the first subslot T21 and the second subslot T22 with different depths is facilitated. In some embodiments, the material of the dummy active region 12 is an oxide (e.g., silicon oxide), and the material of the second insulating layer 13 is a nitride (e.g., silicon nitride).

The substrate 10 in the embodiment of the present disclosure includes the first insulating layer 101, which makes the manufacturing process of the semiconductor structure more flexible than using a semiconductor material such as silicon as a substrate, allows the gate conductive layer 18 to be formed after forming the capacitor structure, and can avoid a leakage phenomenon caused by the substrate made of the semiconductor material such as silicon between the transistors T.

In actual operation, the material of the channel material layer 14 includes an oxide semiconductor material. For example, the material of the channel material layer 14 includes at least one of indium oxide, tin oxide, in-Zn-based oxide, sn-Zn-based oxide, al-Zn-based oxide, in-Ga-Zn-based oxide, in-Al-Zn-based oxide, in-Sn-Zn-based oxide, sn-Ga-Zn-based oxide, al-Ga-Zn-based oxide, sn-Al-Zn-based oxide, or a combination thereof.

But is not limited thereto, the material of the channel material layer 14 may further include an In-Hf-Zn based oxide, an In-La-Zn based oxide, an In-Ce-Zn based oxide, an In-Pr-Zn based oxide, an In-Nd-Zn based oxide, an In-Sm-Zn based oxide, an In-Eu-Zn based oxide, an In-Gd-Zn based oxide, an In-Tb-Zn based oxide, an In-Dy-Zn based oxide, an In-Ho-Zn based oxide, an In-Er-Zn based oxide, an In-Tm-Zn based oxide, an In-Yb-Zn based oxide, an In-Lu-Zn based oxide; and quaternary metal oxides such as at least one of In-Sn-Ga-Zn based oxides, in-Hf-Ga-Zn based oxides, in-Al-Ga-Zn based oxides, in-Sn-Al-Zn based oxides, in-Sn-Hf-Zn based oxides, and In-Hf-Al-Zn based oxides.

The oxide semiconductor material is used as the material of the channel material layer 14, and the oxide semiconductor material is used as a channel for transmitting charges, so that the electric leakage phenomenon can be further effectively relieved or eliminated, and the on-off current ratio and the current drivability of the transistor T are improved, so that the driving capability of the gate conductive layer 18 to the transistor T is further improved, the power consumption is reduced, and the performance of a semiconductor structure is improved.

Referring to fig. 1a and fig. 1b, the gate dielectric layer 17 and the gate conductive layer 18 are located in the second trench T2, the gate dielectric layer 17 at least covers the surface of the channel material layer 14 located in the second trench T2, and the gate conductive layer 18 at least covers the surface of the gate dielectric layer 17 and fills the second trench T2; the channel material layer 14 on the sidewalls SW of the dummy active region 12 exposed by the second sub-groove T22 and the channel material layer 14 on the bottom surface and at least a portion of the sidewalls of the first sub-groove T21 are covered with the gate conductive layer 18. Therefore, the leakage phenomenon can be effectively relieved or eliminated, the on-off current ratio and the current drivability of the transistor T are improved, the driving capability of the gate conducting layer 18 on the transistor T is improved, the power consumption is reduced, and the performance of the semiconductor structure is improved. In addition, the depth of the first sub-groove T21 is smaller than that of the second sub-groove T22, and the gate conductive layer 18 located in the first sub-groove T21 has a smaller height, so that the transistor T is isolated by the second insulating layer 13 more effectively.

In the embodiment shown in fig. 1a and 1b, the gate dielectric layer 17 covers not only the surface of the channel material layer 14 located in the second trench T2, but also the surface of the second trench T2 not covered by the channel material layer 14. It should be understood that in some embodiments, the gate dielectric layer 17 may also cover only the surface of the channel material layer 14 located in the second trench T2.

The portion of the channel material layer 14 covered by the gate conductive layer 18 constitutes a channel region c of the transistor T, and the portions located on both sides of the gate conductive layer 18 and not covered by the gate conductive layer 18 constitute a source d1 and a drain d2 of the transistor T, respectively, so that 2 transistors T having a common source d1 can be formed based on one channel material layer 14.

With continued reference to fig. 1a and fig. 1b, the dummy active regions 12 are wall-shaped structures continuously extending along the first direction, the number of the first trenches T1 and the number of the dummy active regions 12 are multiple, and the multiple first trenches T1 and the multiple dummy active regions 12 are alternately arranged along the second direction; since the plurality of channel material layers 14 are formed on one dummy active region 12 and two transistors T are formed on one channel material layer 14, when the dummy active region 12 has a wall-shaped structure continuously extending in the first direction, two or more transistors T can be formed based on one dummy active region 12. In this embodiment, the orthographic projection of the channel material layer 14 on the plane of the substrate 10 extends along the first direction, and the dimension of the channel material layer 14 in the second direction is larger than that of the dummy active region 12 to ensure that the channel material layer 14 can cover the sidewalls SW of the dummy active region 12 exposed by the second sub-grooves T22. Here, forming the dummy active region 12 having the wall-like structure continuously extending in the first direction can simplify the formation process of the dummy active region 12.

Without limitation, in some other embodiments, referring to fig. 2a and 2b, the dummy active regions 12 are island-shaped structures, and the gaps between the dummy active regions 12 form the first trenches T1; a channel material layer 14 is formed on one dummy active region 12, and thus, when the dummy active region 12 is an island-shaped structure, two transistors T are formed based on one dummy active region 12. In this embodiment, the orthographic projection of the dummy active region 12 on the plane of the substrate 10 falls within the orthographic projection of the channel material layer 14 on the plane of the substrate 10 to ensure that the channel material layer 14 covers the sidewalls SW of the dummy active region 12 exposed by the second sub-trenches T22. In practical operation, the dummy active regions 12 having island structures may be formed by cutting off the wall-like structures continuously extending along the first direction, so that the plurality of dummy active regions 12 having island structures are also spaced apart by the second insulating layer 13 in the first direction, thereby improving the isolation effect between the transistors T.

The gate conductive layer 18 and the gate dielectric layer 17 shown in fig. 1a to 1b are both located within the second trench T2. Without being limited thereto, as shown in fig. 3a and 3b, in a further embodiment of the present disclosure, the gate dielectric layer 17 includes a first sub-layer 171 and a second sub-layer 172, the first sub-layer 171 covers at least a surface of the channel material layer 14 located in the second trench T2, the second sub-layer 172 covers the channel material layer 14 and a portion of a top surface of the second insulating layer 13 located on both sides of the second trench T2, the gate conductive layer 18 includes a first sub-portion 181 and a second sub-portion 182, the first sub-portion 181 covers at least a surface of the first sub-layer 171 and fills the second trench T2, and the second sub-portion 182 covers the second sub-layer 172 and the first sub-portion 181, so that a portion of the channel material layer 14 located in the second trench T2 and on both sides of the first sub-trench T21 forms a channel layer c, which further increases the length of the channel layer c and improves performance of the transistor T.

Here, the material of the gate conductive layer 18 includes tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), a metal alloy, or any combination thereof (e.g., a stack of TiN and W). The material of the gate dielectric layer 17 may be a high dielectric constant material, and may be, for example, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide, or barium strontium titanate. The embodiment of the present disclosure uses a high dielectric constant material as the material of the gate dielectric layer 17, which can further improve the current drivability of the transistor T.

It should be understood that although fig. 3a to 3b illustrate the first sub-layer 171 covering both the surface of the channel material layer 14 located within the second trench T2 and the surface of the second trench T2 not covered by the channel material layer 14, in some other embodiments, the first sub-layer 171 may only cover the surface of the channel material layer 14 located within the second trench T2.

The embodiment of the present disclosure further provides a method for manufacturing a semiconductor structure, as shown in fig. 4, the method includes the following steps:

step S101, providing a substrate, wherein the substrate comprises a first insulating layer;

step S102, etching the first insulating layer to form a pseudo active region extending along a first direction and a first groove defining the pseudo active region;

step S103, forming a second insulating layer for filling the first groove;

step S104, etching the pseudo active region and the second insulating layer to form a second groove extending along a second direction, wherein the second groove comprises a first sub-groove located in the pseudo active region and a second sub-groove located in the second insulating layer, the bottom surface of the first sub-groove is higher than that of the second sub-groove, and the second direction is crossed with the first direction;

step S105, forming a transistor, wherein the transistor comprises a channel material layer, a gate dielectric layer and a gate conducting layer, the channel material layer covers the first sub-groove along with the shape, the top surface of the pseudo active region, which is positioned at two sides of the first sub-groove, and the side wall of the pseudo active region, which is exposed by the second sub-groove, at least part of the gate dielectric layer and the gate conducting layer is positioned in the first groove, and the channel material layer, which is positioned on the side wall of the pseudo active region, which is exposed by the second sub-groove, is covered by the gate dielectric layer and the gate conducting layer.

Fig. 5a to 15b are process flow diagrams of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure; fig. 16a to 23b are process flow diagrams of a method for fabricating a semiconductor structure according to another embodiment of the present disclosure; fig. 24a to 27b are process flow diagrams of a method for fabricating a semiconductor structure according to another embodiment of the present disclosure; fig. 28a to 30b are process flow diagrams of a method for fabricating a semiconductor structure according to still another embodiment of the present disclosure. In which fig. 5B, fig. 6B, fig. 7B, fig. 8B, fig. 9B, fig. 10B, fig. 11B, fig. 12B, fig. 13B, fig. 14B, fig. 15B, fig. 16B, fig. 17B, fig. 18B, fig. 19B, fig. 20B, fig. 21B, fig. 22B, fig. 23B, fig. 24B, fig. 25B, fig. 26B, fig. 27B, fig. 28B, fig. 29B, fig. 30B are schematic views taken along the linesbase:Sub>A-B' in fig. 5base:Sub>A, fig. 6base:Sub>A, fig. 7base:Sub>A, fig. 8base:Sub>A, fig. 9base:Sub>A, fig. 10base:Sub>A, fig. 11base:Sub>A, fig. 12base:Sub>A, fig. 13base:Sub>A, fig. 14base:Sub>A, fig. 15base:Sub>A, fig. 16base:Sub>A, fig. 17base:Sub>A, fig. 18base:Sub>A, fig. 19base:Sub>A, fig. 20base:Sub>A, fig. 21base:Sub>A, fig. 22base:Sub>A, fig. 23base:Sub>A, fig. 24base:Sub>A, fig. 25base:Sub>A, fig. 26base:Sub>A, fig. 27base:Sub>A, fig. 28base:Sub>A, fig. 29base:Sub>A, fig. 30base:Sub>A. The following structure fig. 5a to fig. 30b further illustrate the method for manufacturing the semiconductor structure according to the embodiment of the present disclosure in detail.

First, step S101 is performed, as shown in fig. 5a to 5b, providing a substrate 10, the substrate 10 comprising a first insulating layer 101.

A gate conductive layer 18 (see fig. 1a to 1 b) and a transistor T (see fig. 1a to 1 b) may be subsequently formed on the substrate 10. The substrate 10 in the embodiment of the present disclosure includes the first insulating layer 101, which makes the manufacturing process of the semiconductor structure more flexible than using a semiconductor material such as silicon as a substrate, allows the gate conductive layer 18 (see fig. 1a to 1 b) to be formed after forming the capacitor structure, and can avoid a leakage phenomenon caused by the substrate made of the semiconductor material such as silicon between the transistors T (see fig. 1a to 1 b).

Next, step S102 is performed, as shown in fig. 6a to 7b, the first insulating layer 101 is etched to form the dummy active regions 12 extending along the first direction and the first trenches T1 defining the dummy active regions 12.

For example, etching the first insulating layer 101 to form the dummy active region 12 extending in the first direction and the first trench T1 defining the dummy active region 12 includes:

forming a first mask layer 11 on a substrate 10, the first mask layer 11 including a plurality of wall-shaped mask patterns 111 continuously extending in a first direction;

etching the first insulating layer 101 by using the first mask layer 11 as a mask to form a wall-shaped structure continuously extending along the first direction

Wall-shaped structure>

Defined as dummy active regions 12, and a gap between adjacent dummy active regions 12 is defined as a first trench T1.

Here, the forming process of the first mask layer 11 includes, but is not limited to, a self-aligned double patterning process (SADP), a self-aligned quadruple patterning process (SAQP). In the embodiment of the present disclosure, the dummy active region 12 having the wall-like structure is formed by a one-step etching process, which simplifies the process.

As shown in the figure, the number of the dummy active regions 12 and the first trenches T1 is plural, and the plurality of dummy active regions 12 and the plurality of first trenches T1 are alternately arranged along the second direction.

Next, step S103 is performed, as shown in fig. 8a to 8b, to form the second insulating layer 13 filling the first trench T1.

The second insulating layer 13 may be formed in the first trench T1 by using a Chemical Vapor Deposition (CVD), a Plasma Enhanced Chemical Vapor Deposition (PECVD), a Physical Vapor Deposition (PVD), an Atomic Layer Deposition (ALD), or the like, in combination with a planarization process (e.g., chemical mechanical polishing, CMP). The second insulating layer 13 serves as a good isolation for the subsequently formed transistor T (see fig. 1a to 1 b).

Next, step S104 is performed, as shown in fig. 9a to 9b, the dummy active region 12 and the second insulating layer 13 are etched to form a second trench T2 extending along a second direction, wherein the second trench T2 includes a first sub-trench T21 located in the dummy active region 12 and a second sub-trench T22 located in the second insulating layer 13, a bottom surface of the first sub-trench T21 is higher than a bottom surface of the second sub-trench T22, and the second direction crosses the first direction.

For example, forming a second trench T2 in the substrate 10 includes: and etching the pseudo active region 12 and the second insulating layer 13 in a one-step etching process to form a second trench T2, and controlling the etching selection ratio of the pseudo active region 12 to the second insulating layer 13 to enable the bottom surface of the first sub-trench T21 to be higher than the bottom surface of the second sub-trench T22. In the embodiment of the present disclosure, the bottom surface of the first sub-groove T21 is higher than the bottom surface of the second sub-groove T22, so that the second sub-groove T22 exposes a portion of the sidewall SW of the dummy active region 12.

In an embodiment, the etching selection ratio of the material of the dummy active region 12 (i.e. the material of the first insulating layer 101) to the material of the second insulating layer 13 is in a range from 1.2 to 1, for example, 1.2: 1.2:1, 2.5, 1, 3:1, so that the bottom surface of the first sub-groove T21 is higher than the bottom surface of the second sub-groove T22, and the control of the above ratio range can prevent the height difference between the bottom surface of the first sub-groove T21 and the bottom surface of the second sub-groove T22 from being too large or too small, so as to ensure that the leakage phenomenon is better alleviated or eliminated. In some embodiments, the material of the dummy active region 12 is an oxide (e.g., silicon oxide), and the material of the second insulating layer 13 is a nitride (e.g., silicon nitride).

Next, step S105 is performed, as shown in fig. 10a to 15b and fig. 1a to 1b, a transistor T is formed, the transistor T includes a channel material layer 14, a gate dielectric layer 17 and a gate conductive layer 18, the channel material layer 14 conformally covers the first sub-groove T21, the top surface of the dummy active region 12 on both sides of the first sub-groove T21 and the sidewall SW of the dummy active region 12 exposed by the second sub-groove T22, the gate dielectric layer 17 and the gate conductive layer 18 are at least partially located in the second trench T2, and the channel material layer 14 on the sidewall SW of the dummy active region 12 exposed by the second sub-groove T22 is covered by the gate dielectric layer 17 and the gate conductive layer 18.

For example, referring to fig. 10 a-12 b, a channel material layer 14 is formed comprising:

conformally forming an initial channel material layer

(ii) a Forming a third mask layer 15 by using the same photomask for preparing the first mask layer 11, wherein the third mask layer 15 comprises a plurality of wall-shaped mask patterns 111 continuously extending along the first direction; forming a third insulating layer 16, wherein the third insulating layer 16 covers the sidewall of the wall-shaped mask pattern 111;

etching the initial channel material layer by using the third insulating layer 16 and the third mask layer 15 as masks

Forming a plurality of discrete layers of channel material in strips->

；

Forming a strip-shaped channel material layer

Breaking into a plurality of discreteThe island-shaped channel material layer 141, the island-shaped channel material layer 141 being defined as the channel material layer 14.

The obtained orthographic projection of the channel material layers 14 on the substrate plane extends along the first direction, each channel material layer 14 covers the surfaces of the dummy active regions 12 exposed by the two adjacent second trenches T2, the dummy active regions 12 are located on the top surfaces of the two sides of the two adjacent second trenches T2, and a plurality of channel material layers 14 are correspondingly formed on each dummy active region 12 with the wall-shaped structure.

The third mask layer 15 is formed by the same photomask for preparing the first mask layer 11, so that the orthographic projection of the wall-shaped mask pattern 111 of the third mask layer 15 on the plane of the substrate 10 is overlapped with the orthographic projection of the dummy active region 12 on the plane of the substrate 10; next, a third insulating layer 16 is formed on sidewalls of the wall-shaped mask pattern 111 such that the opening in the third mask layer 15 is reduced, and thus, the initial channel material layer is etched using the third insulating layer 16 and the third mask layer 15 as masks

The dimension of the finally formed channel material layer 14 in the second direction can be made larger than the dimension of the dummy active region 12 in the second direction, thereby ensuring that the formed channel material layer 14 can cover the sidewalls SW of the dummy active region 12 exposed by the second sub-grooves T22.

The second sub-trench T22 exposes a part of the sidewall SW of the dummy active region 12, and the channel material layer 14 and the gate conductive layer 18 at least cover the sidewall SW of the dummy active region 12 exposed by the second sub-trench T22, so that the leakage phenomenon can be effectively alleviated or eliminated, and the on-off current ratio and the current drivability of the transistor T can be improved, thereby improving the driving capability of the gate conductive layer 18 to the transistor T, reducing the power consumption, and improving the performance of the semiconductor structure.

In practice, the material of the channel material layer 14 includes an oxide semiconductor material. For example, the material of the channel material layer 14 includes at least one of indium oxide, tin oxide, an In-Zn-based oxide, a Sn-Zn-based oxide, an Al-Zn-based oxide, an In-Ga-Zn-based oxide, an In-Al-Zn-based oxide, an In-Sn-Zn-based oxide, a Sn-Ga-Zn-based oxide, an Al-Ga-Zn-based oxide, and a Sn-Al-Zn-based oxide, or a combination thereof.

The oxide semiconductor material is used as a channel for transmitting charges, so that the electric leakage phenomenon can be further effectively relieved or eliminated, and the on-off current ratio and the current drivability of the transistor T are improved, so that the driving capability of the gate conductive layer 18 on the transistor T is further improved, the power consumption is reduced, and the performance of a semiconductor structure is improved.

Finally, referring to fig. 13a to 15b and fig. 1a to 1b, forming a gate dielectric layer 17 and a gate conductive layer 18 includes:

randomly forming a gate dielectric material layer

；

Removing the gate dielectric material layer outside the second trench T2

The layer of gate dielectric material remaining in the second trench T2->

Defining as a gate dielectric layer 17;

forming a gate conductive material layer

And a layer of grid conductive material>

Covering the second dielectric layerThe top surface of the insulating layer 13 and the surface of the channel material layer 14, and the second trench T2 is filled;

removing the gate conductive material layer outside the second trench T2

A layer of gate conductive material remaining in the second trench T2>

Defined as the gate conductive layer 18.

Here, the gate dielectric material layer

The film can be formed by Chemical Vapor Deposition (CVD), plasma Enhanced Chemical Vapor Deposition (PECVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), and the like. The material of the gate dielectric layer 17 may be a high dielectric constant material, and may be, for example, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide, or barium strontium titanate. The embodiment of the present disclosure uses a high dielectric constant material as the material of the gate dielectric layer 17, which can further improve the current drivability of the transistor T.

Layer of gate conductive material

May be formed using processes such as Chemical Vapor Deposition (CVD), plasma Enhanced Chemical Vapor Deposition (PECVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), electroplating, electroless plating, sputtering, evaporation, and the like. The material of the gate conductive layer 18 includes tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), a metal alloy, or any combination thereof (e.g., a stack of TiN and W).

The portion of the channel material layer 14 covered by the gate conductive layer 18 forms a channel region c of the transistor T, and the portions of the channel material layer 14 located on both sides of the gate conductive layer 18 and not covered by the gate conductive layer 18 respectively form a source d1 and a drain d2 of the transistor T, so that 2 transistors T can be formed based on one channel material layer 14, the two transistors T having a common source d1, and a plurality of channel material layers 14 are correspondingly formed on each dummy active region 12 having a wall-like structure continuously extending in the first direction, and therefore, more than two transistors T can be formed based on one dummy active region 12 having a wall-like structure.

The dummy active regions 12 shown in fig. 7a to 7b are wall-like structures continuously extending in the first direction. But not limited thereto, in another embodiment of the present disclosure, the dummy active region 12 may also have an island-like structure.

For example, first, as shown in fig. 16a to 18b, etching the first insulating layer 101 to form the dummy active regions 12 extending in the first direction and the first trenches T1 defining the dummy active regions 12 includes:

etching the first insulating layer 101 by using the first mask layer 11 as a mask to form a wall-like structure continuously extending along the first direction

；

Etched wall-like structure

To make the wall-shaped structure->

Is cut off into a plurality of island-shaped structures>

Island-like structure>

Defined as dummy active regions 12, and gaps between the plurality of dummy active regions 12 are defined as first trenches T1.

Next, as shown in fig. 19a to 19b, the second insulating layer 13 is filled in the first trench T1.

Wall-like structure that the disclosed embodiment will extend along a first direction

Is cut off into a plurality of island-shaped structures>

So as to form dummy active regions 12, and form second insulating layers 13 between the dummy active regions 12, and thus, in the first direction, the plurality of dummy active regions 12 having island structures are also spaced apart by the second insulating layers 13, further improving the isolation effect between the transistors T to be formed later.

Next, as shown in fig. 20a to 20b, the dummy active region 12 and the second insulating layer 13 are etched to form a second trench T2 extending in the second direction, the second trench T2 including a first sub-trench T21 in the dummy active region 12 and a second sub-trench T22 in the second insulating layer 13, a bottom surface of the first sub-trench T21 being higher than a bottom surface of the second sub-trench T22.

Next, as shown in fig. 21a to 23b, a channel material layer 14 is formed including:

conformally forming an initial channel material layer

Forming a plurality of discrete layers of channel material in strips->

；

Forming a strip-shaped channel material layer

Broken into a plurality of discrete island-shaped channel material layers 141, the island-shaped channel material layers 141 being defined as the channel material layers 14.

The embodiment of the present disclosure adopts the preparation of the first mask layer 11The same mask as that of the first mask layer 15, such that the orthographic projection of the dummy active region 12 on the plane of the substrate 10 falls within the orthographic projection of the wall-shaped mask pattern 111 of the first mask layer 15 on the plane of the substrate 10; next, a third insulating layer 16 is formed on sidewalls of the wall-shaped mask pattern 111 of the third mask layer 15 such that the opening in the third mask layer 15 is narrowed, and thus, the initial channel material layer is etched using the third insulating layer 16 and the third mask layer 15 as masks

Next, a gate dielectric layer 17 and a gate conductive layer 18 are formed, and finally the semiconductor structure shown in fig. 2a and 2b is formed.

The channel material layer 14, the gate dielectric layer 17 and the gate conductive layer 18 constitute a transistor T. In the embodiment of the present disclosure, the dummy active regions 12 are island-shaped structures, one island-shaped channel material layer 141 is correspondingly formed on each of the dummy active regions 12 having the island-shaped structure, and 2 transistors T can be formed based on one channel material layer 14, so that two transistors T are formed based on one dummy active region 12 having the island-shaped structure.

The dummy active regions 12 having island-like structures shown in fig. 16a to 18b are formed by first etching the first insulating layer 101 into wall-like structures

Then the wall-shaped structure is combined with the device>

Is cut off into a plurality of island-shaped structures>

To form a dummy active region 12 having an island structure. But not limited thereto, in still another embodiment of the present disclosure, the dummy active region 12 having an island structure may also be formed through a one-step etching process.

For example, as shown in fig. 24a to 25b, etching the first insulating layer 101 to form the dummy active regions 12 extending in the first direction and the first trenches T1 defining the dummy active regions 12 includes:

forming a second mask layer 19 on the substrate 10, the second mask layer 19 including a plurality of island-shaped mask patterns 191;

etching the first insulating layer 101 by using the second mask layer 19 as a mask to form multiple island-shaped structures

The island-shaped structures 12' are defined as dummy active regions 12, and gaps between the plurality of dummy active regions 12 are defined as first trenches T1.

As such, the manufacturing process of the dummy active region 12 having the island-like structure is further simplified.

The channel material layer 14 shown in fig. 10 a-12 b and 21 a-23 b is formed by first etching the initial channel material layer

Forming a plurality of discrete layers of channel material in the form of strips->

Then the strip-shaped channel material layer is used for covering or retaining>

The plurality of discrete island-shaped channel material layers 141 are broken to form the channel material layer 14. But is not limited thereto, it is also possible to etch the initial trench material layer in one step->

The channel material layer 14 is formed to further simplify the fabrication process of the channel material layer 14.

For example, as shown in fig. 26a to 27b, the channel material layer 14 is formed including:

conformally forming an initial channel material layer

(ii) a The fourth mask layer 21, is formed using the same mask (or set of masks) used to prepare the second mask layer 19The mask layer 21 includes a plurality of island-shaped mask patterns 191; forming a fourth insulating layer 22, the fourth insulating layer 22 covering sidewalls of the island-shaped mask pattern 191;

etching the initial channel material layer by using the fourth insulating layer 22 and the fourth mask layer 21 as masks

A plurality of discrete island-shaped channel material layers 141 are formed, the island-shaped channel material layers 141 being defined as the channel material layer 14.

Here, the fourth mask layer 21 is formed using the same mask (or the same set of masks) used to prepare the second mask layer 19, such that the orthographic projection of the island-shaped mask pattern 191 of the fourth mask layer 21 on the plane of the substrate 10 overlaps with the orthographic projection of the dummy active region 12 on the plane of the substrate 10; next, a fourth insulating layer 22 is formed on sidewalls of the island-shaped mask pattern 191 of the fourth mask layer 21, so that an opening of the fourth mask layer 21 is reduced, and the initial channel material layer is etched using the fourth insulating layer 22 and the fourth mask layer 21 as masks

The dimension of the finally formed channel material layer 14 in the second direction can be made larger than the dimension of the dummy active region 12 in the second direction, thereby ensuring that the formed channel material layer 14 can cover the sidewall SW of the dummy active region 12 exposed by the second sub-trench T22.

Next, on the basis of fig. 27a to 27b, the gate dielectric layer 17 and the gate conductive layer 18 are formed continuously, and finally the semiconductor structure shown in fig. 2a to 2b is formed.

It should be noted that the channel material layer 14 can also be formed by the above-mentioned one-step etching process of the initial channel material layer 14 ″ on the basis of fig. 9a to 9 b.

In still another embodiment of the present disclosure, the gate dielectric layer 17 and the gate conductive layer 18 may also be formed as follows. For example, as shown in fig. 28a to 30b and fig. 3a to 3b, forming the gate dielectric layer 17 and the gate conductive layer 18 includes:

randomly forming a gate dielectric material layer

；

Removing part of the gate dielectric material layer outside the second trench T2

The layer of gate dielectric material remaining in the second trench T2->

A first sub-layer 171, defined as the gate dielectric layer 17, a layer of gate dielectric material which remains on the channel material layer 14 and the second insulating layer 13 on both sides of the second trench T2->

A second sublayer 172 defined as a gate dielectric layer 17;

forming a gate conductive material layer

And a layer of grid conductive material>

Covering the top surfaces of the channel material layer 14 and the second insulating layer 13 and filling the second trench T2;

etching the gate conductive material layer

A plurality of gate conductive layers 18 extending in the second direction are formed, the gate conductive layers 18 including a first sub-portion 181 and a second sub-portion 182, the first sub-portion 181 covering the first sub-layer 171 and filling the second trench T2, and the second sub-portion 182 covering the first sub-portion 181 and the second sub-layer 172.

In this way, the channel layer c is formed by the channel material layers 14 in the second trench T2 and on both sides of the first sub-trench T21, which further increases the length of the channel layer c and improves the performance of the transistor T.

It should be understood that the skilled in the art can change the above sequence of steps without departing from the scope of the disclosure, and the above is only an alternative embodiment of the disclosure and is not intended to limit the scope of the disclosure, and any modification, equivalent replacement, and improvement made within the spirit and principle of the disclosure should be included in the scope of the disclosure.

Claims

1. A semiconductor structure, comprising:

a substrate comprising a first insulating layer;

a second insulating layer filling the first trench;

the transistor comprises a channel material layer, a gate dielectric layer and a gate conducting layer, wherein the channel material layer covers the first sub-groove, the top surfaces of the pseudo active regions, which are positioned on two sides of the first sub-groove, and the side walls of the pseudo active regions, which are exposed by the second sub-groove, in a shape-following manner, the gate dielectric layer and the gate conducting layer are at least partially positioned in the second groove, and the channel material layer positioned on the side walls of the pseudo active regions, which are exposed by the second sub-groove, is covered by the gate dielectric layer and the gate conducting layer.

2. The semiconductor structure of claim 1, wherein a material of the channel material layer comprises at least one of indium oxide, tin oxide, an In-Zn based oxide, a Sn-Zn based oxide, an Al-Zn based oxide, an In-Ga-Zn based oxide, an In-Al-Zn based oxide, an In-Sn-Zn based oxide, a Sn-Ga-Zn based oxide, an Al-Ga-Zn based oxide, a Sn-Al-Zn based oxide, or a combination thereof.

3. The semiconductor structure according to claim 1, wherein an etching selection ratio of a material of the dummy active region to a material of the second insulating layer ranges from 1.2 to 1.

4. The semiconductor structure of claim 3, wherein the material of the dummy active region is an oxide and the material of the second insulating layer is a nitride.

5. The semiconductor structure according to claim 1, wherein the dummy active region is an island-like structure, and two of the transistors are formed based on one dummy active region; alternatively, the dummy active region may be a wall-like structure continuously extending in the first direction, and two or more transistors may be formed based on one dummy active region.

6. The semiconductor structure of claim 1, wherein the gate dielectric layer and the gate conductive layer are located in the second trench, the gate dielectric layer at least covers a surface of the channel material layer located in the second trench, and the gate conductive layer at least covers a surface of the gate dielectric layer and fills the second trench.

7. The semiconductor structure of claim 1, wherein the gate dielectric layer comprises a first sub-layer and a second sub-layer, the first sub-layer covers at least a surface of the channel material layer located in the second trench, the second sub-layer covers the channel material layer and a portion of a top surface of the second insulating layer located on two sides of the second trench, the gate conductive layer comprises a first sub-portion and a second sub-portion, the first sub-portion covers at least a surface of the first sub-layer and fills the second trench, and the second sub-portion covers the second sub-layer and the first sub-portion.

8. A method of fabricating a semiconductor structure, comprising:

providing a substrate comprising a first insulating layer;

etching the first insulating layer to form a dummy active region extending along a first direction and a first groove defining the dummy active region;

forming a second insulating layer filling the first trench;

etching the dummy active region and the second insulating layer to form a second trench extending along a second direction, wherein the second trench includes a first sub-trench in the dummy active region and a second sub-trench in the second insulating layer, a bottom surface of the first sub-trench is higher than a bottom surface of the second sub-trench, and the second direction crosses the first direction;

forming a transistor, wherein the transistor comprises a channel material layer, a gate dielectric layer and a gate conducting layer, the channel material layer covers the first sub-groove along the shape, the top surfaces of the pseudo active regions on two sides of the first sub-groove and the side walls of the pseudo active regions exposed by the second sub-groove, the gate dielectric layer and the gate conducting layer are at least partially positioned in the second groove, and the channel material layer on the side walls of the pseudo active regions exposed by the second sub-groove is covered by the gate dielectric layer and the gate conducting layer.

9. The method of claim 8, wherein forming a second trench in the substrate comprises:

10. The manufacturing method of the semiconductor structure according to claim 9, wherein an etching selection ratio of the dummy active region to the second insulating layer ranges from 1.2 to 1.

11. The method of manufacturing a semiconductor structure according to claim 8, wherein etching the first insulating layer to form a dummy active region extending in a first direction and a first trench defining the dummy active region comprises:

12. The method of manufacturing a semiconductor structure according to claim 8, wherein etching the first insulating layer to form a dummy active region extending in a first direction and a first trench defining the dummy active region comprises:

and etching the wall-shaped structure, cutting the wall-shaped structure into a plurality of island-shaped structures, wherein the island-shaped structures are defined as pseudo active regions, and gaps among the pseudo active regions are defined as first grooves.

13. The method of manufacturing a semiconductor structure according to claim 11 or 12, wherein forming the channel material layer comprises:

conformally forming an initial channel material layer;

14. The method of manufacturing a semiconductor structure according to claim 8, wherein etching the first insulating layer to form a dummy active region extending in a first direction and a first trench defining the dummy active region comprises:

15. The method of claim 14, wherein forming the channel material layer comprises:

conformally forming an initial channel material layer;

16. The method of claim 8, wherein forming the gate dielectric layer and the gate conductive layer comprises:

17. The method of claim 8, wherein forming the gate dielectric layer and the gate conductive layer comprises: