CN115794681B

CN115794681B - Multi-stage expandable TLB system suitable for RISC-V and address translation method thereof

Info

Publication number: CN115794681B
Application number: CN202211246153.5A
Authority: CN
Inventors: 王涛; 胡海韵; 张拥军; 徐学政; 张光达; 陈莹; 秦宵宵; 崔焱旭
Original assignee: National Defense Technology Innovation Institute PLA Academy of Military Science
Current assignee: National Defense Technology Innovation Institute PLA Academy of Military Science
Priority date: 2022-10-12
Filing date: 2022-10-12
Publication date: 2023-05-23
Anticipated expiration: 2042-10-12
Also published as: CN115794681A

Abstract

The invention discloses a multi-stage expandable TLB system suitable for RISC-V and an address translation method thereof, wherein the TLB system comprises: a multi-level TLB including a first-level TLB, and optionally, a second-level to N-level TLB, the TLB for storing page table entries of virtual to physical addresses, and for translating virtual addresses to actual physical addresses; an stlbctrl register for providing a management function for the TLB; an optional stlbiv register, a stlbidx register, a stlb0 register, a stlb1 register, and a stlb2 register, the stlbiv register being used to indicate the number of levels of the TLB when managing the TLB, the stlbidx register being used to indicate an index of the TLB in a certain level when managing the TLB, the stlb0 register being used to give a virtual page number when managing the TLB, the stlb1 register being used to give a physical page number and access control information when managing the TLB, the stlb2 register being used to give relevant information of the TLB when managing the TLB. The invention can enable the RISC-V processor facing to computation scenes with different performance requirements to realize a proper multi-level TLB structure.

Description

Multi-stage expandable TLB system suitable for RISC-V and address translation method thereof

Technical Field

The invention relates to the technical field of computers, in particular to a multistage expandable TLB system suitable for RISC-V and an address translation method thereof.

Background

Memory is a very important hardware resource in von neumann architecture computers, and it is possible to efficiently manage physical memory, which has a great impact on the overall performance of the computer system. Modern CPU (Central Processing Unit) with memory management function realizes a page-type memory management mechanism, and can effectively manage physical memory according to memory pages with fixed size. The page-based memory management mechanism uses a data structure called a page table to manage physical memory, and page tables typically have multiple levels, which results in multiple accesses to physical memory per instruction fetch and memory access, which is inefficient.

In order to solve the problem of multiple accesses caused by page tables, a modern CPU usually employs a memory management unit (Memory Management Unit, MMU) and a translation look-aside buffer (Translation Lookaside Buffer, TLB) to rapidly complete mapping from virtual addresses to physical addresses, and the TLB caches a common page table in the TLB by using a temporal locality principle and a spatial locality principle of a program, so that the number of accesses can be effectively reduced, and the overall performance of a computer system is improved.

RISC-V is an open source Instruction Set Architecture (ISA) based on the Reduced Instruction Set (RISC) principle, which adopts a page management mechanism for memory at the Supervisory privilege level, wherein RV32 supports the base, sv32 and RV64 supports the page table modes of multiple modes such as base, sv39, sv48 and the like. However, existing RISC-V specifications do not define TLB structures, which are difficult to meet computing scenarios for different performance requirements when used.

Disclosure of Invention

In order to solve some or all of the technical problems in the prior art, the present invention provides a multi-stage expandable TLB system and an address translation method thereof, which are applicable to RISC-V.

The technical scheme of the invention is as follows:

in a first aspect, there is provided a multi-stage expandable TLB system adapted for RISC-V, comprising:

a multi-level TLB comprising a first-level TLB, and optionally a second-level to N-level TLB for storing page table entries of virtual to physical addresses, and for translating virtual addresses to actual physical addresses, wherein N is a preset value;

an stlbctrl register for providing a management function for the TLB;

an alternative stlbiv register for indicating the number of levels of the TLB when the TLB is managed, an stlbidx register for indicating the index of the TLB in a certain level when the TLB is managed, an stlb0 register for giving a virtual page number when the TLB is managed, an stlb1 register for giving a physical page number and access control information when the TLB is managed, and an stlb2 register for giving an address space ID of the TLB when the TLB is managed.

In some possible implementations, the stlbctrl register sets FINV, LINV, INV, R and W domains, and TLB management is performed based on the set plurality of domains.

In some possible implementations, the TLB management mechanism is configured to:

when a 1 is written to the FINV domain of the stlbctrl register, or an extended instruction tlbfiv is executed, all TLB entries of all levels fail.

In some possible implementations, the TLB management mechanism is further configured to:

when a 1 is written to the LINV field of the stlbctrl register, or an extended instruction tlblinv is executed, all TLB entries of the hierarchy specified by the stlbctrl register fail.

when a 1 is written to the INV field of the stlbctrl register, or an extended instruction, tlbinv, is executed, the TLB entry specified by the stlbidx register in the hierarchy specified by the stlbctrl register is invalidated.

when writing 1 to the R field of the stlbctrl register, or executing an extended instruction tlbre, information of the TLB entry specified by the stlbidx register in the hierarchy specified by the stlblv register is read into the stlb0 register, the stlb1 register, and/or the stlb2 register.

when writing 1 to the W field of the stlbctrl register, or executing an extended instruction tlbwe, the information in the stlb0 register, the stlb1 register, and/or the stlb2 register is used to generate TLB entries specified by the stlbidx register in the hierarchy specified by the stlblv register.

In a second aspect, there is provided an address translation method for a multi-level expandable TLB system as described above for RISC-V, I.ltoreq.N when an implemented I-level TLB is present, the method comprising the steps of:

step S1, converting a currently used virtual address into a physical address by using address mapping information in a first-level TLB, if the conversion can be successfully performed, accessing a physical memory by using the physical address obtained by conversion, otherwise, performing step S2 when I is more than or equal to 2, and performing step S5 when I=1;

step S2, converting the currently used virtual address into a physical address by using address mapping information in the second-level TLB, if the conversion can be successfully performed, caching corresponding address conversion information into the first-level TLB, and accessing a physical memory by using the physical address obtained by conversion, otherwise, performing step S3 when I is more than or equal to 3, and performing step S5 when I=2;

step S3, the address mapping information in the next-level TLB is used for converting the currently used virtual address into a physical address, if the conversion can be successfully carried out, the corresponding address conversion information is sequentially cached in the previous-level TLB to the first-level TLB, and the physical memory is accessed by using the physical address obtained by conversion, otherwise, the step S4 is carried out;

step S4, taking the current next-level TLB as a reference, and carrying out step S3 again until the current next-level TLB is the I-level TLB, and then carrying out step S5;

step S5, searching a page table, converting a currently used virtual address into a physical address by using address mapping information in the page table, if the conversion can be successfully performed, sequentially caching corresponding address conversion information into an I-level TLB to a first-level TLB, and accessing a physical memory by using the physical address obtained by conversion, otherwise, performing step S6;

and S6, throwing out the page fault abnormality, and processing by the operating system.

In some possible implementations, the method further includes:

if the TLB hits for many times, the TLB hits for many times and is abnormal, and the operation system processes the TLB hits for many times.

The technical scheme of the invention has the main advantages that:

the multi-level expandable TLB system and the address translation method thereof suitable for RISC-V, provided by the invention, can enable a RISC-V processor facing computing scenes with different performance requirements to realize a proper multi-level TLB structure by setting the expandable multi-level TLB and adding a register to provide a mechanism for managing the multi-level TLB by software and providing an optional mechanism for realizing the multi-level TLB by expanding instructions, so as to meet the use requirements of the computing scenes with different performance requirements.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a stlbctrl register according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a stlblv register according to an embodiment of the invention;

FIG. 3 is a schematic diagram of a stlbidx register according to an embodiment of the present invention;

FIG. 4 is a schematic diagram illustrating a stlb0 register format according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a stlb1 register in accordance with an embodiment of the present invention;

FIG. 6 is a schematic diagram illustrating a stlb2 register format according to an embodiment of the present invention;

FIG. 7 is a flowchart of an address translation method according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of a Sv32 page table mode according to an embodiment of the present invention;

fig. 9 is a schematic diagram of a format of an SATP register according to an embodiment of the present invention.

Description of the embodiments

In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to specific embodiments of the present invention and corresponding drawings. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The following describes in detail the technical scheme provided by an embodiment of the present invention with reference to the accompanying drawings.

1-6, in a first aspect, an embodiment of the present invention provides a multi-stage expandable TLB system for RISC-V, the TLB system comprising:

a multi-level TLB comprising a first level TLB, and optionally, a second to N level TLB, the TLB for storing page table entries of virtual to physical addresses, and for translating the virtual addresses to actual physical addresses, wherein N is a preset value;

an stlbctrl register for providing a management function for the TLB;

an alternative stlbiv register, stlbidx register, stlb0 register, stlb1 register, and stlb2 register, the stlbiv register being used to indicate the number of levels of the TLB when managing the TLB, the stlbidx register being used to indicate an index of the TLB in a certain level when managing the TLB, the stlb0 register being used to give a virtual page number when managing the TLB, the stlb1 register being used to give a physical page number and access control information when managing the TLB, the stlb2 register being used to give an Address Space ID (ASID) of the TLB when managing the TLB.

Referring to fig. 1, in one embodiment of the present invention, a stlbctrl register defines a WPRI (Reserved Writes Preserve Values, reads Ignore Values) area, and FINV, LINV, INV, R and W functional domains, and manages TLBs based on a set plurality of functional domains.

Wherein the stlbctrl register is 32-bits in both RV32 and RV 64.

Referring to fig. 2, in one embodiment of the invention, the stlblv register defines a WPRI (Reserved Writes Preserve Values, reads Ignore Values) and a TLBLEV field that is used to specify the level of the TLB.

Wherein the stlblv register is 32-bits in both RV32 and RV 64.

Referring to fig. 3, in one embodiment of the invention, the stlbidx register defines a WPRI (Reserved Writes Preserve Values, reads Ignore Values) and a TLBNUM field that is used to specify the TLB number in the hierarchy.

Wherein the stlbidx register is 32-bits in both RV32 and RV 64.

Referring to fig. 4, in one embodiment of the present invention, the stlb0 register defines VPN (Virtual Page Number ), reserved and PSLEV fields, the PSLEV fields representing the size of the corresponding virtual page.

Wherein the stlb0 register is 32-bit in RV32 and 64-bit in RV 64.

Referring to FIG. 5, in one embodiment of the present invention, the stlb1 register defines RPN, RSW, D, A, G, U, X, W, R and V fields. V represents a valid bit, if the bit is 0, then the page table entry is invalid and the values of the other fields are meaningless; the RPN is used for designating a physical page number, and the RSW is used for being reserved for supervisory software (Supervior); a is an access domain, and when a page is Accessed, an A domain is set; d is a Dirty domain, and when a page is written, the D domain is set; x, W, R represents executable, writable, readable rights of the page, respectively; the U domain represents whether the user mode program can access the page; the G-domain represents that the page is global, i.e., the page exists in all address spaces.

Wherein the stlb1 register is 32-bit in RV32 and 64-bit in RV 64.

Referring to fig. 6, in one embodiment of the present invention, the stlb2 register defines WPRI (Reserved Writes Preserve Values, reads Ignore Values) and ASID (Address Space ID) regions.

Wherein the stlb2 register is 32-bit in RV32 and 64-bit in RV 64.

Further, in an embodiment of the present invention, based on the formats of the above-defined registers, the management mechanism for managing the TLB by the stlbctrl register, the stlblv register, the stlbidx register, the stlb0 register, the stlb1 register, and the stlb2 register is set as follows:

when writing 1 to the FINV domain of the stlbctrl register, or executing the extended instruction tlbfiv, all TLB entries (TLB entries) of all levels fail;

when writing 1 to the LINV field of the stlbctrl register, or executing the extended instruction tlblinv, all TLB entries (TLB entries) of the hierarchy specified by the stlbctrl register are invalidated;

when writing 1 to the INV field of the stlbctrl register, or executing the expanded instruction tbisn v, the TLB entry (TLB entry) specified by the stlbidx register in the hierarchy specified by the stlbctrl register is invalidated;

when writing 1 to the R field of the stlbctrl register, or executing the expanded instruction tlbre, the information of the TLB entry (TLB entry) specified by the stlbidx register in the hierarchy specified by the stlblv register is read into the stlb0 register, the stlb1 register, and/or the stlb2 register;

when writing 1 to the W field of the stlbctrl register, or executing the expanded instruction tlbwe, the information in the stlb0 register, the stlb1 register, and/or the stlb2 register is used to generate a TLB entry (TLB entry) specified by the stlbidx register in the hierarchy specified by the stlblv register.

Referring to FIG. 7, an embodiment of the present invention also provides an address translation method for the multi-level expandable TLB system for RISC-V described above, wherein when an implemented I-level TLB exists, I.ltoreq.N, the method comprising the steps of:

step S1, converting a currently used virtual address into a physical address by using address mapping information in a first-level TLB (L1 TLB), if the conversion can be successfully performed, accessing a physical memory by using the physical address obtained by conversion, otherwise, performing step S2 when I is more than or equal to 2, and performing step S5 when I=1;

step S2, using address mapping information in a second-level TLB (L2 TLB) to convert a currently used virtual address into a physical address, if the conversion can be successfully performed, caching corresponding address conversion information into the first-level TLB, and using the physical address obtained by conversion to access a physical memory, otherwise, performing step S3 when I is more than or equal to 3, and performing step S5 when I=2;

and S6, throwing out Page Fault abnormality (Page Fault abnormality) and processing by an operating system.

Specifically, when the processor needs access or instruction fetching, the memory management unit (Memory Management Unit, MMU) acquires the corresponding virtual address, and based on the acquired virtual address, converts the virtual address into a physical address by using the address conversion method described above.

In one embodiment of the present invention, when the TLB system includes multiple levels of TLB implemented, the last level of TLB is a cache of the page table, and the last level of TLB is a cache of the next level of TLB. If the multi-level TLB is not implemented, the first-level TLB is a cache of the page table.

Because of the exception of the multi-level TLB mechanism caused by the unstable factors or software faults in the hardware circuit, it is necessary to extend the type of TLB-related exception to handle the related exception, for example, TLB Error Exception is required to be generated by the hardware when the TLB entry ECC is abnormal, or TLB multiple hit Exception is required to be generated by the hardware when a virtual address can match a plurality of TLB entries.

Further, in an embodiment of the present invention, the address translation method further includes: if a TLB hit (TLB multiple-hit exception) occurs, the TLB hit exception is thrown out and handled by the operating system.

RISC-V realizes the mode of various page tables, sv32 is under RV32, RV64 defines Sv39 and Sv48, RV64 also reserves Sv57, and Sv64 extends in future versions.

Further, the following illustrates the matching process of the multi-level expandable TLB system provided by an embodiment of the present invention in different page table modes:

referring to fig. 8-9, the MODE field of the SATP register indicates the page table MODE used by the current hardware, and the address translation algorithm of the page table is different and the TLB is matched differently in different page table MODEs.

Taking Sv32 of RV32 as an example, the virtual address, the physical address and the Page Table entry are divided as shown in fig. 8, and in the address conversion algorithm defined by Sv32, reference is made to Volume ii: RISC-V Privileged Architectures, page 70, defines a level variable of 2. At the end of the conversion algorithm, when level is 1, it is explained that 4MB pages need to be mapped; when level is 0, it is indicated that 4KB pages need to be mapped. The value of LEVELS obtained by the Sv32 address translation algorithm will be the value of TLB0[ PSLEV ] in the TLB.

According to the analysis, in the Sv32 page table mode, the conditions for successful TLB matching are:

when pslev=0,

if VA [31:12] =vpn [32:12] & asid=satp [ ASID ]

When established, the TLB match is indicated to be successful.

When pslev=1,

if VA [31:22] =vpn [32:22] & asid=satp [ ASID ]

When established, the TLB match is indicated to be successful.

For other page table modes defined by RISC-V, such as Sv39, sv48 supported by RV64, similar TLB matching algorithms as described above are also supported modularly.

According to the multi-level expandable TLB system and the address translation method thereof, which are suitable for RISC-V, provided by the embodiment of the invention, by setting the expandable multi-level TLB, adding a register to provide a mechanism for managing the multi-level TLB by software, and providing an optional mechanism for realizing the multi-level TLB by expanding instructions, a RISC-V processor facing computing scenes with different performance requirements can realize a proper multi-level TLB structure so as to meet the use requirements of the computing scenes with different performance requirements.

It should be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. In this context, "front", "rear", "left", "right", "upper" and "lower" are referred to with respect to the placement state shown in the drawings.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting thereof; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A multi-stage expandable TLB system adapted for RISC-V, comprising:

an stlbctrl register for providing a management function for the TLB;

an alternative stlbiv register for indicating the number of levels of the TLB when the TLB is managed, an stlbidx register for indicating an index of the TLB in a certain level when the TLB is managed, an stlb0 register for giving a virtual page number when the TLB is managed, an stlb1 register for giving a physical page number and access control information when the TLB is managed, and an stlb2 register for giving an address space ID of the TLB when the TLB is managed;

the stlbctrl register sets FINV, LINV, INV, R and W domains, and performs TLB management based on the set plurality of domains.

2. The multi-level expandable TLB system for RISC-V according to claim 1, wherein the TLB management mechanism is configured to:

3. The multi-level expandable TLB system for RISC-V according to claim 2, wherein the TLB management mechanism is further configured to:

4. A multi-level expandable TLB system for RISC-V according to claim 3, wherein the TLB management mechanism is further configured to:

5. The multi-level expandable TLB system for RISC-V according to claim 4, wherein the TLB management mechanism is further configured to:

6. The multi-level expandable TLB system for RISC-V according to claim 5, wherein the TLB management mechanism is further configured to:

7. An address translation method for a multi-level expandable TLB system for RISC-V according to any one of claims 1 to 6, wherein when an implemented level I TLB is present, I.ltoreq.N, said method comprising the steps of:

8. The address translation method of claim 7, wherein said method further comprises: