CN115792699A

CN115792699A - Bus fault detection circuit

Info

Publication number: CN115792699A
Application number: CN202211428156.0A
Authority: CN
Inventors: 万明亮
Original assignee: Shanghai Chuantu Microelectronics Co ltd
Current assignee: Shanghai Chuantu Microelectronics Co ltd
Priority date: 2022-11-15
Filing date: 2022-11-15
Publication date: 2023-03-14

Abstract

The invention provides a bus fault detection circuit, comprising: the device comprises a level conversion module, a judgment comparison module and a counting locking module; the level conversion module is connected with bus input signals CANH and CANL and outputs differential voltage of the bus and the power supply to the judgment comparison module; the judgment comparison module is used for comparing the differential voltage with the component of the power supply voltage, and if the bus voltage is in a fault judgment interval, a high level is output to the counting locking module for fault alarm; the input end of the leading edge blanking module is connected with a TXD input signal and used for controlling the TXD input signal to output a control signal TXDn _ deglitch to the counting locking module after a delay time when the TXD input signal generates falling edge jumping; and the counting locking module identifies whether the bus has a Fault or not, and outputs a bus Fault identifier Fault if the Fault is determined to really occur. The invention can monitor the bus state in real time and can report faults quickly and accurately when the bus is short-circuited to a power supply or the ground.

Description

Bus fault detection circuit

Technical Field

The invention relates to the technical field of communication bus interface networks, in particular to a bus fault detection circuit.

Background

In industrial control and vehicle-mounted networks, a pair of differential buses is often used for transmitting signals, and the reliability and the universality are high, such as a CAN bus and an RS485 bus. A bus is usually hung with a plurality of nodes, and each node can independently control the state of the bus to receive and transmit data. When one of the nodes fails, the bus may be shorted to power or ground, requiring the system to report and troubleshoot the failure in time.

In the existing CAN bus ground short circuit on-line monitoring method, a resistor is connected in series on a bus for fault detection, and because voltage drop exists on the detection resistor, heating and efficiency loss CAN be caused, so that bus communication is influenced.

Disclosure of Invention

In view of this, embodiments of the present disclosure provide a bus fault detection circuit, which can monitor the state of a bus in real time without affecting bus communication, and can report a fault quickly and accurately when the bus is shorted to a power supply or a ground.

The embodiment of the application provides the following technical scheme: a bus fault detection circuit comprising:

the system comprises a level conversion module, a judgment comparison module and a counting locking module which are sequentially in communication connection;

the input end of the level conversion module is connected with bus input signals CANH and CANL and is used for carrying out level conversion on bus voltage and outputting differential voltage of a bus and a power supply to the judgment and comparison module; the judgment comparison module is used for comparing the differential voltage with the component of the power supply voltage, and if the bus voltage is in a fault judgment interval, a high level is output to the counting locking module to carry out fault alarm;

the counter is characterized by further comprising a leading edge blanking module, wherein the input end of the leading edge blanking module is connected with a TXD input signal, the TXD input signal is used for controlling switching of dominant and recessive states of buses CANH and CANL, and the leading edge blanking module is used for controlling the TXD input signal to output a control signal TXDn _ deglitch to the counter locking module after a delay time when the TXD input signal generates falling edge jumping;

and the counting locking module identifies whether the bus has a Fault according to the control signal TXDn _ deglitch and the high-level Fault alarm signal output by the judgment and comparison module, and outputs a bus Fault identifier Fault if the fact that the Fault really occurs is determined.

According to one embodiment, the process of identifying whether the bus has a fault by the count locking module comprises the following steps:

and the counting locking module counts the input high-level effective Fault detection time, judges that the Fault really occurs if the effective Fault detection time lasts for at least two cycles, and outputs a bus Fault identifier Fault after locking the signal.

According to one embodiment, after the bus Fault is relieved, the counting locking module clears the counter and the Fault identifier Fault.

According to one embodiment, the level conversion module comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a buffer and an amplifier;

the first end of the first resistor is connected with bus input signals CANH and CANL, the second end of the first resistor is connected with the first end of the second resistor, and the second end of the second resistor is connected to a common mode point Vcc/2; the middle node of the first resistor and the second resistor is connected with the input end of the buffer, and the output end of the buffer is connected with the first end of the third resistor and is used for outputting the voltage of the middle node to the third resistor in a level manner; the second end of the third resistor is connected with the first input end of the amplifier, the second input end of the amplifier is connected with a reference level Vcc/2, the output end of the amplifier is connected to the first input end of the amplifier through the feedback of the fourth resistor, and the amplifier outputs differential voltage of a bus and a power supply to the judgment and comparison module.

According to an embodiment, the relationship between the resistance value R1 of the first resistor, the resistance value R2 of the second resistor, the resistance value R3 of the third resistor and the resistance value R4 of the fourth resistor is: r2 × R4/R3 (R1 + R2) =1.

According to one embodiment, the decision comparison module comprises a comparator, a first input end of the comparator is connected with the output end of the amplifier, a second input end of the comparator is connected with a reference level Vcc/N, and the comparator is used for comparing a differential voltage Vcc-CANH of a bus and a power supply with a component Vcc/N of a power supply voltage, and when the bus voltage CANH enters a fault decision interval Vcc-Vcc/N, the comparator outputs a high level to carry out fault alarm.

The embodiment of the specification can achieve the following beneficial effects at least: the invention provides a bus fault detection circuit which can accurately monitor the occurrence of bus faults in real time and send out fault reports in time under the condition of not influencing the normal communication of a bus. The fault judgment interval provided by the invention changes along with the change of the power supply Vcc, so that the fault misjudgment rate is reduced when the power supply Vcc has different voltages.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 illustrates a conventional transceiver architecture and fault detection circuitry;

FIG. 2 is a block diagram of a bus fault detection architecture according to the present invention;

FIG. 3 is a diagram illustrating a normal operation interval and a fault detection interval of a bus according to an embodiment of the present invention;

FIG. 4 is a diagram of a level sampling circuit and a decision comparison circuit according to an embodiment of the present invention;

FIG. 5 is a waveform diagram of nodes at different levels according to an embodiment of the present invention.

Detailed Description

The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present invention will be described in detail with reference to the accompanying drawings, wherein the embodiments are described in detail, and it is to be understood that the embodiments are only a part of the embodiments of the present invention, and not all of the embodiments are described. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

As shown in fig. 1, fig. 1 illustrates a conventional transceiver structure and a fault detection circuit. The CAN transceiver 10 drives the buses CANH and CANL to communicate, and the resistor 15 is a termination load of the buses. The conventional bus fault detection method is that a detection resistor 13 and another detection resistor 14 are inserted between a CAN transceiver 10 and a terminal load resistor 15, when short-circuit faults occur to buses CANH and CANL, the current value flowing through the detection resistor 13 and the another detection resistor 14 is different from the normal state, and a first comparator 11 and a second comparator 12 connected to two ends of the detection resistor CAN detect the fault state and send out fault alarm. This fault detection method requires a detection resistor to be connected in series with the bus, which causes a voltage drop and a power loss.

As shown in fig. 2, the present invention provides a bus fault detection circuit, including:

the system comprises a level conversion module 20, a judgment comparison module 21 and a counting locking module 22 which are sequentially in communication connection;

the input end of the level shift module 20 is connected to bus input signals CANH and CANL, and is configured to perform level shift on a bus voltage, and output a differential voltage between a bus and a power supply to the decision comparison module 21; the decision comparing module 21 is configured to compare the differential voltage with a component of a power supply voltage, and if the bus voltage is in a fault decision interval, output a high level to the count locking module 22 to perform fault alarm;

the counter locking module 22 further comprises a leading edge blanking module 23, wherein an input end of the leading edge blanking module 23 is connected to a TXD input signal, the TXD input signal is used for controlling switching of dominant and recessive states of buses CANH and CANL, and the leading edge blanking module 23 is used for controlling the TXD input signal to output a control signal TXDn _ deglitch to the counter locking module 22 after a delay time when a falling edge jump occurs in the TXD input signal;

the counting locking module 22 identifies whether the bus has a Fault according to the control signal TXDn _ deglitch and the high-level Fault alarm signal output by the decision comparing module 21, specifically, the counting locking module 22 counts the input high-level effective Fault detection time, and if the effective Fault detection time lasts for at least two cycles, it is determined that the Fault really occurs, and a bus Fault identifier Fault is output.

The invention carries out level conversion on the bus voltage, displays the differential voltage between the bus voltage and the power supply, compares the differential voltage with one component of the power supply voltage, and outputs high level to alarm when the bus voltage is in a fault interval.

When the transceiver explicitly transitions to a recessive transition, the bus state transitions and changes in the bus level may cause glitches in the output of the fault detection comparator. Therefore, the deburring processing is required when the state of the transceiver jumps, if the fault is still reported after deburring and lasts for several cycles, the fault is judged to be really generated and locked to send out an alarm. And resetting the counter and the alarm after the fault is relieved, and monitoring the bus state again by the system.

In the embodiment of the present invention, as shown in fig. 2, the bus input signals CANH and CANL are connected to the level conversion module 20, and after level conversion, the differential voltage Vs between the bus and the power supply is output to the next stage. The decision comparison module 21 compares the converted differential voltage with the component of the power supply voltage, and gives an alarm to the next stage if the bus is in a fault state. Since the bus voltage fluctuates during the bus state switching, the fault detection output is disturbed, and a delay time is required to remove the glitch. The TXD signal controlling the switching of the state is connected to the leading edge blanking block 23, and the control signal TXDn _ deglitch is sent to the next stage after a delay time when the TXD generates a falling edge transition. The counting locking module 22 identifies whether the bus has a Fault according to the output Vout of the decision comparing module 21 and the output TXDn _ deglitch of the leading edge blanking module 23, and if the Fault is determined, an alarm Fault is issued. And clearing the counter and the Fault identifier Fault after the bus Fault is relieved.

As shown in fig. 3, fig. 3 shows a normal operation interval and a fault detection interval of the bus. In the dominant state, the normal operating ranges of buses CANH and CANL are shown in FIGS. CANH 31 and CANL 32, respectively. If a bus fault occurs, such as a CANL short to ground through a small resistor or a CANH short to power supply VCC through a small resistor, the bus will be within the range of the fault intervals CANH short 30 and CANL short 33, at which time the fault detection circuit will recognize these faults and issue an alarm. The bus is in the normal working interval and does not give out an alarm.

In the embodiment of the present invention, as shown in fig. 4, the level shift module 20 includes a first resistor 40, a second resistor 41, a third resistor 43, a fourth resistor 44, a buffer 42, and an amplifier 45;

a first end of the first resistor 40 is connected to bus input signals CANH and CANL, a second end is connected to a first end of the second resistor 41, and a second end of the second resistor 41 is connected to a common mode point Vcc/2; the intermediate node of the first resistor 40 and the second resistor 41 is connected to the input terminal of the buffer 42, and the output terminal of the buffer 42 is connected to the first terminal of the third resistor 43, so as to output the voltage of the intermediate node to the third resistor 43 at equal level; the second end of the third resistor 43 is connected to the first input end of the amplifier 45, the second input end of the amplifier 45 is connected to the reference level Vcc/2, the output end of the amplifier 45 is fed back to the first input end of the amplifier 45 through the fourth resistor 44, and the amplifier 45 outputs the differential voltage between the bus and the power supply to the decision comparing module 21.

The decision comparing module 21 comprises a comparator 46, wherein a first input end of the comparator 46 is connected with the output end of the amplifier 45, a second input end of the comparator 46 is connected with a reference level Vcc/N, the comparator is used for comparing a differential voltage Vcc-CANH of a bus and a power supply with a component Vcc/N of a power supply voltage, and when the bus voltage CANH enters a fault decision interval Vcc-Vcc/N, the comparator 46 outputs a high level to carry out fault alarm.

Specifically, the bus line CANH/L is connected to the common mode point Vcc/2 through the voltage dividing first resistor 40 and the voltage dividing second resistor 41, so that the level of the intermediate node between the voltage dividing first resistor 40 and the voltage dividing second resistor 41 is CANH R2/(R1 + R2) + Vcc R1/2 (R1 + R2). The input terminal of the buffer 42 is connected to the intermediate output node of the voltage dividing resistor for outputting the voltage level of the intermediate node to the next stage without drawing extra current from the voltage dividing resistor. A third resistor 43 is connected to the output of the buffer 42 and connected to one input of an amplifier 45, the other input of the amplifier 45 being connected to the reference level Vcc/2, and the output of the amplifier 45 being fed back to its input via a fourth resistor 44. Thus, the output level of the amplifier 45 is Vcc/2- (CANH-Vcc/2) × R2 × R4/R3 (R1 + R2). If the values of the fourth resistor 44R4 and the third resistor 43R3 are proper, such that R2 × R4/R3 (R1 + R2) =1, the output level Vs of the amplifier 45 is Vcc-CANH, and the circuit characterizes the difference between CANH and Vcc. One input of comparator 46 is connected to the output of preamplifier 45 and the other input is connected to reference Vcc/N, so that comparator 46 will output an alarm when the two inputs of comparator 46 are close in level, i.e. CANH goes between fault intervals Vcc to (Vcc-Vcc/N). The framework has the advantages that the fault judgment interval (Vcc-Vcc/N) is changed along with the change of the power Vcc, and the fault misjudgment rate is reduced when different power supply voltages are different.

As shown in fig. 5, fig. 5 shows waveforms of nodes at different levels according to the embodiment of the present invention. Waveform 50 is the TXD input signal for controlling the dominant and recessive states of CANH bus 51 and CANL bus 52. When the bus fails, such as when CANL suddenly shorts to GND, the output of comparator 46 in FIG. 4 will signal an alarm, as shown by waveform Vout _ L53. When the input state of the TXD is switched, the bus state during short circuit is also different, and the output of the comparator 46 may have a glitch, so that to prevent the misjudgment of the next stage, the judgment needs to be performed after a delay after the TXD jumps. This is determined by the output signal TXDn _ deglitch of the leading edge blanking module 23 in fig. 2, i.e. the high level of the waveform TXDn _ deglitch 54 is the active Fault detection time, and the counter counts two cycles to output the Fault identifier Fault after confirming the active Fault, as shown by Fault 55.

The bus fault detection circuit can accurately monitor the occurrence of bus faults in real time and send out fault reports in time under the condition of not influencing the normal communication of the bus.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A bus fault detection circuit, comprising:

the input end of the level conversion module is connected with bus input signals CANH and CANL and is used for carrying out level conversion on bus voltage and outputting differential voltage of a bus and a power supply to the judgment and comparison module; the judgment comparison module is used for comparing the differential voltage with the component of the power supply voltage, and if the bus voltage is in a fault judgment interval, a high level is output to the counting locking module for fault alarm;

and the counting locking module identifies whether the bus has a Fault according to the control signal TXDn _ debug and the high-level Fault alarm signal output by the judgment and comparison module, and outputs a bus Fault identifier Fault if the bus is determined to be true.

2. The bus fault detection circuit of claim 1, wherein the process of the count lock module identifying whether the bus has a fault comprises:

3. The bus Fault detection circuit of claim 1, wherein the count lock module clears the counter and the Fault identifier Fault after the bus Fault is resolved.

4. The bus fault detection circuit of claim 1, wherein the level shift module comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a buffer, and an amplifier;

5. The bus fault detection circuit according to claim 4, wherein a relationship among the resistance value R1 of the first resistor, the resistance value R2 of the second resistor, the resistance value R3 of the third resistor, and the resistance value R4 of the fourth resistor is: r2 × R4/R3 (R1 + R2) =1.

6. The bus fault detection circuit of claim 5, wherein the decision comparison module comprises a comparator having a first input connected to the output of the amplifier and a second input connected to a reference level Vcc/N for comparing a differential bus-to-power supply voltage Vcc-CANH with a supply voltage component Vcc/N, and wherein the comparator outputs a high level for fault alarm when the bus voltage CANH enters a fault decision interval Vcc to Vcc-Vcc/N.