CN1157854C - High-speed Turbo code decoder - Google Patents
High-speed Turbo code decoder Download PDFInfo
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- CN1157854C CN1157854C CNB001195093A CN00119509A CN1157854C CN 1157854 C CN1157854 C CN 1157854C CN B001195093 A CNB001195093 A CN B001195093A CN 00119509 A CN00119509 A CN 00119509A CN 1157854 C CN1157854 C CN 1157854C
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Abstract
The present invention relates to a high-speed Turbo code decoder which comprises a depunch, a memory unit, two interlaced devices, a deinterlaced device for generating soft information data in normal sequence, three selectors, a calculating unit for decoding and calculating the information data to generate new soft information data, a deinterlaced device for generating soft information in normal sequence after iteration, and a hard decision unit for generating final decoding output. The input terminal of an SISO module uses an input selector to strobe the input of X/Y0/Y1/Z OR X'/Y0'/Y1'/Z' so that the secondary SISO calculation of the decoding iteration of a Turbo code is completed in the same SISO module so as to greatly lower the scale of hardware.
Description
The present invention relates to the Turbo code decoder in the wireless mobile communications mobile system, particularly a kind of high-speed Turbo code decoder that is based upon single soft inputting and soft output (SISO) unit that reduces to realize resource and adopt.
In wireless communication system, because the inhomogeneities and the unsteadiness of transmission medium, the signal of transmission can be subjected to interference effects such as time diffusion, decline, causes the mistake of the peculiar randomness of ratio of reception.In order to prevent the interference effect of interchannel noise, need to adopt certain mode to improve the transmission reliability and the validity of information.By increasing the error correction/encoding method that redundancy reduces the error rate, be class important means effectively reliably by time-proven.In mobile communication and satellite communication system, error correcting code obtains technology application widely especially.
Turbo code is proved to be the very strong sign indicating number of a kind of error correcting capability.Its encoder is to be made of the cascade system of two or more sub-encoders by serial or parallel connection, usually more general Turbo code encoder is to be formed in parallel by two encoder for convolution codess, sub-encoders 1 is directly sent in input information position one tunnel, another road is through sending into sub-encoders 2 codings behind the interleaver, punching is modulated to suitable code check output to the data after having compiled through card punch again.The Turbo code encoder of advising in the cdma2000 motion is made of two RSC convolution code sub-encoders parallel connections, as shown in Figure 1.
Accompanying drawing 1 is the structure of the Turbo code encoder in cdma2000 and the WCDMA motion, comprising: the interleaver 12 of two sub-encoders 14 and 16, one encoder inside, an and card punch 18 up and down.The effect of interleaver 12 is that the order of input data is carried out layout again, and purpose is to adjust the distribution of weight, makes weight distribution and sub-encoders 14 different of sub-encoders 16 incoming bit streams; Card punch 18, can punch to six road bits of two sub-encoders outputs sampling and and string conversion.
Encoder for convolution codes use usually (n0, k0 m) come representation feature, n0 be output bit, k0 is an input bit, m is the register number.K represents constraint length, is convolution code internal displacement the number of registers m and adds 1.Encoder as shown in Figure 2 for Turbo code in the cdma2000 motion (3,1,4) RSC (regression system convolution code).
Accompanying drawing 2 is structures of sub-encoders in the Turbo code encoder in the cdma2000 motion.It is the regression system encoder for convolution codes of a R=1/3 code check, is abbreviated as RSC.Comprise: shift register 21 and tail bit controller 24 and modulo 2 adder 22 etc.; Shift register one has three, thus m=3, K=4.After frame data inputs finishes, need at this moment tail bit controller switches be switched to the below to the register zero clearing, by three beats, with the bit in three registers as importing zero clearing successively.
The RSC sub-encoders of the Turbo code encoder in the WCDMA motion is similar in accompanying drawing 2, does not just have the output of Y1, just the RSC of (2,1,3).
The decoding of Turbo code can be adopted maximum likelihood method decoding, also can adopt the maximum posteriori decoding algorithm, and these two kinds of methods all are used for the recursive iteration mode in the Turbo decoding.Accompanying drawing 3 is a kind of general Turbo decoder architectures, comprising: 34,45, two deinterleavers 36,37, of 32,33, two interleavers of two soft inputting and soft output decoders of SISO-1, SISO-2 are separated a card punch 31 and a symbol judgement device 38.Difference according to decoding algorithm mainly is divided into maximum posteriori decoding (MAP) and maximum-likelihood decoding (SOVA).The 31st, separate perforating device, corresponding to the inverse operation of card punch.Deinterleaver 36,37 inverse operations corresponding to interleaver, the order before reduction interweaves.The 35th, interleaver, 12 identical with in the accompanying drawing 1.The effect of symbol judgement device 38 is, when the input data greater than 0 the time, output 1; When the input data less than 0 the time, output 0.
The Turbo code decoding is a kind of decode procedure of recursive iteration mode, 3 Turbo code decode structures with reference to the accompanying drawings, each iterative decoding need carry out the SISO computing of secondary, the input of SISO-1 decoder 32 is that receiving terminal is separated information digit after the punching according to the check digit data Y 0/Y1 of X, sub-encoders 14 (in conjunction with Fig. 1) and the soft information Z of SISO-2 decoder 33 outputs, and output is through interweaving as the soft information input of SISO-2 decoder 33; The input of SISO-2 decoder 33 be receiving terminal separate punching and interweave after information digit according to the check digit data Y 0 of X ', sub-encoders 16 (in conjunction with Fig. 1) '/the soft information Z ' of Y1 ' and 32 outputs of SISO-1 decoder, output is not through the soft information input of deinterleaving as SISO-1 decoder 32 when the iteration termination condition does not satisfy, and when satisfying the iteration termination condition, output is decoded as Turbo through hard decision and is exported.The performance decision that the number of times of recursive iteration requires according to decoding.
3 structures with reference to the accompanying drawings, the Turbo decoder needs two SISO computing units, and this soft inputting and soft output computing unit SISO-1 32 and SISO-2 33 are identical two processing units, have the shortcoming that hardware size is big, cost of manufacture is high.
The objective of the invention is in order to overcome the shortcoming of existing Turbo decoder, and a kind of of proposition implements a kind of Turbo code decoder that adopts single SISO structure that requirement designs according to cdma2000 and WCDMA motion Turbo code, thereby reduced the realization scale of Turbo code decoder greatly.
The technical scheme that realizes the object of the invention is: a kind of high-speed Turbo code decoder, be characterized in, comprise: one is used for separating card punch with what the information encoded data were separated with checking data, a memory cell that is used to store the information data that receiving terminal receives, first interleaver that is used to produce the interweaving information data, one is used to produce second interleaver of soft information data of interweaving, first deinterleaver that is used to produce the soft information data of normal sequence, three selectors that are used to select information data, one is used for information data, checking data and soft information data are decoded computing and are produced the computing unit of new soft information data, one is used for finishing second deinterleaver that the back produces the soft information of normal sequence in iteration, and a hard decision unit that is used to produce final decoding output;
Described memory cell comprises: one is used for stored information memory of data A, a memory B who is used to store the checking data Y of the sub-encoders 1 that receiving terminal receives, a memory C who is used to store the checking data Y ' of the sub-encoders 2 that receiving terminal receives, and initial value is 0, is used for storing the memory D of the soft information data that iterative process produces;
Described selector comprises: a selector A who is used to select information data or interweaving information data, a selector B who is used for chooser encoder 1 checking data or sub-encoders 2 checking datas, a selector C who is used to select the soft information data (deinterleaving) or the soft information data that interweaves;
Signal through separating card punch output is connected respectively to memory A, B, C; From memory A output two-way information, the one road is connected to selector A, and another road outputs to selector A again behind first interleaver; Export a signal respectively to selector B from memory B and memory C; Export a soft information data to memory D from the computing unit that produces new soft information data, its output signal is connected to selector C behind first deinterleaver or second interleaver; These three selector signals are input to computing unit, the soft data signal of computing unit output or feed back to memory D, or directly by exporting through judgement back, hard decision unit again behind second deinterleaver.
Because the present invention has adopted above technical scheme, the input of SISO module adopts input selector gating X/Y0/Y1/Z or X '/Y0 '/Y1 '/Z ' input, the secondary SISO computing of Turbo code decoding iteration is finished in same SISO module, thereby hardware size is reduced greatly.
Concrete feature of the present invention and performance are further provided by following embodiment and accompanying drawing thereof.
Accompanying drawing 1 is the Turbo code coder structure schematic diagram of prior art cdma2000 and WCDMA system.
Accompanying drawing 2 is Turbo code encoder neutron coder structure schematic diagrames of prior art cdma2000.
Accompanying drawing 3 is decoder architecture schematic diagrames of prior art Turbo code.
Accompanying drawing 4 is structural representations of Turbo code decoder of the present invention.
See also Fig. 4, Turbo code decoder of the present invention comprises: separate card punch 41 with what the information encoded data were separated with checking data for one, a memory cell 42 that is used to store the information data that receiving terminal receives, two are respectively applied for generation interweaving information data and produce first of the soft information data that interweaves, second interleaver 43,45, a deinterleaver 44 that is used to produce the soft information data of normal sequence, three selectors 46 that are used to select information data, 47,48, one is used for information data, the computing of decoding of checking data and soft information data, a computing unit 49 that produces new soft information data, one is used for finishing the deinterleaver 50 that the back produces the soft information of normal sequence in iteration, and a hard decision unit 51 that is used to produce final decoding output.Memory cell 42 comprises: one is used for stored information memory of data A42a, a memory B42b who is used to store the checking data Y of the sub-encoders 1 that receiving terminal receives, a memory C42c who is used to store the checking data Y ' of the sub-encoders 2 that receiving terminal receives, and initial value is 0, is used for storing the memory D42d of the soft information data that iterative process produces.Selector comprises: a selector A46 who is used to select information data or interweaving information data, a selector B47 who is used for chooser encoder 1 checking data or sub-encoders 2 checking datas, a selector C48 who is used to select the soft information data (deinterleaving) or the soft information data that interweaves.
After separating card punch 41, output to memory B42b and the storage data Y of memory A42a, the storage checking data Y of stored information data X respectively from the signal of channel received code device ' memory C42c; From the memory A42a of stored information data X output two-way information, the one road to the selector A46 that is used to select information data or interweaving information data, another road behind first interleaver 43 again to the selector A46 that is used to select information data or interweaving information data; Memory B42b and storage data Y from storage checking data Y ' the signal of memory C42c output to the selector B47 of chooser encoder 1 checking data or sub-encoders 2 checking datas; Memory D42d from the soft information data of computing unit 49 output that produces new soft information data to soft information data, it outputs to first deinterleaver 44 and second interleaver 45, outputs to the selector C48 that selects the soft information data (deinterleaving) or the soft information data that interweaves then; Output to second deinterleaver 50 by the computing unit 49 that produces new soft information data again from the information of three selector outputs, again hard decision unit 51 judgement back outputs by producing final decoding output.
Separate the inverse operation of card punch 41 corresponding to encoder card punch 18, the data that the Turbo code encoder produces are information bit X, sub-encoders 1 check digit Y, sub-encoders 2 check digit Y ' serial transmissions, serial data need be decomposed out separately in decoding end and deposit.Need data in the memory cell 42 storage Turbo code iterative decoding processes, memory A42a stored information data X wherein, the check digit Y of memory B42b storage sub-encoders 1, the check digit Y ' of memory C42c storage sub-encoders 2, the soft information Z that produces in the memory D42d storage iterative process.Memory A42a, memory B42b, memory C42c adopt ping-pong structure, and decoder is in that decode can also normal receive channel data when calculating like this, thereby improves decoding processing efficient.Soft inputting and soft is exported processing unit 49, can adopt in SOVA, MAP, LOG-MAP or the MAX-LOG-MAP algorithm any one.In the present invention, interweave, trellis decoded all finishes in SISO computing unit 49.Input at computing unit 49 has three selectors, the information data X that is stored among the memory A42a is received in selector A46 butt joint and the interweaving information data X ' that passes through interleaver 43 selected, selector B47 butt joint is received the sub-encoders 1 that is stored among the memory B42b and is produced checking data Y and receive the sub-encoders 2 that is stored among the memory C42c and produce checking data Y ' and select, and soft information Z's selector C48 interweaves among the memory 42d, deinterleaving is selected to being stored in of producing of SISO computing last time.Satisfy the condition (as iterations) of design appointment when iteration after, the 51 pairs of soft information through second deinterleaver 50 in hard decision unit are carried out hard decision, get decoding output to the end.
It for the design iteration number of times three times Turbo code decoder, be stored in memory A separating the frame signal that card punch will receive, memory B, after memory C finishes, soft inputting and soft output SISO computing unit is started working, selector A during iteration SISO computing for the first time for the first time, selector B, selector C selection path I, the SISO computing unit is handled X, Y and initial value are 0 Z data, after computing finishes, soft information deposits memory D in, beginning iteration SISO computing for the second time for the first time, this moment selector A, selector B, selector C selection path II, the SISO computing unit is handled the X after interweaving, Y ' and interweave after Z, soft information write back memory D after computing finished, and iterative computation finishes for the first time.During iteration SISO computing for the first time for the second time, selector A, selector B, selector C selection path I, the SISO computing unit is handled the Z data after X, Y and the deinterleaving, soft information write back memory D after computing finished, beginning iteration SISO computing for the second time for the second time, selector A, selector B, selector C selection path II, SISO computing unit handle X, the Y ' after interweaving and interweave after Z, soft information write back memory D after computing finished, and iterative computation finishes for the second time.During iteration SISO computing for the first time for the third time, selector A, selector B, selector C selection path I, the SISO computing unit is handled X, Z data after Y and the deinterleaving, soft information write back memory D after computing finished, begin iteration SISO computing for the second time for the third time, selector A, selector B, selector C selection path II, the SISO computing unit is handled the X after interweaving, Y ' and interweave after Z, because iteration is the last iteration of design for the third time, therefore export as decoded result behind soft information via second deinterleaver of iteration SISO computing generation for the second time for the third time and the hard decision unit, iterative computation finishes for the third time, one frame decoding finishes, memory A, memory B, the memory C switching of rattling, the decoding of beginning next frame.
The whole implementation structure of Turbo decoder is based on the recursive iteration algorithm, used decode time is the computing time of the SISO of 2* iterations, and the secondary SISO in iteration calculates and shares same circuit, can reach and two decode time and decoding performances that the SISO computing circuit is same for frame data, greatly reduce the realization scale.
The present invention is applicable to the Turbo code decoding that W-CDMA and cdma2000 agreement are formulated.
Claims (1)
1, a kind of high-speed Turbo code decoder, comprise: one is used for separating card punch (41) with what the information encoded data were separated with checking data, first interleaver (43) that is used to produce the interweaving information data, one is used to produce second interleaver (45) of soft information data of interweaving, first deinterleaver (44) that is used to produce the soft information data of normal sequence, it is characterized in that, also comprise a memory cell (42) that is used to store the information data that receiving terminal receives, three selectors (46 that are used to select information data, 47,48), one is used for information data, checking data and soft information data are decoded computing and are produced the computing unit (49) of new soft information data, one is used for finishing second deinterleaver (50) that the back produces the soft information of normal sequence in iteration, and a hard decision unit (51) that is used to produce final decoding output;
Described memory cell (42) comprising: one is used for stored information memory of data A (42a), a memory B (42b) who is used to store the checking data Y of the sub-encoders 1 that receiving terminal receives, a memory C (42c) who is used to store the checking data Y ' of the sub-encoders 2 that receiving terminal receives, and initial value is 0, is used for storing the memory D (42d) of the soft information data that iterative process produces;
Described selector comprises: a selector A (46) who is used to select information data or interweaving information data, a selector B (47) who is used for chooser encoder 1 checking data or sub-encoders 2 checking datas, a selector C (48) who is used to select the soft information data (deinterleaving) or the soft information data that interweaves;
Signal through separating card punch (41) output is connected respectively to memory A (42a), memory B (42b), memory C (42c); From memory A (42a) output two-way information, the one road is connected to selector A (46), and another road outputs to selector A (46) again behind first interleaver (43); Export a signal respectively to selector B (47) from memory B (42b) and memory C (42c); Export a soft information data to memory D (42d) from the computing unit (49) that produces new soft information data, its output signal is connected to selector C (48) behind first deinterleaver (44) or second interleaver (45); These three selector signals are input to computing unit (49), the soft data signal of its output or feed back to memory D (42d), or directly by exporting through hard decision unit (51) judgement back again behind second deinterleaver (50).
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| CNB001195093A CN1157854C (en) | 2000-07-25 | 2000-07-25 | High-speed Turbo code decoder |
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| CNB001195093A CN1157854C (en) | 2000-07-25 | 2000-07-25 | High-speed Turbo code decoder |
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Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6973579B2 (en) | 2002-05-07 | 2005-12-06 | Interdigital Technology Corporation | Generation of user equipment identification specific scrambling code for the high speed shared control channel |
| JP4131680B2 (en) * | 2003-06-09 | 2008-08-13 | 松下電器産業株式会社 | Turbo decoder |
| ATE400089T1 (en) * | 2003-12-22 | 2008-07-15 | Koninkl Philips Electronics Nv | SISO DECODER WITH SUBBLOCK PROCESSING AND SUBBLOCK BASED STOP CRITERION |
| CN100438345C (en) * | 2005-03-30 | 2008-11-26 | 华为技术有限公司 | Interlaced device |
| CN100426681C (en) * | 2005-05-10 | 2008-10-15 | 华为技术有限公司 | TURBO coding method and coding apparatus |
| US7890847B2 (en) * | 2007-03-09 | 2011-02-15 | Mediatek Inc. | Apparatus and method for calculating error metrics in a digital communication system |
| CN100369403C (en) * | 2006-02-20 | 2008-02-13 | 东南大学 | Parallel realizing method accepted by iterative detection decoding of wireless communication system |
| CN103095392B (en) * | 2011-10-31 | 2016-06-01 | 扬智电子科技(上海)有限公司 | Iterative decoding method and communicator thereof |
| CN103840842A (en) * | 2014-03-05 | 2014-06-04 | 华为技术有限公司 | Encoder |
| CN103888153A (en) * | 2014-03-13 | 2014-06-25 | 浙江大学城市学院 | Method and device for improving Turbo code MAP decoding performance |
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