CN115758699B - Key graph rapid screening method and device oriented to full-chip light source mask optimization - Google Patents
Key graph rapid screening method and device oriented to full-chip light source mask optimization Download PDFInfo
- Publication number
- CN115758699B CN115758699B CN202211398324.6A CN202211398324A CN115758699B CN 115758699 B CN115758699 B CN 115758699B CN 202211398324 A CN202211398324 A CN 202211398324A CN 115758699 B CN115758699 B CN 115758699B
- Authority
- CN
- China
- Prior art keywords
- slice
- mask
- light source
- defect
- photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Preparing Plates And Mask In Photomechanical Process (AREA)
Abstract
The invention discloses a key graph rapid screening method and device for full-chip light source mask optimization. Belonging to the field of semiconductor computing lithography. According to the invention, by carrying out flattening equal-size segmentation on the full-chip pattern and combining a lithography imaging model with high-efficiency approximation and an SMO flow based on lithography complexity and slicing defect region classification, the key pattern for optimizing the full-chip light source mask can be rapidly and accurately screened or obtained while complex screening rule design or huge pattern spectrum analysis work is avoided. According to the photoetching imaging flow, the invention simplifies the specificity of each component module on the premise of ensuring qualitative description of the characteristics of each module.
Description
Technical Field
The invention belongs to the field of semiconductor computing lithography, and particularly relates to a method and a device for rapidly screening key patterns for optimizing a full-chip light source mask.
Background
With the development of information science and technology, the critical dimensions of semiconductor Integrated Circuit (IC) devices are continuously reduced, and the optical proximity effect of a lithography imaging system is more remarkable. The photoetching machine is an optical imaging system with diffraction limit, and due to the characteristic of hardware stepwise updating, various photoetching Resolution Enhancement Technologies (RET) based on computational photoetching are generated in face of challenges of the photoetching pattern transfer fidelity and the sharp reduction of photoetching process windows generated by continuously rising IC manufacturing technology nodes.
Common lithographic resolution enhancement techniques are mainly Optical Proximity Correction (OPC), source Optimization (SO), off-axis illumination (OAI), sub-resolution assist pattern (SRAF), phase Shift Mask (PSM), etc. The above lithography resolution enhancement techniques are mostly optimized for only the light source shape, mask pattern or mask phase to accomplish the correction of part of the optical proximity effect. In contrast, the combined optimization of light Source Mask (SMO) technique as a combination of SO and OPC techniques, which enables simultaneous optimization of illumination source and mask patterns, has a higher degree of freedom of optimization, has become the most widely used lithographic resolution enhancement technique in 28nm and more advanced IC fabrication nodes
The optimization speed of RET technology is a critical factor in determining the lithographic manufacturing process and throughput. Although the SMO technology has extremely high optimization degree of freedom, the SMO technology has the defects of huge calculation amount, low optimization efficiency and the like when facing to full-chip optimization.
In order to improve the optimization efficiency and reduce the optimization difficulty, a representative key graph needs to be screened out by utilizing a graph screening technology. The traditional screening method based on manpower is gradually eliminated by the industry because the screening method has high requirements on technical experience of operators and is not suitable for optimizing large-scale integrated circuits. The screening method based on graph clustering is to preset the number of clusters of the graph clustering, and select graphs with specific characteristics to serve as SMO key graphs according to the designed ordering method. The pattern screening method can remove a large number of patterns with repeated characteristics, but the pattern clustering and the ordering rule design flow are complex and tedious. With the development of signal processing technology, a screening method based on spectrum analysis is slow in the brand-new corner. The method designs corresponding coverage rules according to main frequency information of the patterns, searches representative characterization frequencies according to coverage relations, and screens out key patterns with the representative characterization frequencies. Although the key graph screening method using spectrum analysis can effectively improve the optimized process window, with the rising of chip process manufacturing nodes, the complexity and the density of the graph are greatly increased, and the spectrum analysis workload for the full-chip graph is huge and cannot be applied to engineering software.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide a method and a device for rapidly screening key patterns for optimizing full-chip light source masks, and aims to solve the problem of huge spectrum analysis workload when the conventional key pattern screening method is used for full-chip layout patterns.
In order to achieve the above object, in a first aspect, the present invention provides a method for fast screening critical patterns for optimizing a full-chip light source mask, where the method is applied to a management node of a distributed computing cluster, and includes:
s1, setting the size of a slice, the proportion of the slices used for graphic screening, the number of SMO key graphic screening process levels, the slice duty ratio coefficient under each process level, the defect level and the sub-slice duty ratio coefficient of each defect level; generating light source patterns with different complexity degrees according to the flow level; loading a full-chip mask layout, and slicing the full-chip mask layout according to the set slice size to obtain a slice set C total Randomly selecting slices with set proportion from the above to obtain a mask slice set C Init ；
S2, initializing a flow grade i=1;
s3, slicing the mask into a set C init The flow level i and the light source graph S corresponding to the flow level i i Distributing the defect grade division rule to each idle computing node in the distributed computing cluster to carry out SMO key graph screening distributed computing under grade i;
s4, receiving defect sub-slices of all defect levels under the process level i returned by all computing nodes in the distributed computing cluster, classifying graphs in the defect sub-slices of the same defect level under the process level i, and obtaining a plurality of key graph sets G ij Mask slice set C Init Updated to the current mask slice set C Init And all key graphics set G ij Is the difference set of (2);
s5, judging whether the current mask slice is the last mask slice in the distributed computing cluster, if so, entering S6, otherwise, entering S3;
s6, judging whether SMO flows under all flow levels are completed, if not, updating the flow level i=i+1 to update the mask slice set C Init And a flow class i, entering S3; if yes, according to the flow level duty ratio coefficient and the sub-slice duty ratio coefficient of each defect level, randomly selecting a key graph set G of the corresponding level ij Selecting corresponding number of graphics to be combined into a final key graphics set G final 。
Preferably, the generating the light source graph under each flow level is specifically as follows:
(1) A circular light source, an annular light source or a C-shaped multistage light source is adopted, the polarization state of the multistage light source is set to be a non-polarization state, and the wavelength is set to be any wavelength in the deep ultraviolet or extreme ultraviolet band range;
(2) According to the slice duty ratio coefficient of each flow level, performing sparse sampling on the light source in different degrees by adopting an inverse interpolation method to obtain a light source approximation model;
wherein S is i The light source points s after sparse sampling under the process level i ij N is the original light source point i For the sparse sampling multiple under the process level i, the slice duty ratio coefficient alpha under each process level i Rise and fall, i.e. n i ∝1/α i 。
Preferably, the defect levels are classified according to the defect type and EPE size, and the higher the defect level or the larger the EPE, the larger the level defect duty factor.
In order to achieve the above object, in a second aspect, the present invention provides a method for simulating light intensity distribution inside a photoresist, the method comprising:
converting the mask slice graph into a binary graph by using a bipolar mask model, and convolving the binary graph with a Gaussian convolution kernel to obtain a mask approximation model;
constructing a pupil by adopting an ideal pupil function, wherein the threshold NA is not lower than 0.95, and obtaining a pupil approximation model;
and combining the light source pattern, the mask approximation model and the pupil approximation model, and obtaining the light intensity distribution inside the photoresist by using an Abbe imaging formula.
In order to achieve the above objective, in a third aspect, the present invention provides a method for fast screening critical patterns for optimizing a full-chip light source mask, where the method is applied to a computing node of a distributed computing cluster, and includes:
T1.receiving the allocated mask slice, the flow level i and the light source graph S under the flow level i i Defect grade;
t2, constructing the internal light intensity distribution of the simulated photoresist of the mask slice under the process level i by using the method of the second aspect, substituting the internal light intensity distribution of the photoresist into a photoresist approximate model, and extracting the simulated outline of the photoresist of the slice through a set threshold value;
and T3, comparing the extracted photoresist simulation contour with an actual mask slice graph, and if the SMO flow convergence condition is not met, entering into T4; if the SMO flow convergence condition is met, entering T6;
t4, judging whether the extracted photoresist simulation contour meets the light source optimization convergence condition, and if so, entering into T5; if not, returning to T2 after light source optimization is carried out;
t5, judging whether the extracted photoresist simulation contour meets the mask optimization convergence condition, if so, entering into T6; if not, mask pattern optimization is carried out, and T2 is returned;
t6, judging whether the simulation contour extracted after the SMO process meets the defect slice screening condition, if so, entering into T7; if not, the current grade SMO flow is free of defect slices, the screening is finished, and the current grade SMO flow is set to be in an idle state;
and T7, confirming the key grade of each defect point in the mask slice, cutting out a defect sub-slice containing a key pattern from the mask slice according to the set size of the sub-slice and surrounding the defect point, and transmitting the defect sub-slice to a management node.
Preferably, the substituting the light intensity distribution inside the photoresist into the photoresist approximate model, extracting the photoresist simulation contour of the slice through the set threshold, specifically as follows:
wherein C (x, y) is the photoresist profile, J (x, y) is the photoresist approximate model output pattern intensity distribution, I (x, y) is the photoresist internal light intensity distribution, sig [ ] is a Sigmoid function, T is the photoresist reaction threshold, and alpha is the photoresist model experience parameter, and is set according to the actual process conditions.
To achieve the above object, in a fourth aspect, the present invention provides a computer-readable storage medium storing a computer program comprising program instructions which, when executed by a processor, cause the processor to perform the method according to the first aspect; alternatively, performing the method as described in the second aspect; alternatively, the method according to the third aspect is performed.
To achieve the above object, in a fifth aspect, the present invention provides an apparatus for rapid screening of key graphics, comprising: a processor and a memory; the memory is used for storing computer execution instructions; the processor is configured to execute the computer-executable instructions such that the method according to the first aspect is performed.
To achieve the above object, in a sixth aspect, the present invention provides an apparatus for rapid screening of key graphics, comprising: a processor and a memory; the memory is used for storing computer execution instructions; the processor is configured to execute the computer-executable instructions such that the method according to the third aspect is performed.
In general, the above technical solutions conceived by the present invention have the following beneficial effects compared with the prior art:
(1) The invention provides a key pattern rapid screening method and device for full-chip light source mask optimization, which are used for realizing rapid and accurate screening or acquisition of the key pattern for full-chip light source mask optimization while avoiding complex screening rule design or huge pattern spectrum analysis work by carrying out flattening and other size segmentation on the full-chip pattern and combining a photoetching imaging model with high-efficiency approximation and an SMO (surface-mounted optical imaging) process based on photoetching complexity and slicing defect area classification.
(2) The invention provides a photoresist internal light intensity distribution simulation method, which is used for simplifying the specificity of each component module on the premise of ensuring qualitative description of the characteristics of each module according to a photoetching imaging flow. The key pattern screening is carried out by utilizing the established high-efficiency approximate photoetching imaging model, so that the accuracy of key pattern extraction in the whole chip range based on a simple and rapid light source mask optimization process can be ensured, and the key pattern screening efficiency in the whole chip range can be effectively improved.
Drawings
Fig. 1 is a flowchart of a method for fast screening key patterns for optimizing full-chip light source masks, which is provided by an embodiment of the invention.
FIG. 2 is a flow chart of a high-efficiency approximate lithography imaging model construction provided by an embodiment of the invention.
Fig. 3 is a schematic diagram of classifying key graphics according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The invention provides a key graph rapid screening method for full-chip light source mask optimization, which is applied to a management node of a distributed computing cluster and comprises the following steps:
s1, receiving settings of the sizes of the slices, the proportion of the slices for graphic screening, the number of SMO key graphic screening process levels, the slice duty ratio coefficients under each process level, the defect levels and the sub-slice duty ratio coefficients of each defect level; generating light source patterns with different complexity degrees according to the flow level; loading a full-chip mask layout, and slicing the full-chip mask layout according to the set slice size to obtain a slice set C total Randomly selecting slices with set proportion from the above to obtain a mask slice set C Init 。
Preferably, the generating the light source graph under each flow level is specifically as follows:
(1) A circular light source, an annular light source or a C-shaped multistage light source is adopted, the polarization state of the multistage light source is set to be a non-polarization state, and the wavelength is set to be any wavelength in the deep ultraviolet or extreme ultraviolet band range;
(2) According to the slice duty ratio coefficient of each flow level, performing sparse sampling on the light source in different degrees by adopting an inverse interpolation method to obtain a light source approximation model;
wherein S is i The light source points s after sparse sampling under the process level i ij N is the original light source point i For the sparse sampling multiple under the process level i, the slice duty ratio coefficient alpha under each process level i Rise and fall, i.e. n i ∝1/α i 。
Preferably, the defect levels are classified according to the defect type and EPE size, and the higher the defect level or the larger the EPE, the larger the level defect duty factor. For example, EPE values range from 0 to inf. The EPE size is divided into: EPE is between 0 and 5, and gives a defect grade of 1 and a proportion coefficient beta 1 The method comprises the steps of carrying out a first treatment on the surface of the EPE is between 5 and 15, and the defect grade 2 and the proportion coefficient beta are given 2 The method comprises the steps of carrying out a first treatment on the surface of the And so on.
Step s2, initializing a flow level i=1.
S3, slicing the mask into a set C Init The flow level i and the light source graph S corresponding to the flow level i i And distributing the defect grading rule to each idle computing node in the distributed computing cluster to carry out SMO key graph screening distributed computing under the grade i.
S4, receiving defect sub-slices of all defect levels under the process level i returned by all computing nodes in the distributed computing cluster, classifying patterns in the defect sub-slices of the same defect level under the process level i, and obtaining a plurality of key pattern sets G ij Mask slice set C Init Updated to the current mask slice set C Init And all key graphics set G ij Is a difference set of (c).
S5, judging whether the current mask slice is the last mask slice in the distributed computing cluster, if so, entering S6, otherwise, entering S3.
Step S6, judging whether SMO flows under all flow levels are completed, if not, updating the flow level i=i+1 to update the mask slice set C Init And a flow class i, entering S3; if yes, according to the flow level duty ratio coefficient and the sub-slice duty ratio coefficient of each defect level, randomly selecting a key graph set G of the corresponding level ij Selecting corresponding number of graphics to be combined into a final key graphics set G final 。
The invention provides a key graph rapid screening method for full-chip light source mask optimization, which is applied to computing nodes of a distributed computing cluster and comprises the following steps:
step T1, receiving the assigned mask slice, process level i, and light source pattern S under the process level i i Defect grade.
And step T2, constructing the light intensity distribution in the simulation photoresist of the mask slice under the process level i, substituting the light intensity distribution in the photoresist into a photoresist approximate model, and extracting the photoresist simulation contour of the slice through a set threshold value.
The invention provides a method for simulating light intensity distribution in photoresist, which comprises the following steps: converting the mask slice graph into a binary graph by using a bipolar mask model, and convolving the binary graph with a Gaussian convolution kernel to obtain a mask approximation model; constructing a pupil by adopting an ideal pupil function, wherein the threshold NA is not lower than 0.95, and obtaining a pupil approximation model; and combining the light source pattern, the mask approximation model and the pupil approximation model, and obtaining the light intensity distribution inside the photoresist by using an Abbe imaging formula.
Preferably, the substituting the light intensity distribution inside the photoresist into the photoresist approximate model, extracting the photoresist simulation contour of the slice through the set threshold, specifically as follows:
wherein C (x, y) is the photoresist profile, J (x, y) is the photoresist approximate model output pattern intensity distribution, I (x, y) is the photoresist internal light intensity distribution, sig [ ] is a Sigmoid function, T is the photoresist reaction threshold, and alpha is the photoresist model experience parameter, and is set according to the actual process conditions.
Step T3, comparing the extracted photoresist simulation contour with the actual mask slice graph, and if the SMO flow convergence condition is not met, entering into T4; if the SMO flow convergence condition is met, entering T6.
Step T4, judging whether the extracted photoresist simulation contour meets the light source optimization convergence condition, and if so, entering into a step T5; if not, returning to T2 after light source optimization is performed.
Step 5, judging whether the extracted photoresist simulation contour meets the mask optimization convergence condition, and if so, entering into a step 6; if not, mask pattern optimization is performed, and T2 is returned.
Step T6, judging whether the simulation contour extracted after the SMO process meets the defect slice screening condition, and if so, entering into a step T7; if not, the current grade SMO flow is free of defect slices, the screening is ended, and the current grade SMO flow is set to be in an idle state.
And step T7, confirming the key grade of each defect point in the mask slice, cutting out a defect sub-slice containing a key pattern from the mask slice according to the set size of the sub-slice and surrounding the defect point, and transmitting the defect sub-slice to a management node.
The present invention provides a computer readable storage medium storing a computer program comprising program instructions which, when executed by a processor, cause the processor to perform the above-described method.
The invention provides a device for rapidly screening key graphics, which comprises: a processor and a memory; the memory is used for storing computer execution instructions; the processor is configured to execute the computer-executable instructions such that the method as described above is performed.
Fig. 1 is a flowchart of a method for fast screening key patterns for optimizing full-chip light source masks, which is provided by an embodiment of the invention. As shown in fig. 1, the entire distributed computing cluster works as follows:
and step 1, loading the full-chip mask layout on a management node of the distributed computing cluster. Dividing the full-chip mask layout into a plurality of slices according to the set slice size (set by a user according to the characteristics of the mask layout such as the graphic complexity, the density and the like), and marking all slice sets as C Total The method comprises the steps of carrying out a first treatment on the surface of the From C total Randomly selecting a slice set C corresponding to a proportion C (set by a user) for SMO key graph screening Init 。
|C Init |＝c|C Total |
A circular light source, an annular light source or a C-shaped multi-stage light source is adopted, so that the difficulty in realizing the light source is reduced; the polarization state is set as a non-polarization state, the wavelength is set as any wavelength (such as 193 nm) in the deep ultraviolet or extreme ultraviolet band range, the light source is subjected to sparse sampling in different degrees by adopting an inverse interpolation method according to a photoetching complexity grading strategy, the number of light source points is reduced, and the key pattern screening efficiency is improved. Under the SMO key graph screening process class i, the light source sparse sampling method comprises the following steps:
wherein S is i The light source points s after sparse sampling under the process level i ij N is the original light source point i For the sparse sampling multiple under the process level i, the ratio coefficient of the slice under each process level is increased and is reduced, namely n i ∝1/α i 。
The critical level j of the pattern can be classified according to the defect type and EPE size, the higher the defect level or the larger the EPE, the defect duty factor beta of the level j The larger and
wherein m is the total number of defect levels.
Step 2, on the management node of the distributed computing cluster, generating light source patterns S with different complexity degrees according to the number k (user setting) of SMO key pattern screening flow grades i (i=1, …, k); in the SMO key graph screening process, a corresponding process grade i is given according to the complexity of the light source, and a corresponding slice duty ratio coefficient alpha under the process grade is set i (i＝1,…,k；0≤α i Not more than 1), and
step 3, on the management node of the distributed computing cluster, a slice set C for SMO key graph screening is carried out Init And distributing the SMO key graph to each idle computing node in the distributed computing cluster, and screening the distributed computing for the SMO key graph under the level i.
And 4, in a certain computing node of the distributed computing cluster, simulating the light intensity distribution inside the photoresist by using the constructed high-efficiency approximate photoetching imaging model with the flow level i, and extracting the simulation contour of the sliced photoresist. FIG. 2 is a flow chart of a high-efficiency approximate lithography imaging model construction provided by an embodiment of the invention. As shown in fig. 2, the construction process is as follows:
and 4.1, dividing the high-efficiency approximate photoetching imaging model into a light source approximate module, a mask approximate module, a pupil approximate module and a photoresist approximate module according to the photoetching imaging flow.
And 4.2, constructing and transmitting the light source for the management node by the light source approximation module.
And 4.3, a mask approximation module construction process is carried out by taking a bipolar mask model as a basis and carrying out convolution with a Gaussian convolution kernel to obtain a mask near field:
wherein M is NF (x, y) outputting a mask near field for the approximate mask model; m is M 2v (x, y) is the use of doubleA binary pattern for converting the mask pattern by the polar mask model; k (k) Gauss (x, y) is a gaussian convolution kernel.
Step 4.4, the pupil approximation module adopts an ideal pupil function, and NA can be selected to be a larger value, for example, na=0.95:
wherein P (f) x ,f y ) Is an ideal pupil function.
Step 4.5, combining the light source approximation model, the mask approximation model and the pupil approximation model, and obtaining the light intensity distribution I (x, y) inside the photoresist by using an Abbe imaging formula:
and 4.6, distributing the light intensity inside the photoresist into the photoresist approximate model by using the photoresist approximate model as a hard threshold model based on a Sigmoid function, and completing the extraction of the photoresist outline through a set threshold. Wherein the photoresist approximation model outputs a pattern intensity distribution J (x, y) of:
wherein sig is Sigmoid function, T is photoresist reaction threshold, alpha is photoresist model experience parameter, and is set according to actual process condition.
The photoresist profile C (x, y) can be extracted by the following procedure:
step 5, in a certain computing node of the distributed computing cluster, comparing the extracted photoresist simulation contour with the input mask slice graph, and if the simple and rapid SMO flow convergence condition is not met, entering the next step; if the simple and fast SMO procedure is satisfied, step 8 is entered.
The SMO flow convergence condition is that any one of the following conditions is satisfied: 1) The total number of SMO optimization iterations reaches a user-set threshold Iter SMO The method comprises the steps of carrying out a first treatment on the surface of the 2) The edge placement error EPE (Edge Placement Error) between the simulated extraction profile and the design mask pattern is less than the user-set SMO process error threshold EPE SMO 。
Step 6, judging whether the extracted photoresist simulation contour meets the light source optimization convergence condition in a certain calculation node of the distributed calculation cluster, and if so, entering the next step; if not, carrying out optimization on the corresponding light source, and returning to the step 4.
Light source optimization methods include, but are not limited to: light source optimization based on covariance matrix self-adaptive evolution, light source optimization based on light source partial sampling and the like.
The light source optimization convergence condition is that any one of the following conditions is satisfied: 1) The light source optimization iteration number reaches the SMO flow optimization iteration number threshold Iter SMO The method comprises the steps of carrying out a first treatment on the surface of the 2) The EPE between the simulated extraction profile and the design mask pattern is less than the user-set light source optimization error threshold EPE Source The method comprises the steps of carrying out a first treatment on the surface of the 3) The EPE change before and after light source optimization is smaller than the light source optimization error change threshold delta EPE set by a user Source 。
Mask optimization methods include, but are not limited to: mask optimization based on bilateral evolution of mask patterns, mask optimization based on discrete cosine transform and the like.
The mask optimization convergence condition is that any one of the following conditions is satisfied: 1) The mask optimization iteration number reaches the SMO flow optimization iteration number threshold Iter SMO The method comprises the steps of carrying out a first treatment on the surface of the 2) The EPE between the simulated extraction profile and the design mask pattern is less than the user-set mask optimization error threshold EPE Mask The method comprises the steps of carrying out a first treatment on the surface of the 3) Small EPE error change before and after mask optimizationSetting mask optimization error variation threshold deltaepe by user Mask 。
Step 8, in a certain computing node of the distributed computing cluster, judging whether the simulation contour extracted after the simple and rapid SMO process meets the defect slice screening condition, and if so, entering the next step; if not, go to step 11.
The defect slice screening condition is that any one of the following conditions is satisfied: 1) The EPE between the simulated extraction profile and the design mask pattern is less than the user-set critical pattern error threshold EPE CP The method comprises the steps of carrying out a first treatment on the surface of the 2) The simulated extraction profile has defects such as Hard-bridge, pin, etc.
And 9, in a certain computing node of the distributed computing cluster, setting the size of the sub-slice according to a user, and cutting out a corresponding graph from the current slice around the defect point.
Step 10, screening the process level i and the key level j of the graph according to the SMO key graph corresponding to the sub-slice on the management node of the distributed computing cluster, and classifying the key graph in the defective sub-slice with the same level into G ij 。
Fig. 3 is a schematic diagram of classifying key graphics according to an embodiment of the present invention. As shown in FIG. 3, the entire full-chip mask layout is in accordance with a duty cycle α 1 ～α 4 Divided into four slices, the upper left slice being taken as an example for illustration. Two defects exist in the slice, which correspond to key grades 1 and 3 respectively, and a key graph classification G is obtained under a process grade i 11 And G 13 。
After completing the classification of the defective sub-slice pattern, the method is carried out from the initial slice set C Init Removing the current slice to finish a slice set C Init And then proceeds to the next step.
Step 11, on a management node of the distributed computing cluster, judging whether the current slice is the last mask slice in the distributed computing cluster, and if not, returning to the step 3; if yes, go to the next step.
Step 12, on the management node of the distributed computing cluster, judging whether all SMO flows under the photoetching complexity grading are completed, if not, updating the SMO flowsSlice set C Init Inputting the data into a distributed computing cluster, and returning to the step 3 to perform the SMO process of the next photoetching complexity level; if yes, screening flow grades according to SMO key figures of different slices and corresponding figure proportion w under the key grades of the figures ij Random from corresponding level key graphic set G ij Selecting corresponding number of graphics to be combined into a final key graphics set G final ：
w ij ＝α i β j
Wherein k is the number of classification of the photoetching complexity SMO flow, m is the number of classification of the sub-slice defect level, |G ij I and G final I respectively represent the set G ij And G final The number of elements contained in the composition.
It will be readily appreciated by those skilled in the art that the foregoing description is merely a preferred embodiment of the invention and is not intended to limit the invention, but any modifications, equivalents, improvements or alternatives falling within the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (8)
1. A key graph rapid screening method oriented to full-chip light source mask optimization is characterized by being applied to management nodes of a distributed computing cluster and comprising the following steps:
s1, setting the size of a slice, the proportion of the slices used for graphic screening, the number of SMO key graphic screening process levels, the slice duty ratio coefficient under each process level, the defect level and the sub-slice duty ratio coefficient of each defect level; generating light source patterns with different complexity degrees according to the flow level; loading a full-chip mask layout, and slicing the full-chip mask layout according to the set slice size to obtain a slice set C total Randomly selecting slices with set proportion from the above to obtain a mask slice set C Init ；
S2, initializing a flow grade i=1;
s3, slicing the mask into a set C Init The flow level i and the light source graph S corresponding to the flow level i i Distributing the defect grade division rule to each idle computing node in the distributed computing cluster to carry out SMO key graph screening distributed computing under grade i;
s4, receiving defect sub-slices of all defect levels under the process level i returned by all computing nodes in the distributed computing cluster, classifying the patterns in the defect sub-slices of the same defect level under the process level i, and obtaining a plurality of key pattern sets C ij Mask slice set C Init Updated to the current mask slice set C Init And all key graphics set G ij Is the difference set of (2);
s5, judging whether the current mask slice is the last mask slice in the distributed computing cluster, if so, entering S6, otherwise, entering S3;
s6, judging whether SMO flows under all flow levels are completed, if not, updating the flow level i=i+1 to update the mask slice set C Init And a flow class i, entering S3; if yes, according to the flow level duty ratio coefficient and the sub-slice duty ratio coefficient of each defect level, randomly selecting a key graph set G of the corresponding level ij Selecting corresponding number of graphics to be combined into a final key graphics set G final 。
2. The method of claim 1, wherein the generating the light source patterns with different complexity levels according to the flow level comprises:
(1) A circular light source, an annular light source or a C-shaped multi-stage light source is adopted, the polarization state of the light source is set to be a non-polarization state, and the wavelength is set to be any wavelength in the deep ultraviolet or extreme ultraviolet band range;
(2) According to the slice duty ratio coefficient of each flow level, performing sparse sampling on the light source in different degrees by adopting an inverse interpolation method to obtain a light source approximation model;
wherein S is i The light source points s after sparse sampling under the process level i ij N is the original light source point i For the sparse sampling multiple under the process level i, the slice duty ratio coefficient alpha under each process level i Rise and fall, i.e. n i ∝1/α i 。
3. The method of claim 1, wherein the defect levels are classified according to defect type and EPE size, and the higher the defect level or the larger the EPE, the larger the level defect duty factor.
4. A key graph rapid screening method oriented to full-chip light source mask optimization is characterized by being applied to computing nodes of a distributed computing cluster, and comprising the following steps:
t1 receiving the assigned mask slice, flow level i, and light source pattern S under flow level i i Defect grade;
t2, constructing the simulated photoresist internal light intensity distribution of the mask slice under the process level i by using a photoresist internal light intensity distribution simulation method, substituting the photoresist internal light intensity distribution into a photoresist approximate model, and extracting the photoresist simulation contour of the slice through a set threshold value;
and T3, comparing the extracted photoresist simulation contour with an actual mask slice graph, and if the SMO flow convergence condition is not met, entering into T4; if the SMO flow convergence condition is met, entering T6;
t4, judging whether the extracted photoresist simulation contour meets the light source optimization convergence condition, and if so, entering into T5; if not, returning to T2 after light source optimization is carried out;
t5, judging whether the extracted photoresist simulation contour meets the mask optimization convergence condition, if so, entering into T6; if not, mask pattern optimization is carried out, and T2 is returned;
t6, judging whether the simulation contour extracted after the SMO process meets the defect slice screening condition, if so, entering into T7; if not, the current grade SMO flow is free of defect slices, the screening is finished, and the current grade SMO flow is set to be in an idle state;
t7, confirming the key grade of each defect point in the mask slice, cutting out a defect sub-slice containing a key pattern from the mask slice according to the set size of the sub-slice and surrounding the defect point, and transmitting the defect sub-slice to a management node;
the method for simulating the light intensity distribution in the photoresist comprises the following steps:
converting the mask slice graph into a binary graph by using a bipolar mask model, and convolving the binary graph with a Gaussian convolution kernel to obtain a mask approximation model;
constructing a pupil by adopting an ideal pupil function, wherein the threshold NA is not lower than 0.95, and obtaining a pupil approximation model;
and combining the light source pattern, the mask approximation model and the pupil approximation model, and obtaining the light intensity distribution inside the photoresist by using an Abbe imaging formula.
5. The method for rapid screening of critical patterns according to claim 4, wherein the substituting the light intensity distribution inside the photoresist into the photoresist approximation model extracts the photoresist simulation profile of the slice through a set threshold, specifically as follows:
wherein C (x, y) is the photoresist profile, J (x, y) is the photoresist approximate model output pattern intensity distribution, I (x, y) is the photoresist internal light intensity distribution, sig [ ] is a Sigmoid function, T is the photoresist reaction threshold, and alpha is the photoresist model experience parameter, and is set according to the actual process conditions.
6. A computer readable storage medium, characterized in that the computer readable storage medium stores a computer program comprising program instructions which, when executed by a processor, cause the processor to perform the method of any of claims 1-3; alternatively, the method of claim 4 or 5 is performed.
7. An apparatus for rapid screening of key graphics, comprising: a processor and a memory; the memory is used for storing computer execution instructions; the processor configured to execute the computer-executable instructions such that the method of any of claims 1-3 is performed.
8. An apparatus for rapid screening of key graphics, comprising: a processor and a memory; the memory is used for storing computer execution instructions; the processor configured to execute the computer-executable instructions such that the method of claim 4 or 5 is performed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211398324.6A CN115758699B (en) | 2022-11-09 | 2022-11-09 | Key graph rapid screening method and device oriented to full-chip light source mask optimization |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211398324.6A CN115758699B (en) | 2022-11-09 | 2022-11-09 | Key graph rapid screening method and device oriented to full-chip light source mask optimization |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115758699A CN115758699A (en) | 2023-03-07 |
| CN115758699B true CN115758699B (en) | 2023-06-20 |
Family
ID=85368567
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211398324.6A Active CN115758699B (en) | 2022-11-09 | 2022-11-09 | Key graph rapid screening method and device oriented to full-chip light source mask optimization |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115758699B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117454831B (en) * | 2023-12-05 | 2024-04-02 | 武汉宇微光学软件有限公司 | Mask pattern optimization method and system and electronic equipment |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101644890A (en) * | 2009-09-03 | 2010-02-10 | 浙江大学 | Optical adjacent correction method suitable for pixel array of image sensor |
| CN102054092A (en) * | 2009-10-28 | 2011-05-11 | Asml荷兰有限公司 | Pattern selection for full-chip source and mask optimization |
| CN102224459A (en) * | 2008-11-21 | 2011-10-19 | Asml荷兰有限公司 | Fast freeform source and mask co-optimization method |
| CN105825036A (en) * | 2016-06-07 | 2016-08-03 | 中国科学院微电子研究所 | Method and system for optimizing layout design rules |
| WO2020078844A1 (en) * | 2018-10-19 | 2020-04-23 | Asml Netherlands B.V. | Method to create the ideal source spectra with source and mask optimization |
| CN112578644A (en) * | 2020-12-08 | 2021-03-30 | 北京理工大学 | Self-adaptive full-chip light source optimization method and system |
| CN113792866A (en) * | 2021-10-29 | 2021-12-14 | 智腾科技股份有限公司 | Level set mask optimization method of distance regular level set and convolutional neural network |
| CN114326287A (en) * | 2021-11-30 | 2022-04-12 | 华中科技大学 | Separated strict mask model and photoresist model modeling and calibration method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102269925B (en) * | 2011-09-09 | 2012-10-03 | 北京理工大学 | Phase-shift mask optimizing method based on Abbe vector imaging model |
| CN111624850B (en) * | 2020-06-08 | 2021-07-27 | 中国科学院上海光学精密机械研究所 | Key graph screening method for full-chip light source mask optimization |
-
2022
- 2022-11-09 CN CN202211398324.6A patent/CN115758699B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102224459A (en) * | 2008-11-21 | 2011-10-19 | Asml荷兰有限公司 | Fast freeform source and mask co-optimization method |
| CN101644890A (en) * | 2009-09-03 | 2010-02-10 | 浙江大学 | Optical adjacent correction method suitable for pixel array of image sensor |
| CN102054092A (en) * | 2009-10-28 | 2011-05-11 | Asml荷兰有限公司 | Pattern selection for full-chip source and mask optimization |
| CN105825036A (en) * | 2016-06-07 | 2016-08-03 | 中国科学院微电子研究所 | Method and system for optimizing layout design rules |
| WO2020078844A1 (en) * | 2018-10-19 | 2020-04-23 | Asml Netherlands B.V. | Method to create the ideal source spectra with source and mask optimization |
| CN112578644A (en) * | 2020-12-08 | 2021-03-30 | 北京理工大学 | Self-adaptive full-chip light source optimization method and system |
| CN113792866A (en) * | 2021-10-29 | 2021-12-14 | 智腾科技股份有限公司 | Level set mask optimization method of distance regular level set and convolutional neural network |
| CN114326287A (en) * | 2021-11-30 | 2022-04-12 | 华中科技大学 | Separated strict mask model and photoresist model modeling and calibration method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115758699A (en) | 2023-03-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11113445B2 (en) | Hotspot detection based on litho-aware machine learning | |
| US8843859B2 (en) | Layout content analysis for source mask optimization acceleration | |
| US20050188338A1 (en) | System for designing integrated circuits with enhanced manufacturability | |
| US20070011648A1 (en) | Fast systems and methods for calculating electromagnetic fields near photomasks | |
| US8650511B2 (en) | Lithography performance check methods and apparatus | |
| US11762283B2 (en) | Inverse lithography and machine learning for mask synthesis | |
| US20120054694A1 (en) | Aerial Image Signatures | |
| CN115758699B (en) | Key graph rapid screening method and device oriented to full-chip light source mask optimization | |
| CN115470741B (en) | Method, electronic device and storage medium for light source mask co-optimization | |
| CN111338179B (en) | Full-chip light source mask optimization key graph screening method based on multi-width representation | |
| Meng et al. | Machine learning models for edge placement error based etch bias | |
| CN114509912A (en) | Mask optimization method, mask optimization device and electronic equipment | |
| CN111505898A (en) | OPC correction method combined with graph matching | |
| CN108107670B (en) | Method for improving OPC precision of through hole layer | |
| CN116068864A (en) | Sub-resolution auxiliary feature pattern generation method capable of improving definition of photoetching pattern | |
| US9857693B1 (en) | Lithography model calibration via cache-based niching genetic algorithms | |
| US11704471B2 (en) | Three-dimensional mask simulations based on feature images | |
| US10151971B2 (en) | System for and method of seeding an optical proximity correction (OPC) process | |
| Pang et al. | Source mask optimization (SMO) at full chip scale using inverse lithography technology (ILT) based on level set methods | |
| CN111611761B (en) | Method, apparatus and computer readable storage medium for generating circuit layout pattern | |
| US20240078366A1 (en) | Circuit design adjustments using redundant nodes | |
| US11657207B2 (en) | Wafer sensitivity determination and communication | |
| Duan et al. | Design technology co-optimization for N14 Metal1 layer | |
| US20230079453A1 (en) | Mask corner rounding effects in three-dimensional mask simulations using feature images | |
| US20210264087A1 (en) | Automatic test pattern generation (atpg) for parametric faults |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |