CN115732437A - Chip packaging structure and preparation method thereof - Google Patents

Abstract

The invention provides a chip packaging structure and a preparation method thereof, wherein the chip packaging structure comprises: the heat dissipation structure is internally provided with a through containing cavity and comprises a first layer of heat dissipation part to an Nth layer of heat dissipation part which are sequentially connected along the direction of a central shaft of the through containing cavity, and any Nth layer of heat dissipation part is of an annular structure; the opening of the accommodating cavity surrounded by the k-1 heat dissipation part is larger than the opening of the accommodating cavity surrounded by the k-1 heat dissipation part; a k-1 step is formed between the k-1 heat dissipation part and the k-1 heat dissipation part; the first chip module is positioned in the accommodating cavity surrounded by the first heat dissipation part; any kth chip module is positioned in the accommodating cavity surrounded by the kth heat radiating part and is arranged opposite to the kth-1 step; the kth chip module is electrically connected with the kth-1 chip module, and the opposite areas of the first chip module and the second chip module are fixedly connected. The chip packaging structure has good reliability and heat dissipation effect.

Description

Chip packaging structure and preparation method thereof

Technical Field

The invention relates to the technical field of electronic packaging, in particular to a chip packaging structure and a preparation method thereof.

Background

The radio frequency system has wide application prospect in the fields of radar, 5G communication, electronic countermeasure and the like, and under the promotion of the miniaturization trend of electronic equipment, the radio frequency system can greatly reduce the volume and the power consumption of the system, simultaneously considers multifunctional integration and intellectualization and continuously improves the system performance. The radio frequency system is combined with a three-dimensional integration technology, and has great potential in the aspects of developing a radio frequency micro system with high performance, miniaturization and low cost.

Along with the integration level of the radio frequency micro system is higher and higher, the number of layers of three-dimensional stacking is more and more, the reliability of the chip packaging structure is poorer in the packaging process, the number of integrated chips is more and more, the functions of the chips are stronger and stronger, and the power consumption of the chips is increased, so that the heat dissipation requirement on the micro system is larger and larger, and the reliability and the heat dissipation capability of the conventional chip packaging structure are poorer.

Disclosure of Invention

Therefore, the technical problem to be solved by the present invention is to overcome the defect of poor reliability and heat dissipation capability of the chip package structure in the prior art, thereby providing a chip package structure and a method for manufacturing the same.

The invention provides a chip packaging structure, comprising: the heat dissipation structure is provided with a through accommodating cavity and comprises a first layer of heat dissipation part to an Nth layer of heat dissipation part which are sequentially connected along the direction of a central shaft of the through accommodating cavity, N is an integer larger than or equal to 2, any nth layer of heat dissipation part is of an annular structure, and N is an integer larger than or equal to 1 and smaller than or equal to N; the opening of the accommodating cavity surrounded by the kth layer of heat dissipation part is larger than the opening of the accommodating cavity surrounded by the kth-1 layer of heat dissipation part; a k-1 step is formed between the kth layer of heat dissipation part and the k-1 layer of heat dissipation part; k is an integer greater than or equal to 2 and less than or equal to N; the first chip module is positioned in the accommodating cavity surrounded by the first heat dissipation part; any kth chip module is positioned in the accommodating cavity surrounded by the kth heat radiating part and is arranged opposite to the kth-1 step; the kth chip module is electrically connected with the kth-1 chip module, and the opposite areas of the first chip module and the second chip module are fixedly connected.

Optionally, the method further includes: the first edge welding pad to the N-1 edge welding pad, and any k-1 edge welding pad is positioned on the bottom surface of the k-1 step; a k-1 welding piece is arranged on the surface of one side, facing the bottom surface of the k-1 step, of the kth chip module; the (k-1) th weldment is located on the (k-1) th edge pad and is connected with the (k-1) th edge pad.

Optionally, the (k-1) th edge bonding pad is in an annular structure surrounding the accommodating cavity, and the (k-1) th welding piece is in an annular structure corresponding to the (k-1) th edge bonding pad.

Optionally, any jth chip module includes: a jth carrier plate; the jth chip is positioned on the upper surface of the jth carrier plate; the jth conductive connecting piece is positioned on the upper surface of the jth carrier plate and positioned on the side part of the jth chip; a jth solder ball positioned on the surface of one side, away from the jth chip, of the jth carrier plate; the jth plastic packaging layer covers the jth chip and the side wall of the jth conductive connecting piece; the jth top layer bonding pad is positioned on the surface of one side, away from the jth carrier plate, of the jth plastic packaging layer; part of the jth top layer bonding pad is connected with the jth conductive connecting piece; j is an integer greater than or equal to 1 and less than or equal to N-1; the Nth chip module includes: an Nth carrier plate; the Nth chip is positioned on the upper surface of the Nth carrier plate; the Nth conductive connecting piece is positioned on the upper surface of the Nth carrier plate and positioned on the side part of the Nth chip; an Nth solder ball positioned on the surface of one side of the Nth carrier plate, which is far away from the Nth chip; the Nth plastic packaging layer covers the side walls of the Nth chip and the Nth conductive connecting piece; the antenna unit is positioned on the surface of one side, away from the Nth carrier plate, of the Nth plastic packaging layer; the antenna unit is connected with the Nth conductive connecting piece; and the jth top layer bonding pad is connected with the jth +1 th welding ball.

Optionally, the method further includes: and the nth layer of heat-conducting glue is positioned between the side wall of any nth chip module and the inner side wall of the nth heat radiating part.

Optionally, the thickness of the nth layer of heat-conducting glue is 50um-100um.

Optionally, the heat dissipation structure includes: copper, aluminum or ceramic.

The invention also provides a preparation method of the chip packaging structure, which comprises the following steps: providing a heat dissipation structure, wherein the heat dissipation structure is provided with a through accommodating cavity, the heat dissipation structure comprises a first layer of heat dissipation part to an Nth layer of heat dissipation part which are sequentially connected along the direction of a central shaft of the through accommodating cavity, N is an integer greater than or equal to 2, any Nth layer of heat dissipation part is in an annular structure, and N is an integer greater than or equal to 1 and less than or equal to N; the opening of the accommodating cavity surrounded by the k-1 heat dissipation part is larger than the opening of the accommodating cavity surrounded by the k-1 heat dissipation part; a k-1 step is formed between the k-1 heat dissipation part and the k-1 heat dissipation part; k is an integer greater than or equal to 2 and less than or equal to N; providing a first chip module to an Nth chip module; placing the first chip module in an accommodating cavity surrounded by the first heat dissipation part; placing any kth chip module in an accommodating cavity surrounded by the kth heat dissipation part and opposite to the kth-1 step; the kth chip module is electrically connected with the kth-1 chip module, and the opposite areas of the first chip module and the second chip module are fixedly connected.

Optionally, a carrier plate is provided, a carrier plate hole is formed in a middle area of the carrier plate, and an opening of the carrier plate hole is smaller than an opening of the accommodating cavity surrounded by the first heat dissipation portion; placing a heat dissipation structure on the carrier plate, wherein a first layer of heat dissipation part to an Nth layer of heat dissipation part are arranged on the carrier plate from bottom to top; the carrier plate hole is positioned at the bottom of the accommodating cavity surrounded by the first heat dissipation part and is communicated with the accommodating cavity; a bottom step is formed between the carrier plate and the first layer of heat dissipation part; in the step of placing the first chip module in the accommodating cavity surrounded by the first heat dissipation part, the first chip module is arranged opposite to the bottom step; after the first chip module is placed in the accommodating cavity surrounded by the first heat dissipation part, any k chip module is placed in the accommodating cavity surrounded by the k heat dissipation part; and after the Nth chip module is placed in the accommodating cavity surrounded by the Nth heat dissipation part, removing the carrier plate.

Optionally, the heat dissipation structure further includes: first to N-1 edge pads; any (k-1) th edge welding pad is positioned on the bottom surface of the (k-1) th step; a k-1 edge weldment is arranged on one side surface of any k chip module, which faces to the bottom surface of the k-1 step; and in the step of placing any kth chip module in the accommodating cavity surrounded by the kth heat dissipation part, arranging the kth-1 edge welding piece on the kth-1 edge welding pad and connecting the kth-1 edge welding pad with the kth edge welding pad.

Optionally, in the process of placing any nth chip module in the accommodating cavity surrounded by the nth heat sink portion, the method further includes: and an nth layer of heat-conducting glue is formed between the side wall of any nth chip module and the inner side wall of the nth heat radiating part.

The technical scheme of the invention has the following advantages:

the invention provides a chip packaging structure, wherein a through accommodating cavity is arranged in a heat dissipation structure, the heat dissipation structure comprises a first layer of heat dissipation part to an Nth layer of heat dissipation part which are sequentially connected along the direction of a central shaft of the through accommodating cavity, N is an integer larger than or equal to 2, any Nth layer of heat dissipation part is in an annular structure, and N is an integer larger than or equal to 1 and smaller than or equal to N; the opening of the accommodating cavity surrounded by the kth layer of heat dissipation part is larger than the opening of the accommodating cavity surrounded by the kth-1 layer of heat dissipation part; a k-1 step is formed between the k-1 heat dissipation part and the k-1 heat dissipation part; k is an integer greater than or equal to 2 and less than or equal to N; the first chip module is positioned in the accommodating cavity surrounded by the first heat dissipation part; any kth chip module is positioned in the accommodating cavity surrounded by the kth heat dissipation part and is arranged opposite to the kth-1 step, the kth-1 step can carry out prepositioning on the position of the kth chip module, the kth-1 step can also provide structural support for the kth chip module, so that the reliability of the chip packaging structure is improved, the nth heat dissipation part can timely dissipate the heat of the nth chip module, and the heat dissipation effect of the chip packaging structure is improved; the kth chip module is electrically connected with the kth-1 chip module, the kth-1 chip module provides structural support for the kth chip module, the opposite areas of the first chip module and the second chip module are fixedly connected, and the first chip module provides structural support for the second chip module, so that the chip packaging structure is good in reliability. In conclusion, the chip packaging structure has good reliability and heat dissipation effect.

Further, the chip package structure further includes: the first edge welding pad to the N-1 edge welding pad, and any k-1 edge welding pad is positioned on the bottom surface of the k-1 step; a k-1 welding piece is arranged on the surface of one side, facing the bottom surface of the k-1 step, of the kth chip module; the k-1 th welding piece is positioned on the k-1 th edge welding pad and is connected with the k-1 th edge welding pad, and the k-1 th edge welding pad is favorable for firmly connecting the k-1 th chip module with the k-1 th heat dissipation part, so that the reliability of the chip packaging structure can be improved. The (k-1) th edge welding pad is in an annular structure surrounding the accommodating cavity, and the (k-1) th welding piece is in an annular structure corresponding to the (k-1) th edge welding pad. The k-1 edge welding pad and the k-1 welding piece can realize a heat conduction function, so that the heat of the k chip module can be timely transmitted to the k-1 heat dissipation part, and the heat dissipation effect of the chip packaging structure is improved.

Further, the chip package structure further includes: and the nth layer of heat-conducting glue is positioned between the side wall of any nth chip module and the inner side wall of the nth heat radiating part. On one hand, the nth layer of heat-conducting glue is used for connecting the nth chip module with the nth layer of heat dissipation part, so that the connection reliability of the nth chip module and the heat dissipation structure is improved; on the other hand, the nth layer of heat-conducting glue can timely transfer the heat of the nth chip module to the nth layer of heat dissipation part, and the nth layer of heat dissipation part timely dissipates the heat, so that the reliability and the heat dissipation effect of the chip packaging structure are good.

The invention provides a preparation method of a chip packaging structure, wherein a through accommodating cavity is arranged in a heat dissipation structure, the heat dissipation structure comprises a first layer of heat dissipation part to an Nth layer of heat dissipation part which are sequentially connected along the direction of a central shaft of the through accommodating cavity, N is an integer larger than or equal to 2, any Nth layer of heat dissipation part is in a ring structure, and N is an integer larger than or equal to 1 and smaller than or equal to N; the opening of the accommodating cavity surrounded by the k-1 heat dissipation part is larger than the opening of the accommodating cavity surrounded by the k-1 heat dissipation part; a k-1 step is formed between the k-1 heat dissipation part and the k-1 heat dissipation part; k is an integer greater than or equal to 2 and less than or equal to N; placing the first chip module in an accommodating cavity surrounded by the first heat dissipation part; placing any kth chip module in an accommodating cavity surrounded by the kth heat dissipation part and opposite to the kth-1 step; in the preparation process of the chip packaging structure, the k-1 th step can pre-position the position of the k chip module, and the first chip module to the Nth chip module can be sequentially placed in the accommodating cavities surrounded by the first heat dissipation part to the Nth heat dissipation part for primary packaging without multiple packaging, so that the preparation method of the chip packaging structure can improve the reliability of the chip packaging structure; the nth layer of heat dissipation part can dissipate the heat of the nth chip module in time, so that the heat dissipation effect of the chip packaging structure is improved; the kth chip module is electrically connected with the kth-1 chip module, the kth-1 chip module provides structural support for the kth chip module, the opposite areas of the first chip module and the second chip module are fixedly connected, and the first chip module provides structural support for the second chip module, so that the chip packaging structure is good in reliability. In conclusion, the preparation method of the chip packaging structure can improve the reliability and the heat dissipation effect of the chip packaging structure.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a schematic structural diagram of a heat dissipation structure according to an embodiment of the present invention;

fig. 2 is a top view of a heat dissipation structure according to an embodiment of the invention;

fig. 3 is a schematic structural diagram of a chip package structure according to an embodiment of the invention;

fig. 4 is a schematic structural diagram of a second chip module when j is equal to two according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a fifth chip module according to an embodiment of the present invention when N is equal to five;

fig. 6 is a flowchart of a method for manufacturing a chip package structure according to an embodiment of the invention;

fig. 7 to 9 are schematic views illustrating a manufacturing process of a chip package structure according to an embodiment of the invention.

Detailed Description

The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

Example 1

The embodiment provides a chip package structure, including:

the heat dissipation structure is provided with a through accommodating cavity and comprises a first layer of heat dissipation part to an Nth layer of heat dissipation part which are sequentially connected along the direction of a central shaft of the through accommodating cavity, N is an integer larger than or equal to 2, any nth layer of heat dissipation part is of an annular structure, and N is an integer larger than or equal to 1 and smaller than or equal to N; the opening of the accommodating cavity surrounded by the k-1 heat dissipation part is larger than the opening of the accommodating cavity surrounded by the k-1 heat dissipation part; a k-1 step is formed between the k-1 heat dissipation part and the k-1 heat dissipation part; k is an integer greater than or equal to 2 and less than or equal to N;

the first chip module is positioned in the accommodating cavity surrounded by the first heat dissipation part; any kth chip module is positioned in the accommodating cavity surrounded by the kth heat radiating part and is arranged opposite to the kth-1 step; the kth chip module is electrically connected with the kth-1 chip module, and the opposite areas of the first chip module and the second chip module are fixedly connected.

In the chip packaging structure provided by the embodiment, the kth-1 step can be used for pre-positioning the position of the kth chip module, the kth-1 step can also be used for providing structural support for the kth chip module, so that the reliability of the chip packaging structure is improved, and the nth layer of heat dissipation part can be used for timely dissipating heat of the nth chip module, so that the heat dissipation effect of the chip packaging structure is improved; the kth chip module is electrically connected with the kth-1 chip module, the kth-1 chip module provides structural support for the kth chip module, the opposite areas of the first chip module and the second chip module are fixedly connected, and the first chip module provides structural support for the second chip module, so that the chip packaging structure is good in reliability. In conclusion, the chip packaging structure has good reliability and heat dissipation effect.

In one embodiment, the chip package structure further includes: the first edge welding pad to the N-1 edge welding pad, and any k-1 edge welding pad is positioned on the bottom surface of the k-1 step; a k-1 welding piece is arranged on one side surface of the kth chip module, which faces to the bottom surface of the k-1 step; the kth-1 welding piece is positioned on the kth-1 edge welding pad and is connected with the kth-1 edge welding pad, and the kth-1 edge welding pad is favorable for firmly connecting the kth chip module with the kth-1 layer heat dissipation part, so that the reliability of the chip packaging structure can be improved.

In one embodiment, the (k-1) th edge bonding pad is in a ring structure surrounding the accommodating cavity, and the (k-1) th welding piece is in a ring structure corresponding to the (k-1) th edge bonding pad. The k-1 edge welding pad and the k-1 welding piece can realize a heat conduction function, so that the heat of the k chip module can be timely transmitted to the k-1 heat dissipation part, and the heat dissipation effect of the chip packaging structure is improved.

In one embodiment, the material of the heat dissipation structure includes: copper, aluminum or ceramic; in other embodiments, the material of the heat dissipation structure may further include other materials with good heat dissipation capability and structural stability.

In this embodiment, with reference to fig. 1 and fig. 2 in combination, it is indicated that N is equal to five, the heat dissipation structure includes a first heat dissipation portion r1, a second heat dissipation portion r2, a third heat dissipation portion r3, a fourth heat dissipation portion r4, and a fifth heat dissipation portion r5, which are sequentially connected in a direction of a central axis running through the accommodating cavity, each of the first heat dissipation portion r1, the second heat dissipation portion r2, the third heat dissipation portion r3, the fourth heat dissipation portion r4, and the fifth heat dissipation portion r5 is in an annular structure, an opening of the accommodating cavity surrounded by the fifth heat dissipation portion r5 is larger than an opening of the accommodating cavity surrounded by the fourth heat dissipation portion r4, an opening of the accommodating cavity surrounded by the fourth heat dissipation portion r4 is larger than an opening of the accommodating cavity surrounded by the third heat dissipation portion r3, an opening of the accommodating cavity surrounded by the third heat dissipation portion r3 is larger than an opening of the accommodating cavity surrounded by the second heat dissipation portion r2, and an opening of the accommodating cavity surrounded by the second heat dissipation portion r2 is larger than an opening of the accommodating cavity surrounded by the first heat dissipation portion r 1; a fourth step j1 is formed between the fifth heat sink portion r5 and the fourth heat sink portion r4, a third step j3 is formed between the fourth heat sink portion r4 and the third heat sink portion r3, a second step j2 is formed between the third heat sink portion r3 and the second heat sink portion r2, and a first step j1 is formed between the second heat sink portion r2 and the first heat sink portion r 1.

Referring to fig. 3, taking N equal to five as an illustration, the chip package structure further includes: the first chip module m1 is positioned in an accommodating cavity surrounded by the first heat dissipation part r 1; the second chip module m2 is positioned in the accommodating cavity surrounded by the second heat dissipation part r2, the third chip module m3 is positioned in the accommodating cavity surrounded by the third heat dissipation part r3, the fourth chip module m4 is positioned in the accommodating cavity surrounded by the fourth heat dissipation part r4, and the fifth chip module m5 is positioned in the accommodating cavity surrounded by the fifth heat dissipation part r 5; the second chip module m2 is positioned in the accommodating cavity surrounded by the second heat dissipation part r2 and is arranged opposite to the first step j1, the third chip module m3 is positioned in the accommodating cavity surrounded by the third heat dissipation part r3 and is arranged opposite to the second step j2, the fourth chip module m4 is positioned in the accommodating cavity surrounded by the fourth heat dissipation part r4 and is arranged opposite to the third step j3, and the fifth chip module m5 is positioned in the accommodating cavity surrounded by the fifth heat dissipation part r5 and is arranged opposite to the fourth step j 4; the second chip module m2 is electrically connected with the first chip module m1, the region where the first chip module m1 and the second chip module m2 are opposite is fixedly connected, the third chip module m3 is electrically connected with the second chip module m2, the region where the second chip module m2 and the third chip module m3 are opposite is fixedly connected, the fourth chip module m4 is electrically connected with the third chip module m3, the region where the third chip module m3 and the fourth chip module m4 are opposite is fixedly connected, the fifth chip module m5 is electrically connected with the fourth chip module m4, and the region where the fourth chip module m4 and the fifth chip module m5 are opposite is fixedly connected.

Referring to fig. 1, taking N equal to five as an illustration, the chip package structure further includes: the first edge bonding pad h1, the second edge bonding pad h2, the third edge bonding pad h3 and the fourth edge bonding pad h4 are arranged on the bottom surface of the first step j1, the second edge bonding pad h2 is arranged on the bottom surface of the second step j2, the third edge bonding pad h3 is arranged on the bottom surface of the third step j3, and the fourth edge bonding pad h4 is arranged on the bottom surface of the fourth step j 4.

In one embodiment, any jth chip module includes: a jth carrier plate; the jth chip is positioned on the upper surface of the jth carrier plate; the jth conductive connecting piece is positioned on the upper surface of the jth carrier plate and positioned on the side part of the jth chip; the jth solder ball is positioned on the surface of one side, away from the jth chip, of the jth carrier plate; the jth plastic packaging layer covers the jth chip and the side wall of the jth conductive connecting piece; the jth top layer bonding pad is positioned on the surface of one side, away from the jth carrier plate, of the jth plastic packaging layer; part of the jth top layer bonding pad is connected with the jth conductive connecting piece; j is an integer greater than or equal to 1 and less than or equal to N-1.

In one embodiment, in any jth chip module, the number of jth chips located on the upper surface of the jth carrier is several, and the several jth chips are arranged at intervals in the horizontal direction, so that the improvement of the function of the chip packaging structure is facilitated.

Referring to fig. 4, with j equal to two as an illustration, the second chip module includes: a second carrier plate 21; a second chip 22 located on the upper surface of the second carrier 21; a second conductive connecting part 23 located on the upper surface of the second carrier 21, wherein the second conductive connecting part 23 is located at the side of the second chip 22; the second solder balls 24 are positioned on the surface of one side of the second carrier 21, which faces away from the second chip 22; a second molding layer 25 covering sidewalls of the second chip 22 and the second conductive connection member 23; a second top pad 26 on a side surface of the second molding compound layer 25 away from the second carrier 21, and a side surface of the second chip module facing the bottom surface of the first step are provided with first solder members 27.

In one embodiment, any jth chip module further includes: and the capacitors or the resistors are arranged on the upper surface of the jth carrier plate at intervals.

In one embodiment, the nth chip module includes: an Nth carrier plate; the Nth chip is positioned on the upper surface of the Nth carrier plate; the Nth conductive connecting piece is positioned on the upper surface of the Nth carrier plate and positioned on the side part of the Nth chip; an Nth solder ball positioned on the surface of one side of the Nth carrier plate, which is far away from the Nth chip; the Nth plastic packaging layer covers the side walls of the Nth chip and the Nth conductive connecting piece; the antenna unit is positioned on the surface of one side, away from the Nth carrier plate, of the Nth plastic packaging layer; the antenna unit is connected with the Nth conductive connecting piece.

In one embodiment, in the nth chip module, the number of the nth chips located on the upper surface of the nth carrier is several, and the several nth chips are arranged at intervals in the horizontal direction, which is favorable for improving the function of the chip packaging structure.

Referring to fig. 5, with N equal to five as an illustration, the fifth chip module includes: a fifth carrier plate 51; a fifth chip 52 located on the upper surface of the fifth carrier 51; a fifth conductive connecting part 53 located on the upper surface of the fifth carrier 51, wherein the fifth conductive connecting part 53 is located at the side of the fifth chip 52; a fifth solder ball 54 located on a surface of the fifth carrier 51 facing away from the fifth chip 52; a fifth molding layer 55 covering sidewalls of the fifth chip 52 and the fifth conductive connecting member 53; the antenna unit 56 is located on the surface of the fifth plastic package layer 55 on the side away from the fifth carrier plate 51; the antenna element 56 is connected to the fifth conductive connection 53.

In one embodiment, any nth chip module further includes: and the capacitors or the resistors are arranged on the upper surface of the Nth carrier plate at intervals.

In one embodiment, the jth top level pad is connected to the j +1 th solder ball. The jth top layer bonding pad can be used for electrically connecting the jth chip module with the (j + 1) th chip module, so that the connection reliability of the jth chip module and the (j + 1) th chip module is improved, and the heat of the jth chip module and the (j + 1) th chip module can be dissipated in time.

Referring to fig. 3, with N equal to five as an illustration, the first top-level pad is connected to the second solder ball, the second top-level pad is connected to the third solder ball, the third top-level pad is connected to the fourth solder ball, and the fourth top-level pad is connected to the fifth solder ball.

In one embodiment, the chip package structure further includes: and the nth layer of heat-conducting glue is positioned between the side wall of any nth chip module and the inner side wall of the nth heat radiating part. On one hand, the nth layer of heat-conducting glue is used for connecting the nth chip module with the nth layer of heat dissipation part, so that the connection reliability of the nth chip module and the heat dissipation structure is improved; on the other hand, the heat of the nth chip module can be timely transferred to the nth heat dissipation part by the nth layer of heat-conducting glue, and the heat is timely dissipated by the nth heat dissipation part, so that the reliability and the heat dissipation effect of the chip packaging structure are good.

In one embodiment, the material of the nth layer of heat-conducting glue has good heat-conducting effect and good bonding effect.

In an embodiment, the thickness of the nth layer of thermal conductive adhesive is 50um to 100um, for example 55um, if the thickness of the nth layer of thermal conductive adhesive is less than 50um, the conductive adhesive may not completely fill the gap between the nth chip module and the nth layer of heat dissipation portion, so that the heat dissipation effect of the chip packaging structure is not obvious, and if the thickness of the nth layer of thermal conductive adhesive is greater than 100um, the thermal resistance is increased, so that the heat dissipation effect of the chip packaging structure is not obvious.

The thickness of the nth layer of heat-conducting glue is limited by the precision of a machining instrument and micro-assembly, and the nth layer of heat-conducting glue is completely filled in a gap between the side wall of the nth chip module and the inner side wall of the nth layer of heat dissipation part and is required to be as small as possible. In this embodiment, with reference to fig. 3, taking N equal to five as an illustration, the chip package structure further includes: the first layer of heat-conducting glue l1 is positioned between the side wall of the first chip module m1 and the inner side wall of the first heat dissipation part r 1; the second layer of heat-conducting glue l2 is positioned between the side wall of the second chip module m2 and the inner side wall of the second layer of heat dissipation part r 2; a third layer of heat-conducting glue l3 positioned between the side wall of the third chip module m3 and the inner side wall of the third layer of heat-radiating part r 3; a fourth layer of heat-conducting glue l4 positioned between the side wall of the fourth chip module m4 and the inner side wall of the fourth layer of heat dissipation part r 4; and the fifth layer heat-conducting glue l5 is positioned between the side wall of the fifth chip module m5 and the inner side wall of the fifth layer heat-radiating part r 5.

Example 2

The embodiment provides a method for manufacturing a chip package structure, and referring to fig. 6, the method includes the following steps:

step S1: providing a heat dissipation structure, wherein the heat dissipation structure is provided with a through accommodating cavity, the heat dissipation structure comprises a first layer of heat dissipation part to an Nth layer of heat dissipation part which are sequentially connected along the direction of a central shaft of the through accommodating cavity, N is an integer greater than or equal to 2, any Nth layer of heat dissipation part is in an annular structure, and N is an integer greater than or equal to 1 and less than or equal to N; the opening of the accommodating cavity surrounded by the k-1 heat dissipation part is larger than the opening of the accommodating cavity surrounded by the k-1 heat dissipation part; a k-1 step is formed between the k-1 heat dissipation part and the k-1 heat dissipation part; k is an integer greater than or equal to 2 and less than or equal to N;

step S2: providing a first chip module to an Nth chip module;

and step S3: placing the first chip module in an accommodating cavity surrounded by the first heat dissipation part; placing any kth chip module in an accommodating cavity surrounded by the kth heat dissipation part and opposite to the kth-1 step; the kth chip module is electrically connected with the kth-1 chip module, and the opposite areas of the first chip module and the second chip module are fixedly connected.

According to the preparation method of the chip packaging structure provided by the embodiment, in the preparation process of the chip packaging structure, the k-1 th step can be used for prepositioning the position of the k chip module, and the first chip module to the Nth chip module can be sequentially placed in the accommodating cavities surrounded by the first heat dissipation part to the Nth heat dissipation part for primary packaging without multiple packaging, so that the reliability of the chip packaging structure can be improved by the preparation method of the chip packaging structure; the nth layer of heat dissipation part can dissipate the heat of the nth chip module in time, so that the heat dissipation effect of the chip packaging structure is improved; the kth chip module is electrically connected with the kth-1 chip module, the kth-1 chip module provides structural support for the kth chip module, the opposite areas of the first chip module and the second chip module are fixedly connected, and the first chip module provides structural support for the second chip module, so that the chip packaging structure is good in reliability. In conclusion, the preparation method of the chip packaging structure can improve the reliability and the heat dissipation effect of the chip packaging structure.

The heat dissipation structure is provided with a through accommodating cavity, the heat dissipation structure comprises a first layer of heat dissipation part to an Nth layer of heat dissipation part which are sequentially connected along the direction of a central shaft of the through accommodating cavity, N is an integer larger than or equal to 2, any Nth layer of heat dissipation part is of an annular structure, and N is an integer larger than or equal to 1 and smaller than or equal to N; the opening of the accommodating cavity surrounded by the k-1 heat dissipation part is larger than the opening of the accommodating cavity surrounded by the k-1 heat dissipation part; a k-1 step is formed between the kth layer of heat dissipation part and the k-1 layer of heat dissipation part; k is an integer greater than or equal to 2 and less than or equal to N. The heat dissipation structure further includes: first to N-1 edge pads; an arbitrary (k-1) th edge pad is located at the bottom of the (k-1) th step.

In one embodiment, the method for manufacturing a chip package structure further includes: and providing a carrier plate, wherein a carrier plate hole is formed in the middle area of the carrier plate, and an opening of the carrier plate hole is smaller than an opening of the accommodating cavity surrounded by the first heat dissipation part.

In one embodiment, the method for manufacturing a chip package structure further includes: placing a heat dissipation structure on the carrier plate, wherein a first layer of heat dissipation part to an Nth layer of heat dissipation part are arranged on the carrier plate from bottom to top; the carrier plate hole is positioned at the bottom of the accommodating cavity surrounded by the first heat dissipation part and is communicated with the accommodating cavity; a bottom step is formed between the carrier plate and the first layer of heat dissipation part.

In step S2, specifically, the step of forming the jth chip module includes: providing a jth carrier plate; forming a jth chip on the upper surface of the jth carrier; forming a jth conductive connecting piece on the upper surface of the jth carrier, wherein the jth conductive connecting piece is positioned on the side part of the jth chip; forming a jth solder ball on the surface of one side, away from the jth chip, of the jth carrier plate; forming a jth plastic packaging layer covering the jth chip and the side wall of the jth conductive connecting piece; forming a jth top layer bonding pad on the surface of one side, away from the jth carrier plate, of the jth plastic packaging layer; the jth top layer bonding pad is connected with the jth conductive connecting piece; and forming a (k-1) th edge welding piece in the edge area of the surface of the jth carrier plate, which is far away from the jth chip, wherein j is an integer which is greater than or equal to 1 and less than or equal to N-1. In one embodiment, the step of forming the nth layer chip module includes: providing an Nth carrier plate; forming an Nth chip on the upper surface of the Nth carrier plate; forming an Nth conductive connecting piece on the upper surface of the Nth carrier plate, wherein the Nth conductive connecting piece is positioned on the side part of the Nth chip; forming an Nth solder ball on the surface of one side, away from the Nth chip, of the Nth carrier plate; forming an Nth plastic package layer covering the side walls of the Nth chip and the Nth conductive connecting piece; forming an N-1 edge welding piece in the edge area of the surface of one side, away from the Nth chip, of the Nth carrier plate, and forming an antenna unit on the surface of one side, away from the Nth carrier plate, of the Nth plastic packaging layer; the antenna unit is connected with the Nth conductive connecting piece.

In step S3, specifically, the first chip module is placed in the accommodating cavity surrounded by the first heat dissipation portion; and in the step of placing the first chip module in the accommodating cavity surrounded by the first heat dissipation part, the first chip module is arranged opposite to the bottom step.

After the first chip module is placed in the accommodating cavity surrounded by the first heat dissipation part, any k chip module is placed in the accommodating cavity surrounded by the k heat dissipation part; a k-1 edge weldment is arranged on one side surface of any k chip module, which faces to the bottom surface of the k-1 step; and in the step of placing any kth chip module in the accommodating cavity surrounded by the kth heat dissipation part, arranging the kth-1 edge welding piece on the kth-1 edge welding pad and connecting the kth-1 edge welding pad with the kth edge welding pad.

In one embodiment, the step of disposing the (k-1) th edge bonding element on the (k-1) th edge bonding pad and connecting with the (k-1) th edge bonding pad further comprises: and connecting the jth top layer bonding pad with the jth +1 welding ball, so that the packaging times of the chip packaging structure are reduced, and the reliability of the chip packaging structure is improved.

In one embodiment, the step of connecting the k-1 edge solder member to the k-1 edge solder pad includes: and coating a welding layer on the surface of the k-1 edge welding pad, coating a welding layer on the surface of the k-1 edge welding piece, and connecting the k-1 edge welding piece with the k-1 edge welding pad, wherein the welding layer on the surface of the k-1 edge welding pad is connected with the welding layer on the surface of the k-1 edge welding piece.

The material of the solder layer comprises solder paste.

The in-process of placing arbitrary nth chip module in the holding chamber that nth layer heat dissipation portion encircles still includes: and an nth layer of heat-conducting glue is formed between the side wall of any nth chip module and the inner side wall of the nth heat radiating part.

And after the Nth chip module is placed in the accommodating cavity surrounded by the Nth heat dissipation part, the carrier plate is removed.

In this embodiment, a method for manufacturing the chip package structure is described in detail with reference to fig. 7 to 9, which are schematic views of N being equal to five.

In this embodiment, referring to fig. 7, the heat dissipation structure includes a first heat dissipation portion r1, a second heat dissipation portion r2, a third heat dissipation portion r3, a fourth heat dissipation portion r4 and a fifth heat dissipation portion r5 sequentially connected in a central axis direction passing through the accommodating cavity, the first heat dissipation portion r1, the second heat dissipation portion r2, the third heat dissipation portion r3, the fourth heat dissipation portion r4 and the fifth heat dissipation portion r5 are all in an annular structure, an opening of the accommodating cavity surrounded by the fifth heat dissipation portion r5 is larger than an opening of the accommodating cavity surrounded by the fourth heat dissipation portion r4, an opening of the accommodating cavity surrounded by the fourth heat dissipation portion r4 is larger than an opening of the accommodating cavity surrounded by the third heat dissipation portion r3, an opening of the accommodating cavity surrounded by the third heat dissipation portion r3 is larger than an opening of the accommodating cavity surrounded by the second heat dissipation portion r2, and an opening of the accommodating cavity surrounded by the second heat dissipation portion r2 is larger than an opening of the accommodating cavity surrounded by the first heat dissipation portion r 1; a fourth step j1 is formed between the fifth heat dissipation portion r5 and the fourth heat dissipation portion r4, a third step j3 is formed between the fourth heat dissipation portion r4 and the third heat dissipation portion r3, a second step j2 is formed between the third heat dissipation portion r3 and the second heat dissipation portion r2, and a first step j1 is formed between the second heat dissipation portion r2 and the first heat dissipation portion r 1. The chip packaging structure further comprises: the first edge bonding pad h1, the second edge bonding pad h2, the third edge bonding pad h3 and the fourth edge bonding pad h4 are arranged on the bottom surface of the first step j1, the second edge bonding pad h2 is arranged on the bottom surface of the second step j2, the third edge bonding pad h3 is arranged on the bottom surface of the third step j3, and the fourth edge bonding pad h4 is arranged on the bottom surface of the fourth step j 4.

In this embodiment, referring to fig. 8, the method for manufacturing the chip package structure further includes: a carrier plate 100 is provided, and a middle area of the carrier plate 100 has a carrier plate hole, and an opening of the carrier plate hole is smaller than an opening of the accommodating cavity surrounded by the first heat dissipation portion r 1.

With N equal to five as an illustration, with continued reference to fig. 8, the method for manufacturing a chip package structure further includes: placing a heat dissipation structure on the carrier plate 100, wherein a first heat dissipation part r1, a second heat dissipation part r2, a third heat dissipation part r3, a fourth heat dissipation part r4 and a fifth heat dissipation part r5 are arranged on the carrier plate 100 from bottom to top; the carrier plate hole is positioned at the bottom of the accommodating cavity surrounded by the first heat dissipation part r1 and is communicated with the accommodating cavity; a bottom step is formed between the carrier 100 and the first layer of heat dissipation part r 1.

With N equal to five as an illustration, with continued reference to fig. 8, in the process of disposing the first edge bonding part on the first edge bonding pad and connecting with the first edge bonding pad, the method further includes: connecting the first top layer bonding pad with the second solder ball, and arranging the second edge welding piece on the second edge bonding pad and in the process of connecting the second edge bonding pad with the second edge bonding pad, the method further comprises the following steps: connect second top layer pad and third solder ball, set up third edge soldering part on third edge pad and with the in-process that third edge pad is connected, still include: connect third top layer pad and fourth solder ball, set up fourth edge soldering part on fourth edge pad and with the in-process that fourth edge pad is connected, still include: and connecting the fourth top-layer bonding pad and the fifth welding ball.

With N equal to five as an illustration, with continued reference to fig. 8, in the process of placing the first chip module m1 in the accommodating cavity surrounded by the first layer of heat dissipation portion r1, the method further includes: forming a first layer of heat-conducting glue l1 between the side wall of the first chip module m1 and the inner side wall of the first heat dissipation part r 1; place second chip module m2 in-process in the holding chamber that second layer heat dissipation portion r2 encircles, still include: a second layer of heat-conducting glue l2 is formed between the side wall of the second chip module m2 and the inner side wall of the second layer of heat dissipation part r 2; in the process of placing the third chip module m3 in the accommodating cavity surrounded by the third heat sink r3, the method further comprises: form third layer heat-conducting glue l3 between the lateral wall of third chip module m3 and the inside wall of third layer heat dissipation portion r3, place fourth chip module m4 in the in-process in the holding chamber that fourth layer heat dissipation portion r4 encircles, still include: form fourth layer heat-conducting glue l4 between the lateral wall of fourth chip module m4 and the inside wall of fourth layer heat dissipation portion r4, place fifth chip module m5 at the in-process in the holding chamber that fifth layer heat dissipation portion r5 encircles, still include: a fifth layer heat-conducting glue l5 is formed between the side wall of the fifth chip module m5 and the inner side wall of the fifth layer heat sink portion r 5.

With reference to fig. 9, after a fifth chip module m5 is placed in the accommodating cavity surrounded by the fifth heat dissipation portion r5, the carrier 100 is removed.

The same parts of this embodiment as those of the previous embodiment will not be described in detail.

It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications derived therefrom are intended to be within the scope of the invention.

Claims (8)

1. A chip package structure, comprising:

the heat dissipation structure is provided with a through accommodating cavity and comprises a first layer of heat dissipation part to an Nth layer of heat dissipation part which are sequentially connected along the direction of a central shaft of the through accommodating cavity, N is an integer larger than or equal to 2, any nth layer of heat dissipation part is of an annular structure, and N is an integer larger than or equal to 1 and smaller than or equal to N; the opening of the accommodating cavity surrounded by the kth layer of heat dissipation part is larger than the opening of the accommodating cavity surrounded by the kth-1 layer of heat dissipation part; a k-1 step is formed between the k-1 heat dissipation part and the k-1 heat dissipation part; k is an integer greater than or equal to 2 and less than or equal to N;

the first chip module is positioned in the accommodating cavity surrounded by the first heat dissipation part; any kth chip module is positioned in the accommodating cavity surrounded by the kth heat radiating part and is arranged opposite to the kth-1 step; the kth chip module is electrically connected with the kth-1 chip module, and the opposite areas of the first chip module and the second chip module are fixedly connected.

2. The chip package structure according to claim 1, further comprising: the first edge welding pad to the N-1 edge welding pad, and any k-1 edge welding pad is positioned on the bottom surface of the k-1 step; a k-1 welding piece is arranged on the surface of one side, facing the bottom surface of the k-1 step, of the kth chip module; the kth-1 welding piece is positioned on the kth-1 edge welding pad and is connected with the kth-1 edge welding pad;

preferably, the (k-1) th edge welding pad is in an annular structure surrounding the accommodating cavity, and the (k-1) th welding piece is in an annular structure corresponding to the (k-1) th edge welding pad.

3. The chip package structure according to claim 1, wherein any jth chip module comprises: a jth carrier plate; the jth chip is positioned on the upper surface of the jth carrier plate; the jth conductive connecting piece is positioned on the upper surface of the jth carrier plate and positioned on the side part of the jth chip; a jth solder ball positioned on the surface of one side, away from the jth chip, of the jth carrier plate; the jth plastic packaging layer covers the jth chip and the side wall of the jth conductive connecting piece; the jth top layer bonding pad is positioned on the surface of one side, away from the jth carrier plate, of the jth plastic packaging layer; part of the jth top layer bonding pad is connected with the jth conductive connecting piece; j is an integer greater than or equal to 1 and less than or equal to N-1;

the Nth chip module includes: an Nth carrier plate; the Nth chip is positioned on the upper surface of the Nth carrier plate; the Nth conductive connecting piece is positioned on the upper surface of the Nth carrier plate and positioned on the side part of the Nth chip; the Nth solder ball is positioned on the surface of one side, departing from the Nth chip, of the Nth carrier plate; the Nth plastic packaging layer covers the side walls of the Nth chip and the Nth conductive connecting piece; the antenna unit is positioned on the surface of one side, away from the Nth carrier plate, of the Nth plastic packaging layer; the antenna unit is connected with the Nth conductive connecting piece;

and the jth top layer bonding pad is connected with the jth +1 th welding ball.

4. The chip package structure according to claim 1, further comprising: the nth layer of heat-conducting glue is positioned between the side wall of any nth chip module and the inner side wall of the nth heat radiating part;

preferably, the thickness of the nth layer of heat-conducting glue is 50um-100um.

5. The chip package structure according to claim 1, wherein the material of the heat dissipation structure comprises: copper, aluminum or ceramic.

6. A method for preparing a chip packaging structure is characterized by comprising the following steps:

providing a heat dissipation structure, wherein the heat dissipation structure is provided with a through accommodating cavity, the heat dissipation structure comprises a first layer of heat dissipation part to an Nth layer of heat dissipation part which are sequentially connected along the direction of a central shaft of the through accommodating cavity, N is an integer greater than or equal to 2, any Nth layer of heat dissipation part is in an annular structure, and N is an integer greater than or equal to 1 and less than or equal to N; the opening of the accommodating cavity surrounded by the k-1 heat dissipation part is larger than the opening of the accommodating cavity surrounded by the k-1 heat dissipation part; a k-1 step is formed between the k-1 heat dissipation part and the k-1 heat dissipation part; k is an integer greater than or equal to 2 and less than or equal to N;

providing a first chip module to an Nth chip module;

placing the first chip module in an accommodating cavity surrounded by the first heat dissipation part; placing any kth chip module in an accommodating cavity surrounded by the kth heat dissipation part and opposite to the kth-1 step; the kth chip module is electrically connected with the kth-1 chip module, and the opposite areas of the first chip module and the second chip module are fixedly connected.

7. The method of manufacturing a chip package structure according to claim 6,

providing a carrier plate, wherein a carrier plate hole is formed in the middle area of the carrier plate, and an opening of the carrier plate hole is smaller than an opening of an accommodating cavity surrounded by a first heat dissipation part;

placing a heat dissipation structure on the carrier plate, wherein a first layer of heat dissipation part to an Nth layer of heat dissipation part are arranged on the carrier plate from bottom to top; the carrier plate hole is positioned at the bottom of the accommodating cavity surrounded by the first heat dissipation part and is communicated with the accommodating cavity; a bottom step is formed between the carrier plate and the first layer of heat dissipation part;

in the step of placing the first chip module in the accommodating cavity surrounded by the first heat dissipation part, the first chip module is arranged opposite to the bottom step;

after the first chip module is placed in the accommodating cavity surrounded by the first heat dissipation part, any k chip module is placed in the accommodating cavity surrounded by the k heat dissipation part;

placing the Nth chip module in an accommodating cavity surrounded by the Nth layer of heat dissipation part, and removing the carrier plate;

preferably, the heat dissipation structure further includes: first to N-1 edge pads; any (k-1) th edge welding pad is positioned on the bottom surface of the (k-1) th step; a k-1 edge weldment is arranged on one side surface of any k chip module, which faces to the bottom surface of the k-1 step; and in the step of placing any kth chip module in the accommodating cavity surrounded by the kth heat dissipation part, arranging the kth-1 edge welding piece on the kth-1 edge welding pad and connecting the kth-1 edge welding pad with the kth edge welding pad.

8. The method for manufacturing a chip package structure according to claim 6, wherein in the process of placing any nth chip module in the accommodating cavity surrounded by the nth heat sink portion, the method further comprises: and an nth layer of heat-conducting glue is formed between the side wall of any nth chip module and the inner side wall of the nth layer of heat sink part.

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