CN115730560A - Method and device for generating verilog code based on SOC chip signal - Google Patents
Method and device for generating verilog code based on SOC chip signal Download PDFInfo
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Abstract
The invention discloses a method and a device for generating verilog codes based on SOC chip signals, which comprises the following steps: selecting a plurality of functional modules according to a clock tree and a reset tree of the SOC chip, and creating corresponding functional modules, at least one input interface and at least one output interface on a graphical interactive interface; acquiring an incidence relation between a clock tree and a reset tree, and establishing a connection relation among signal ends, input interfaces and output interfaces of each functional module according to the incidence relation to obtain a signal structure chart; and analyzing the signal structure diagram to obtain configuration information corresponding to the functional module, the connection relation, the input interface and the output interface, and filling the configuration information to a corresponding position of the verilog template to generate a verilog code. The connection relation of the clock tree and the reset tree signals is visually displayed through an interactive interface, the clock tree and the reset tree are ensured to accord with the design intention, and the error rate of codes is effectively reduced.
Description
Technical Field
The invention belongs to the field of chip design, and particularly relates to a method and a device for generating verilog codes based on SOC chip signals.
Background
Clock and reset logic is a key to SOC (System on Chip) Chip design, and the clock and reset signals inside large SOC chips are hundreds. However, verilog code for the clock and reset logic is currently available primarily through manual editing. The verilog codes of the clock and the reset signal are manually edited, so that the time consumption is long, and the error rate is high; and the obtained verilog code is inconsistent with the real design intention, and the problems are often large in influence and difficult to locate.
Disclosure of Invention
Aiming at the defects or improvement requirements of the prior art, the invention provides a method and a device for generating verilog codes based on SOC chip signals, aiming at visually displaying the connection relation of clock trees and reset tree signals through an interactive interface, reducing the error probability, easily checking even if errors occur, ensuring that the designed clock trees and reset trees conform to the design intention, automatically generating corresponding verilog codes based on the graphical clock trees and reset trees, effectively reducing the error rate of the clock trees and reset tree signals, and solving the problems of long time consumption and high error rate of manually editing the verilog codes of the clocks and the reset signals; moreover, the obtained verilog code is inconsistent with the real design intention, and the problems usually affect the technical problems of large influence and difficult positioning.
To solve the foregoing problem, a first aspect provides a method for generating verilog code based on SOC chip signals, including:
selecting a plurality of functional modules according to a clock tree and a reset tree of the SOC chip, and creating corresponding functional modules, at least one input interface and at least one output interface on a graphical interactive interface;
acquiring the incidence relation between the clock tree and the reset tree, and establishing the connection relation among the signal end of each functional module, the input interface and the output interface according to the incidence relation to obtain a signal structure chart;
and analyzing the signal structure chart to obtain configuration information corresponding to the functional module, the connection relation, the input interface and the output interface, and filling the configuration information to a corresponding position of a verilog template to generate a verilog code.
Further, the obtaining an association relationship between the clock tree and the reset tree, and establishing a connection relationship among the signal end of each functional module, the input interface, and the output interface according to the association relationship to obtain a signal structure diagram includes:
connecting the signal ends of the corresponding functional modules together according to the incidence relation to form a connecting line;
connecting the signal end of the corresponding functional module with the input interface;
and connecting the signal end and the output interface of the corresponding functional module together.
Further, after the connection relationship is established, the method further includes:
configuring instantiation names of the function modules, connection names of connecting lines between the two function modules, first signal names of the input interfaces and second signal names of the output interfaces to obtain a signal structure diagram.
Further, the configuring an instantiation name of each functional module, a connection name of a connection line between two functional modules, a first signal name of each input interface, and a second signal name of each output interface to obtain a signal structure diagram includes:
detecting the types of the functional modules according to the flow direction of the signals, and dividing the functional modules of the same type into a group;
aiming at each group of functional modules, configuring instantiation names for each functional module according to the sequence of the position numbers from small to large;
and acquiring a first instantiation name and a second instantiation name of the two connected functional modules, and generating a connection name of the corresponding connection line according to the first instantiation name and the second instantiation name.
Further, the analyzing the signal structure diagram to obtain configuration information corresponding to the functional module, the connection relationship, the input interface, and the output interface, and filling the configuration information to a corresponding position of a verilog template to generate a verilog code includes:
analyzing the signal structure chart to obtain the instantiation name, the connection name, the first signal name and the second signal name;
and filling the instantiation name, the connection name, the first signal name and the second signal name into corresponding positions of a verilog template to generate verilog codes.
Further, the populating the instantiation name, the connection name, the first signal name, and the second signal name to corresponding positions of a verilog template to generate verilog code further comprises:
instantiating an input port and an output port of each functional module according to the signal structure diagram;
when the input port of the function module is connected with the input interface, the instantiation value of the input port of the function module is a first signal name;
when the input port of the functional module is connected with the output ports of other functional modules, the instantiation value of the input port of the functional module is a connection name;
when the output port of the function module is connected with the output interface, the instantiation value of the output port of the function module is a second signal name;
when the output port of the functional module is connected with the input ports of other functional modules, the instantiation value of the output port of the functional module is a connection name;
and filling the instantiation values of the input port and the output port in corresponding positions of the verilog template.
Furthermore, the functional modules comprise a clock selection module, a clock gating module, a clock buffer module, a clock frequency division module, an asynchronous reset synchronous release module or a constant output module.
Further, when the functional module is a clock frequency division module, the clock frequency division module comprises a frequency division coefficient; the method further comprises the following steps:
and acquiring a frequency division coefficient of the clock frequency division module, and filling the frequency division coefficient in a corresponding position of the verilog template.
Further, the method further comprises:
configuring module names for a signal structure diagram formed by a plurality of functional modules, at least one input interface and at least one output interface;
and filling the module name to the corresponding position of the verilog template.
In order to solve the foregoing problem, a second aspect provides an apparatus for generating verilog codes based on SOC chip signals, including at least one processor and a memory, where the at least one processor and the memory are connected through a data bus, and the memory stores instructions executable by the at least one processor, and the instructions are used to complete the method for generating verilog codes based on SOC chip signals according to the first aspect after being executed by the processor.
In general, compared with the prior art, the technical scheme conceived by the invention has the following beneficial effects: the embodiment of the invention provides a method for generating verilog codes based on SOC chip signals, which can intuitively display the connection relation of clock tree and reset tree signals through an interactive interface, reduce the error probability, easily troubleshoot errors, ensure that the designed clock tree and reset tree conform to the design intention, automatically generate corresponding verilog codes based on the graphical clock tree and reset tree, effectively reduce the error rate of the clock tree and reset tree signals and further shorten the design period of an SOC chip.
Drawings
Fig. 1 is a schematic flowchart of a method for generating verilog code based on SOC chip signals according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a signal structure diagram created based on a function module, an input interface and an output interface according to an embodiment of the present invention;
fig. 3 is a schematic diagram of another signal structure diagram created based on a function module, an input interface and an output interface according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an apparatus for generating verilog code based on SOC chip signals according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 1, the present embodiment provides a method for generating verilog code based on SOC chip signal, including:
step 101: and selecting a plurality of functional modules according to the clock tree and the reset tree of the SOC chip, and creating corresponding functional modules, at least one input interface and at least one output interface on the graphical interactive interface.
The clock signal is the reference for data transmission and is decisive for the function, performance and stability of the synchronous digital system. A clock signal is typically the signal that has the greatest fan-out throughout the chip, travels the longest distance, and runs at the highest speed. The clock signal must ensure that under worst case conditions, critical timing requirements can be met, otherwise any improper control of the clock signal may cause a violation, and the wrong data signal is stored in the register, resulting in a system function error.
The clock tree is a mesh structure built by a plurality of buffer units in a balanced mode, and has an active point, generally a clock input end, and then the clock tree is built by the buffer units of one level, and the specific number of levels depends on the setting and the used units.
The reset signal is of secondary importance within the digital circuit to the clock signal. For a chip, the main purpose of the reset is to bring the chip circuitry into a known, definite state. In general, each flip-flop in the chip should be resettable, and in some cases, when pipelined flip-flops are used in high speed applications, resets may be eliminated from some flip-flops in order to achieve higher performance designs.
Wherein the reset tree comprises at least one reset signal.
The functional modules comprise a clock selection module, a clock gating module, a clock buffer module, a clock frequency division module, an asynchronous reset synchronous release module or a constant output module.
The clock selection module is used for selecting a corresponding clock according to the clock; the clock gating module is used for configuring the size of an output clock according to a gating signal, and the clock buffer module is used for buffering an input clock signal; the asynchronous reset synchronous release module is used for synchronizing an asynchronous reset signal reset to a clk _ in clock domain; the constant output module is used for constant level. The explanation of each functional module is described in detail below.
Step 102: and acquiring the incidence relation between the clock tree and the reset tree, and establishing the connection relation among the signal end of each functional module, the input interface and the output interface according to the incidence relation to obtain a signal structure chart.
Specifically, signal ends of corresponding functional modules are connected together according to the association relationship to form a connecting line; connecting the signal end of the corresponding functional module with the input interface; and connecting the signal end and the output interface of the corresponding functional module together.
After the connection relationship is established, the instantiation name of each functional module, the connection name of a connection line between two functional modules, the first signal name of each input interface and the second signal name of each output interface are configured to obtain a signal structure diagram. Wherein the instantiation name, the connection name, the first signal name and the second signal name have uniqueness.
In a practical application scenario, instantiation names, connection names, first signal names and second signal names of the modules can be manually configured.
The manual configuration mode is troublesome, and particularly when the number of modules is large, corresponding names can be automatically generated in an actual application scene. In one preferred embodiment, the types of the functional modules are detected according to the flow direction of the signals, and the functional modules of the same type are divided into a group; aiming at each group of functional modules, configuring instantiation names for each functional module according to the sequence of the position numbers from small to large; and acquiring a first instantiation name and a second instantiation name of the two connected functional modules, and generating a connection name corresponding to the connection line according to the first instantiation name and the second instantiation name.
In another preferred embodiment, each additional function module can configure an instantiation name for the function module in a manner of increasing the position number; in a manner of increasing the number, each additional connection line can configure a connection name for the connection line.
Step 103: and analyzing the signal structure chart to obtain configuration information corresponding to the functional module, the connection relation, the input interface and the output interface, and filling the configuration information to a corresponding position of a verilog template to generate a verilog code.
Specifically, the signal structure diagram is analyzed to obtain the instantiation name, the connection name, the first signal name and the second signal name; and filling the instantiation name, the connection name, the first signal name and the second signal name into corresponding positions of a verilog template to generate verilog codes.
In verilog code, a port value of each functional module is instantiated according to the signal structure diagram, and the specific implementation mode is as follows: instantiating an input port and an output port of each functional module according to the signal structure diagram; when the input port of the function module is connected with the input interface, the instantiation value of the input port of the function module is a first signal name; when the input port of the functional module is connected with the output ports of other functional modules, the instantiation value of the input port of the functional module is a connection name; when the output port of the function module is connected with the output interface, the instantiation value of the output port of the function module is a second signal name; when the output port of the function module is connected with the input ports of other function modules, the instantiation value of the output port of the function module is the connection name; and filling the instantiation values of the input port and the output port in corresponding positions of the verilog template.
In an actual application scene, when the functional module is a clock frequency division module, the clock frequency division module comprises a frequency division coefficient; the method further comprises the following steps: and acquiring a frequency division coefficient of the clock frequency division module, and filling the frequency division coefficient in a corresponding position of the verilog template.
Further, the method further comprises: configuring module names for a signal structure diagram formed by a plurality of functional modules, at least one input interface and at least one output interface; and filling the module name to the corresponding position of the verilog template.
Referring to FIG. 2, CLK \/MUX is a clock selection module, CLK _ GATE is a clock gating module, CLK _ BUF is a clock buffering module, CLK _ DIV is a clock division module, RESET _ SYNC is an asynchronous RESET synchronous release module, and TIE0_ CELL and TIE1_ CELL are constant output modules. sel, clk1, clk2, clk3 and rst _ n are respectively first signal names corresponding to the input interfaces, and aclk _ gated and rst _ n _ sync are respectively second signal names corresponding to the output interfaces; sel, clk1, clk2 and clk3 are input signals from other modules, rst _ n _ sync and aclk _ gated are output signals, and the output signals are input to other modules.
The U0 to U7 are the position numbers of the corresponding functional modules, and clk1_ buf, pclk, sel0, clk3_ div4, aclk, and sel1 are the connection names of the connection lines connecting the two functional modules. rcm is the module name.
Wherein, verilog template is as follows:
module name (signal name of input interface, signal name of output interface);
the connection name of the wire connection line;
name of instantiation of CLK _ BUF function Module (b 1)
.clkin(),
.clkout()
)；
Name of CLK _ MUX function Module instantiation (
Clka (port instantiation value),
a clkb (port instantiation value),
clk _ sel (port instantiation value),
rst n (port instantiation value),
clk _ o (Port instantiation value)
)；
Name of CLK _ MUX function Module instantiation (
A clka (port instantiation value),
a clkb (port instantiation value),
clk _ sel (port instantiation value),
rst _ n (port instantiation value),
clk _ o (Port instantiation value)
)；
TIE0_ CELL function Module instantiation name (. Output (Port instantiation value)
)；
TIE1_ CELL function Module instantiation name (. Output (Port instantiation value)
)；
Name of CLK _ DIV function module instantiation (A)
Clk _ in (port instantiation value),
div _ set (port instantiation value),
rst n (port instantiation value),
.clk_out(clk13_div4)
)；
the CLK GATE function instantiates the name (. CLK in (port instantiation value),
clk en (port instantiation value),
clk _ out (Port instantiation value)
)；
The RESET _ SYNC function module instantiates a name (.clk _ in (port instantiation value),
reset (port instantiation value),
reset _ sync (port instantiation value)
)；
endmodule
In the verilog template, after a module name is filled in a module, a first signal name of an input interface and a second signal name of an output interface are filled in the module name, a template of a corresponding function module is selected according to the type of each function module, a function module instantiation name is filled in the position behind the corresponding function module, and an instantiation value of a port of each function module is filled in a corresponding position.
In this embodiment, instantiation names of the modules, signal names of the input interface and the output interface, and connection names are all configured manually. In order to improve efficiency, in this embodiment, the names may be automatically generated, that is, the corresponding names may be generated according to the uniqueness of the names.
In order to intuitively learn the function module corresponding to the connection name through the connection name, in this embodiment, the instantiation name and the connection name of the function module may be generated as follows: detecting the type of each functional module according to the flow direction of the signal, and dividing the functional modules of the same type into a group; aiming at each group of functional modules, configuring instantiation names for each functional module according to the sequence of the position numbers from small to large; a first instantiation name and a second instantiation name of two connected functional modules are obtained, and a connection name corresponding to the connection line is generated according to the first instantiation name and the second instantiation name, which is specifically shown in fig. 3. For convenience of understanding, for example, U10 and U11 are both position numbers corresponding to the clock selection modules, and the position numbers are used as instantiation names of each clock selection module. The connection name clk0_10 indicates that the functional module with the U0 location number and the functional module with the U10 location number are connected.
The embodiment of the invention provides a method for generating verilog codes based on SOC chip signals, which can visually display the connection relation of clock trees and reset tree signals through an interactive interface, reduce the error probability, easily check the errors, ensure that the designed clock trees and reset trees conform to the design intention, automatically generate corresponding verilog codes based on the graphical clock trees and reset trees, effectively reduce the error rate of the clock trees and reset tree signals and further shorten the design period of an SOC chip.
The embodiment of the invention comprises three parts: the device mainly comprises a basic component part, a clock selection module, a clock gating module, a clock buffer module, a clock frequency division module and an asynchronous reset synchronous release module; the clock tree and reset tree interactive interface part is used for visually displaying the connection relation of the clock tree and the reset tree signals; and the third part is a conversion part which can convert the imaged clock tree and the reset tree into verilog codes.
The implementation mode of the embodiment of the invention is as follows:
1. the common design method of the internal clock tree and the reset tree of the SOC chip is summarized to obtain 7 basic components. The clock select block, hereinafter denoted CLK MUX, has 4 input signals and 1 output signal, as shown in table 1 below:
table 1 attribute definition table of each interface of clock selection module
The clock gating block is denoted CLK _ GATE and has 2 input signals and 1 output signal as shown in table 2 below.
Table 2 attribute definition table of each interface of clock gating module
The clock buffer module is denoted CLK _ BUF and has 1 input signal and 1 output signal, as shown in table 3 below.
Table 3 attribute definition table of each interface of clock buffer module
The clock divider block is denoted CLK _ DIV and has 3 input signals and 1 output signal, as shown in table 4 below.
Table 4 attribute definition table of each interface of clock division module
The asynchronous RESET synchronous release module is denoted by RESET _ SYNC and has 2 input signals and 1 output signal, as shown in table 5 below. Where a signal is driven by a clock, the signal may belong to a signal within the clock domain.
Table 5 attribute definition table of each interface of asynchronous reset synchronous release module
The embodiment of the invention also comprises two constant output modules TIE0_ CELL and TIE1_ CELL, as shown in tables 6 and 7 below. Wherein, TIE0_ CELL and TIE1_ CELL are modules for constantly outputting 0 and 1; 1'b0 is a descriptive way, and represents < bit width > < system > < number >,1' b0 each numerical value or letter represents 1 bit width, 2 system, number 0 respectively; 1' b1 each numeric value or letter represents 1 bit wide, 2 system, number 1, respectively.
| TIE0_CELL | Properties | Description of the function |
| tie0 | output | Always output 1' b0 |
Table 6 attribute definition table for each interface of tie0_cell
| TIE1_CELL | Properties | Description of the function |
| tie1 | output | Always output 1' b1 |
Attribute definition table of interface of table 7TIE0_CELL
2. Establishing a graphical interactive interface, wherein the following 3 operations can be executed in the graphical interactive interface:
(1) Creating an input interface and an output interface, and specifying unique input signal names and output signal names;
(2) Creating a functional module which comprises 7 basic units such as CLK _ MUX, CLK _ GATE, CLK _ BUF, CLK _ DIV, RESET _ SYNC, TIE0_ CELL and TIE1_ CELL and can specify a unique instantiation name;
(3) Connecting the interface of each functional module with an input interface or an output interface, or connecting the interfaces of each basic unit with each other, wherein each connecting line can designate a unique signal name;
3. and automatically filling the signal name and the instantiation name into the corresponding position of the verilog template according to the connection relation in the interface, and automatically generating verilog codes.
In an actual application scenario, one of application modes of the method provided by the embodiment of the present invention is as follows: 1. determining a clock tree and reset tree scheme in the SOC according to the design specification; 2. according to the scheme of the clock tree and the reset tree, a functional module or an input/output interface is established in the interface; 3. connecting the interfaces of the functional modules with each other or connecting the interfaces of the functional modules with the input/output interfaces in the interface; 4. each functional module is assigned a unique instantiation name; 5. assigning a unique link name to each link; 6. and acquiring instantiation names of each functional module, connection names of each connection line, connection names of the input interfaces and signal names of the output interfaces, and filling the instantiation names, the connection names and the connection names in corresponding positions of the verilog template to generate verilog codes.
The embodiment of the invention provides a method for generating verilog codes based on SOC chip signals, which can intuitively display the connection relation of clock tree and reset tree signals through an interactive interface, reduce the error probability, easily troubleshoot errors, ensure that the designed clock tree and reset tree conform to the design intention, automatically generate corresponding verilog codes based on the graphical clock tree and reset tree, effectively reduce the error rate of the clock tree and reset tree signals and further shorten the design period of an SOC chip.
The embodiment also provides an example, and the example shows how to configure the clock tree and the reset tree through each functional module, the input interface and the output interface, so as to obtain the signal structure diagram, and how to generate the verilog code through the signal structure diagram.
As shown in FIG. 2, CLK _ MUX is a clock selection module, CLK _ GATE is a clock gating module, CLK _ BUF is a clock buffering module, CLK _ DIV is a clock division module, RESET _ SYNC is an asynchronous RESET synchronous release module, and TIE0_ CELL and TIE1_ CELL are constant output modules. sel, clk1, clk2, clk3 and rst _ n are respectively first signal names corresponding to the input interfaces, and aclk _ gated and rst _ n _ sync are respectively second signal names corresponding to the output interfaces; sel, clk1, clk2, clk3 are input signals from other modules, rst _ n _ sync and aclk _ gated are output signals, and the output signals are input to other modules.
The U0 to U7 are the position numbers of the corresponding functional modules, and clk1_ buf, pclk, sel0, clk3_ div4, aclk, and sel1 are the connection names of the connection lines connecting the two functional modules. rcm is the module name.
The verilog code is automatically generated according to the connection relationship shown in fig. 2 as follows:
module rcm(
input sel,
input clk1,
input clk2,
input clk3,
input rst_n,
output aclk_gated,
output rst_n_sync
)；
wire clk1_buf；
wire pclk；
wire aclk；
wire clk3_div4wire sel0；
wire sel1；
CLK_BUF U0(.clkin(clk1),
.clkout(clk1_buf))；
CLK_MUX U1(.clka(clk1_buf),.clkb(clk2),
.clk_sel(sel),
.rst_n(rst_n),
.clk_o(pclk)
)；
CLK_MUX U2(.clka(pclk),
.clkb(clk3_div4),.clk_sel(sel0),
.rst_n(rst_n),
.clk_o(aclk)
)；
TIE0_CELL U3(.output(sel0)
)；
TIE1_CELL U4(
.output(sel1)
)；
CLK_DIV U5(
.clk_in(clk3),
.div_set(2'd2),
.rst_n(rst_n),
.clk_out(clk13_div4)
)；
CLK_GATE U6(
.clk_in(aclk),
.clk_en(sel1),
.clk_out(aclk_gated)
)；
RESET_SYNC U7(
.clk_in(aclk),
.reset(rst_n),
.reset_sync(rst_n_sync)
)；
endmodule
on the basis of the method for generating verilog codes based on SOC chip signals provided in the foregoing embodiment, the present invention further provides a device for generating verilog codes based on SOC chip signals, which can be used to implement the method described above, as shown in fig. 4, it is a schematic diagram of a device architecture according to an embodiment of the present invention. The apparatus for generating verilog code based on SOC chip signal of the present embodiment includes one or more processors 21 and a memory 22. In fig. 4, one processor 21 is taken as an example.
The processor 21 and the memory 22 may be connected by a bus or other means, and fig. 4 illustrates the connection by a bus as an example.
The memory 22, which is a non-volatile computer-readable storage medium for a method of generating verilog code based on SOC chip signals, may be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the method of generating verilog code based on SOC chip signals in the above embodiments. The processor 21 executes various functional applications and data processing of the device by running the nonvolatile software program, instructions and modules stored in the memory 22, that is, implements the method for generating verilog codes based on SOC chip signals according to the above embodiments.
The memory 22 may include high speed random access memory and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, the memory 22 may optionally include memory located remotely from the processor 21, and these remote memories may be connected to the processor 21 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The program instructions/modules are stored in the memory 22 and, when executed by the one or more processors 21, perform the method for generating verilog code based on SOC chip signals in the above embodiments, for example, perform the steps illustrated in fig. 1 described above.
The method specifically comprises the following steps: selecting a plurality of functional modules according to a clock tree and a reset tree of the SOC chip, and creating corresponding functional modules, at least one input interface and at least one output interface on a graphical interactive interface; acquiring the incidence relation between the clock tree and the reset tree, and establishing the connection relation among the signal end of each functional module, the input interface and the output interface according to the incidence relation to obtain a signal structure chart; analyzing the signal structure diagram to obtain configuration information corresponding to the functional module, the connection relation, the input interface and the output interface, and filling the configuration information to a corresponding position of a verilog template to generate a verilog code.
Those of ordinary skill in the art will appreciate that all or part of the steps of the various methods of the embodiments may be implemented by associated hardware as instructed by a program, which may be stored on a computer-readable storage medium, which may include: a Read Only Memory (ROM), a Random Access Memory (RAM), a magnetic or optical disk, and the like.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A method for generating verilog code based on SOC chip signals is characterized by comprising the following steps:
selecting a plurality of functional modules according to a clock tree and a reset tree of the SOC chip, and creating corresponding functional modules, at least one input interface and at least one output interface on a graphical interactive interface;
acquiring the incidence relation between the clock tree and the reset tree, and establishing the connection relation among the signal end of each functional module, the input interface and the output interface according to the incidence relation to obtain a signal structure chart;
and analyzing the signal structure chart to obtain configuration information corresponding to the functional module, the connection relation, the input interface and the output interface, and filling the configuration information to a corresponding position of a verilog template to generate a verilog code.
2. The method for generating verilog code based on SOC chip signal according to claim 1, wherein the obtaining the association relationship between the clock tree and the reset tree, and establishing the connection relationship among the signal terminal of each functional module, the input interface and the output interface according to the association relationship to obtain the signal structure diagram includes:
connecting the signal ends of the corresponding functional modules together according to the association relationship to form a connecting line;
connecting the signal end of the corresponding functional module with the input interface;
and connecting the signal end and the output interface of the corresponding functional module together.
3. The method for generating verilog code based on SOC chip signals of claim 1, wherein after establishing a connection relationship, the method further comprises:
configuring an instantiation name of each functional module, a connection name of a connection line between two functional modules, a first signal name of each input interface and a second signal name of each output interface to obtain a signal structure diagram.
4. The method of generating verilog code based on SOC chip signal of claim 3, wherein the configuring instantiation name of each of the functional modules, connection name of a connection line between two functional modules, first signal name of each of the input interfaces and second signal name of each of the output interfaces to obtain a signal structure diagram comprises:
detecting the types of the functional modules according to the flow direction of the signals, and dividing the functional modules of the same type into a group;
aiming at each group of functional modules, configuring instantiation names for each functional module according to the sequence of the position numbers from small to large;
and acquiring a first instantiation name and a second instantiation name of the two connected functional modules, and generating a connection name of the corresponding connection line according to the first instantiation name and the second instantiation name.
5. The method for generating verilog code based on SOC chip signal of claim 3, wherein the analyzing the signal structure diagram to obtain the configuration information corresponding to the functional module, the connection relationship, the input interface and the output interface, and filling the configuration information to the corresponding position of verilog template to generate verilog code includes:
analyzing the signal structure diagram to obtain the instantiation name, the connection name, the first signal name and the second signal name;
and filling the instantiation name, the connection name, the first signal name and the second signal name into corresponding positions of a verilog template to generate verilog codes.
6. The method of generating verilog code based on SOC chip signal of claim 5, wherein the populating the instantiation name, the wire name, the first signal name and the second signal name to corresponding locations of verilog template to generate verilog code further comprises:
instantiating an input port and an output port of each functional module according to the signal structure diagram;
when the input port of the function module is connected with the input interface, the instantiation value of the input port of the function module is a first signal name;
when the input port of the function module is connected with the output ports of other function modules, the instantiation value of the input port of the function module is the connection name;
when the output port of the functional module is connected with the output interface, the instantiation value of the output port of the functional module is a second signal name;
when the output port of the functional module is connected with the input ports of other functional modules, the instantiation value of the output port of the functional module is a connection name;
and filling the instantiation values of the input port and the output port in corresponding positions of the verilog template.
7. The method for generating verilog code based on SOC chip signal of claim 1, wherein the functional module comprises a clock selection module, a clock gating module, a clock buffering module, a clock division module, an asynchronous reset synchronous release module or a constant output module.
8. The method of generating verilog code based on SOC chip signal of claim 7, wherein when the functional module is a clock division module, the clock division module includes a division coefficient; the method further comprises the following steps:
and acquiring a frequency division coefficient of the clock frequency division module, and filling the frequency division coefficient in a corresponding position of the verilog template.
9. The method for generating verilog code based on SOC chip signal of claim 1, wherein the method further comprises:
configuring module names for a signal structure diagram formed by a plurality of functional modules, at least one input interface and at least one output interface;
and filling the module name to the corresponding position of the verilog template.
10. An apparatus for generating verilog code based on SOC chip signals, comprising at least one processor and a memory, wherein the at least one processor and the memory are connected via a data bus, and the memory stores instructions executable by the at least one processor, and the instructions are used for completing the method of generating verilog code based on SOC chip signals according to any one of claims 1-9 after being executed by the processor.
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| CN116225404A (en) * | 2023-03-28 | 2023-06-06 | 深圳华芯盛软件科技有限公司 | Method for integrating chip codes |
| CN117272918A (en) * | 2023-11-21 | 2023-12-22 | 芯行纪科技有限公司 | Method for clock tree rule configuration in GUI interface and related equipment |
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| CN116225404A (en) * | 2023-03-28 | 2023-06-06 | 深圳华芯盛软件科技有限公司 | Method for integrating chip codes |
| CN117272918A (en) * | 2023-11-21 | 2023-12-22 | 芯行纪科技有限公司 | Method for clock tree rule configuration in GUI interface and related equipment |
| CN117272918B (en) * | 2023-11-21 | 2024-02-23 | 芯行纪科技有限公司 | Method for clock tree rule configuration in GUI interface and related equipment |
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