CN115729752A - Register checking method and device and storage medium - Google Patents
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Abstract
The embodiment of the application provides a register checking method and device and a storage medium, and the method comprises the following steps: reading a register address and register data in a target chip; sequentially searching an address node corresponding to the register address and at least one register segmentation sub-node corresponding to the address node from the multi-layer register index; analyzing at least one register segmentation sub-node to obtain at least one register segmentation information, and converting register data into at least one register value based on the at least one register segmentation information; respectively searching a value subnode corresponding to each register segmentation subnode from the multi-layer register index based on at least one register value to obtain at least one value subnode; and according to the at least one value sub-node, retrieving at least one register interpretation data segment from a register interpretation database corresponding to the multi-layer register index so as to realize register check based on the at least one register interpretation data segment.
Description
Technical Field
The present application relates to the field of registers, and in particular, to a register checking method and apparatus, and a storage medium.
Background
In the process of performing drive development or Chip Validation (CV) On a System On Chip (SOC) platform, if a problem occurs in the System, the System is validated by checking the value of the register and determining whether the actual configuration is matched.
At present, the check of the register can be realized by driving a CPU to send a register reading instruction to a system bus, and the SOC platform returns the required data, or by using a Trace32 (simulator) tool to send a register reading instruction through a Joint Test Action Group (JTAG) port, the SOC platform returns the required data; the hardware specification standard document is then consulted to locate the problem register.
However, the number of registers of an SOC platform is large, and a single problem may also relate to several or even more than ten registers, resulting in problems of low checking efficiency and long checking time.
Disclosure of Invention
The embodiment of the application provides a register checking method and device and a storage medium, which can improve checking efficiency and reduce time consumption.
The technical scheme of the application is realized as follows:
in a first aspect, an embodiment of the present application provides a register checking method, where the method includes:
reading a register address and register data in a target chip; sequentially searching an address node corresponding to the register address and at least one register segmented sub-node corresponding to the address node from the multi-layer register index;
analyzing the at least one register segmentation sub-node to obtain at least one register segmentation information, and converting the register data into at least one register value based on the at least one register segmentation information; the number of the at least one register value is the same as the number of the at least one register segment child node;
based on the at least one register value, respectively searching a value subnode corresponding to each register segmentation subnode from the multi-layer register index to obtain at least one value subnode;
and according to the at least one value sub-node, retrieving at least one register interpretation data segment from a register interpretation database corresponding to the multi-layer register index, so as to realize register check based on the at least one register interpretation data segment.
In a second aspect, an embodiment of the present application provides a register checking apparatus, including:
the reading unit is used for reading the register address and the register data in the target chip;
the searching unit is used for sequentially searching an address node corresponding to the register address and at least one register segmentation sub-node corresponding to the address node from the multi-layer register index;
the analysis unit is used for analyzing the at least one register segmentation sub-node to obtain at least one register segmentation information;
a conversion unit for converting the register data into at least one register value based on the at least one register segmentation information; the number of the at least one register value is the same as the number of the at least one register segment child node;
the searching unit is further configured to search, based on the at least one register value, one value sub-node corresponding to each register segment sub-node from the multi-layer register index, to obtain at least one value sub-node;
and the retrieval unit is used for retrieving at least one register interpretation data segment from a register interpretation database corresponding to the multi-layer register index according to the at least one value sub-node so as to realize register check based on the at least one register interpretation data segment.
In a third aspect, an embodiment of the present application provides a register checking apparatus, where the apparatus includes: a processor, a memory, and a communication bus; the processor, when executing the execution program stored in the memory, implements the method of any of the above.
In a fourth aspect, an embodiment of the present application provides a storage medium, on which a computer program is stored, where the computer program is executed by a processor to implement the method according to any one of the above methods.
The embodiment of the application provides a register checking method, a register checking device and a storage medium, wherein the method comprises the following steps: reading a register address and register data in a target chip; sequentially searching an address node corresponding to the register address and at least one register segmented sub-node corresponding to the address node from the multi-layer register index; analyzing the at least one register segmentation child node to obtain at least one register segmentation information, and converting the register data into at least one register value based on the at least one register segmentation information; the number of the at least one register value is the same as the number of the at least one register segmentation child node; respectively searching a value sub-node corresponding to each register segmentation sub-node from the multi-layer register index based on at least one register value to obtain at least one value sub-node; and according to the at least one value sub-node, retrieving at least one register interpretation data segment from a register interpretation database corresponding to the multi-layer register index so as to realize register check based on the at least one register interpretation data segment. By adopting the implementation scheme, the multilayer register indexes and the register paraphrase database corresponding to the multilayer register indexes are preset, after the register address and the register segmentation information in the target chip are read, at least one value-taking sub-node is determined based on the multilayer register indexes, and at least one register paraphrase data segment is retrieved from the register paraphrase database based on the at least one value-taking sub-node, so that the paraphrase data corresponding to the register can be positioned quickly, the checking efficiency is improved, and the time-consuming problem is reduced.
Drawings
Fig. 1 is a flowchart of a register checking method according to an embodiment of the present application;
fig. 2 is a flowchart of a dictionary file generation method according to an embodiment of the present application;
FIG. 3 is a block diagram illustrating an exemplary hardware specification standard document according to an embodiment of the present disclosure;
FIG. 4 is a block diagram illustrating an exemplary four-level binary tree chain register index according to an embodiment of the present disclosure;
fig. 5 is a schematic flowchart of an exemplary SOC software debugging method according to an embodiment of the present disclosure;
FIG. 6 is a first schematic structural diagram of a register checking apparatus according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of a register checking apparatus according to an embodiment of the present disclosure.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the present application. And are not intended to limit the present application.
An embodiment of the present application provides a register checking method, as shown in fig. 1, the method may include:
s101, reading a register address and register data in a target chip; and sequentially searching an address node corresponding to the register address and at least one register segmentation sub-node corresponding to the address node from the multi-layer register index.
The register checking method provided by the embodiment of the application can be applied to a scene of system fault elimination based on the register in the soc chip.
In the embodiment of the present application, the register indexing device may be any device having communication and storage functions, for example: tablet computers, mobile phones, personal Computers (PCs), notebook computers, wearable devices, and the like.
It should be noted that, on a platform requiring debugging, the CPU is driven to get down the register address of the SOC and the register data dump in the register address, and this process needs to load and run a register dump instruction to read the register address and the register data in the target chip. In the embodiment of the present application, the register dump instruction may be pre-designed based on specific implementation logic, such as performing segmentation or screening processing for a large number of registers.
In the embodiment of the application, after the register address and the register data in the target chip are read, the register address and the register data can be stored as a binary file data.
It should be noted that, after the register address and the register data in the target chip are read, the corresponding register interpretation data is searched from the hardware specification standard document, in order to improve the search efficiency, in the embodiment of the present application, for the hardware specification standard document, the relevant information of the register useful for hardware debugging is extracted from the hardware specification standard document to generate the multilayer register index and the register paraphrase database corresponding to the multilayer register index, and the multilayer register index and the register paraphrase database jointly form a dictionary file corresponding to the hardware specification standard document. The register checking means retrieves the interpretation data of the retrieved register in the SOC directly via the dictionary file. Firstly, after reading the register address and the register data, sequentially searching an address node corresponding to the register address and at least one register segmentation sub-node corresponding to the address node from the multi-layer register index.
In the embodiment of the application, the structure of the multilayer register index is a binary tree chain index with a multilayer structure, wherein a first layer register index in the multilayer register index is composed of a group of address nodes, each address node in the first layer register index points to a group of register segmentation sub-nodes in a second layer register index, and each register segmentation sub-node in the second layer register index points to a group of value-taking sub-nodes in a third layer register index; the group of address nodes, the group of register segmentation sub-nodes and the group of value sub-nodes are composed of a single linked list structure; the group of address nodes store address information of registers in the hardware specification standard document, the group of register segmentation sub-nodes store segmentation information corresponding to the address information of the registers in the hardware specification standard document, and the group of value-taking sub-nodes store value-taking ranges corresponding to the segmentation information corresponding to the address information of the registers in the hardware specification standard document.
Specifically, based on the multi-layer register index structure, after the register address and the register data in the target chip are read, the address node corresponding to the register address is searched from the first-layer register index, and at least one register segment child node pointed by the address node is determined from the second-layer register index.
Specifically, the process of generating the multi-level register index and register paraphrase database includes:
s201, extracting address information of a register, segmentation information corresponding to the address information, a value range corresponding to the segmentation information and interpretation data of each value in the value range from an original hardware specification standard document.
In the embodiment of the present application, the register related information in the original hardware specification standard document includes: the address information of the register, the segmentation information corresponding to the address information, the value range corresponding to the segmentation information and the interpretation data of each value in the value range.
FIG. 3 is a block diagram of an original hardware specification standard document, wherein the regOffset field describes the address information of the register, and the fieldRange stores the internal offset start and internal offset end of each block of the register in the form of [ internal offset end: internal offset start ]]Specifically, referring to fig. 3, the register is normally 32-bit unsigned int type data, and for the register with regOffset of 0x0000000, fieldange is [0]，[1:1]，[2:2]，[3:3]，[31:4]As can be seen, the [0]Occupy 1bit, [1]Occupy 1bit, [2]Occupy 1bit, [3]Occupy 1bit, [31]When the segment occupies 28 bits, the 0x0000000 segment information is 1bit, 1bit and 28bit, wherein the value range of 1bit is 0-1, and the value range of 28bit is 0-2 28 (ii) a The fieldDescription field describes the interpretation data for the segment information.
S202, establishing a register paraphrase database according to the explanation data.
In the embodiment of the application, a blank register paraphrase database is established, and after the interpretation data corresponding to each value is obtained, each piece of interpretation data is stored in the blank register paraphrase database to obtain the register paraphrase database.
S203, establishing a multi-layer register index based on the address information of the register, the hierarchical correspondence between the segmentation information corresponding to the address information and the value range corresponding to the segmentation information.
In the embodiment of the application, because the structure of the multilayer register index is a binary tree chain index of a multilayer structure, an index structure of the binary tree chain index of the multilayer structure is set based on a hierarchical correspondence relationship, the index structure is that a first layer register index in the multilayer register index is composed of a group of address nodes, each address node in the first layer register index points to a group of register segmentation sub-nodes in a second layer register index, and each register segmentation sub-node in the second layer register index points to a group of value-taking sub-nodes in a third layer register index; a group of address nodes, a group of register segmentation sub-nodes and a group of value sub-nodes are composed of a single linked list structure. And then sequentially storing the address information of the register into a group of address nodes, sequentially storing the segmentation information corresponding to the address information into a group of register segmentation sub-nodes, and sequentially storing the value range corresponding to the segmentation information into a group of value sub-nodes.
It should be noted that, for the singly linked list structure, each node may point to the next node of the same type, or point to the head pointer of its child chain table at the same time, and if the node is the last node of the singly linked list structure, the node may point to an empty node.
It should be noted that, before the address information of the register is sequentially stored in the group of address nodes, the address information of the register is first sorted according to the size of the offset address value to obtain the sorted address information, and then the sorted address information is sequentially stored in the group of address nodes, so that it can be ensured that the obtained binary tree is an ordered binary tree, and the efficiency of checking and comparing the register can be improved.
It should be noted that, in the process of setting a group of register segment sub-nodes, the reserved segment information in the segment information corresponding to the address information of the register may be first proposed to obtain the adjusted segment information, and then a group of register segment sub-nodes may be set based on the adjusted segment information. The number of the sub-nodes of a group of register segments can be greatly reduced, the complexity of the multi-layer register index is further reduced, and the storage size of the multi-layer register index is reduced.
Referring to fig. 3, fieldName of fieldrand [31 ].
S204, establishing the corresponding relation of the multilayer register index and the register paraphrase database according to the corresponding relation between the interpretation data and each value in the value range.
In the embodiment of the application, one value corresponds to one piece of interpretation data, so that the corresponding relation between the multi-layer register index and the register paraphrase database can be established according to the corresponding relation between the interpretation data and the value.
It should be noted that a fourth-layer register index may also be newly added in the multi-layer register index, the fourth-layer register index stores interpretation information of values, each value-taking child node in the third-layer register index points to an interpretation information identifier in the fourth-layer register index, and then, according to a corresponding relationship between the interpretation information identifier and the interpretation data, a corresponding relationship between the multi-layer register index and the register interpretation database is established. The specific three-layer register index structure or the specific four-layer register index structure of the multilayer register index can be selected according to actual conditions, and the embodiment of the present application is not particularly limited.
Based on the step descriptions of S201 to S204, a dictionary file corresponding to the original hardware specification standard document is generated, and taking a binary tree chain register index with a four-layer structure as an example, as shown in fig. 4, a schematic structural diagram of a dictionary file composed of a binary tree chain register index with a four-layer structure and an index paraphrase database is shown.
First-tier register index: what is saved is the offset address of the register, the right node of which points to the offset address of the next register, and the left node of which points to the segment information of the register, that is, the second-layer register index node in fig. 4, and the internal information of the structure is:
second-level register index,: the current segment information of the register is stored, the right node of the current segment information points to the next segment information in the register, the left node of the current segment information points to different value information in the current segment information, namely, the third layer index register node in fig. 4, and the internal information of the structure body is as follows:
third level register index: what is saved is that a value information in a certain segment information in the register, for example, a possible value of a 3-bit field may be {3 ' b0, 3 ' b1, 3 ' b10, 3 ' b11, 3 ' b100 \8230 }, a right node of which points to a next value information in a certain segment information in the register, and a left node of which points to an interpretation information identifier identified by a value information in a certain segment information in the register, that is, a fourth-layer index register node in fig. 4, and the internal information of the structure is:
fourth-layer index register: all nodes store an explanation information identifier identified by one value information in a certain segment information in the register, and specific explanation data is acquired from the register explanation database through the explanation information identifier.
After the dictionary file corresponding to the original hardware specification standard document is generated, the dictionary file may be saved as an original hardware specification standard dictionary file in a binary file format.
S102, analyzing at least one register segmentation sub-node to obtain at least one register segmentation information, and converting register data into at least one register value based on the at least one register segmentation information; the number of the at least one register value is the same as the number of the at least one register segment child node.
After the address node corresponding to the register address and the at least one register segment sub-node corresponding to the address node are sequentially found from the multi-layer register index, the at least one register segment sub-node is analyzed to obtain at least one register segment information, and the register data is converted into at least one register value based on the at least one register segment information.
In the embodiment of the application, the register segmentation sub-nodes store the segmentation information of the register, so that each register segmentation sub-node is respectively analyzed to obtain the register segmentation information corresponding to each register segmentation sub-node.
In the embodiment of the present application, the register segment information is a start offset and a stop offset corresponding to the register segment child node, and at least one bit value occupied by at least one register segment information may be determined based on at least one start offset and at least one corresponding stop offset; then dividing the register data into at least one segment of register data based on at least one bit value; carrying out the binary conversion on at least one segment of register data to obtain at least one register value.
It should be noted that at least one piece of register data is composed of an arrangement of 0 and 1, and therefore, at least one piece of register data is converted into a decimal value to determine at least one register value.
Illustratively, referring to fig. 3, the storage form of fieldange is [ internal offset termination: internal offset start ], for a register with regOffset of 0x0000004, fieldange is [ 1. And then, converting the 6 segments of data into decimal values, and determining 6 register values.
S103, respectively searching a value sub-node corresponding to each register segment sub-node from the multi-layer register index based on at least one register value to obtain at least one value sub-node.
In the embodiment of the application, based on at least one register value, one value subnode corresponding to each register segment subnode is searched from a third layer register index in a multi-layer register index, so as to obtain at least one value subnode.
Illustratively, if the register value is 3, a third value sub-node corresponding to the register segment sub-node is searched from the third-layer register index.
S104, according to the at least one value-taking sub-node, retrieving at least one register interpretation data segment from a register interpretation database corresponding to the multi-layer register index, so as to realize register check based on the at least one register interpretation data segment.
In the embodiment of the application, after at least one value sub-node is determined, a register interpretation data segment corresponding to each value sub-node is retrieved from a register interpretation database respectively to obtain at least one register interpretation data segment, and the at least one register interpretation data segment constitutes interpretation data of a corresponding register.
Further, after the interpretation data of the register is obtained, the interpretation data of the register may be saved and printed for review by a debugging.
Further, in the actual debugging process, expected values of registers may be preset in the hardware specification standard document, and then the expected values of each register are compared with the obtained register values, and whether the specifically implemented function of the register is the function that the hardware specification standard document expects to implement is determined according to the comparison result. The specific debugging process can be realized according to actual conditions, and the embodiment of the application is not specifically limited.
It can be understood that the multi-layer register index and the register paraphrase database corresponding to the multi-layer register index are preset, after the register address and the register segmentation information in the target chip are read, at least one value sub-node is determined based on the multi-layer register index, and at least one register paraphrase data segment is retrieved from the register paraphrase database based on the at least one value sub-node, so that the paraphrase data corresponding to the register can be positioned quickly, the checking efficiency is improved, and the time consumption problem is reduced.
Based on the foregoing embodiments, an embodiment of the present application provides an SOC software debugging method, as shown in fig. 5, the method may include:
1. extracting the original hardware specification standard text from the original hardware specification standard document, and extracting information useful for hardware debugging, including regOffset, fieldange and fieldDescription.
2. Establishing a binary tree chain index of a multilayer structure by utilizing regOffset and fieldRange, and establishing dictionary data of the binary tree chain index according to fieldDescription; the binary tree chain index and the dictionary data together form a dictionary file.
3. And storing the dictionary file as an original hardware specification standard dictionary file according to a binary file format.
4. A register dump instruction is loaded.
5. And (4) driving the processor to execute a register dump instruction at the target platform, and dumping the register address and the register data.
6. And storing the register address and the register data as a data file according to a binary file format.
7. And analyzing the data by using the original hardware specification standard dictionary file and the data file to obtain specific interpretation data of the register.
Specifically, reading in an index node of an original hardware specification standard dictionary file, and acquiring regOffset of each node; then, using regOffset as data offset, reading register data of the offset from the data file, wherein the register data is usually 32-bit unsigned integer; analyzing the sub-node 1 of regOffset, and acquiring internal segment information fieldRange; dividing register data into a plurality of pieces of data based on fieldRange, determining value information corresponding to each piece of data, analyzing a child node 1x of a child node 1 based on the value information, and respectively obtaining a plurality of explanation data segments corresponding to the plurality of pieces of data, wherein the explanation data segments form specific explanation data of the register.
8. And saving the specific interpretation data of the register for debugging and reading.
Based on the above embodiments, the present application provides a register checking apparatus 1. As shown in fig. 6, the apparatus 1 includes:
a reading unit 10 for reading a register address and register data in a target chip;
the searching unit 11 is configured to sequentially search an address node corresponding to the register address and at least one register segment sub-node corresponding to the address node from the multi-layer register index;
the analysis unit 12 is configured to analyze the at least one register segment child node to obtain at least one register segment information;
a conversion unit 13 for converting the register data into at least one register value based on the at least one register segmentation information; the number of the at least one register value is the same as the number of the at least one register segment child node;
the searching unit 11 is further configured to search, based on the at least one register value, one value sub-node corresponding to each register segment sub-node from the multi-layer register index, to obtain at least one value sub-node;
and the retrieval unit 14 is configured to retrieve at least one register interpretation data segment from the register interpretation database corresponding to the multi-layer register index according to the at least one value child node, so as to implement register checking based on the at least one register interpretation data segment.
Optionally, the apparatus further comprises: an extraction unit and a building unit;
the extracting unit is used for extracting the address information of the register, the segmentation information corresponding to the address information, the value range corresponding to the segmentation information and the interpretation data of each value in the value range from the original hardware specification standard document;
the establishing unit is used for establishing the register paraphrase database according to the interpretation data; establishing the multi-layer register index based on the address information of the register, the segmentation information corresponding to the address information and the hierarchy corresponding relationship between the value ranges corresponding to the segmentation information; and establishing the corresponding relation between the multilayer register index and the register paraphrase database according to the corresponding relation between the interpretation data and each value in the value range.
Optionally, the apparatus further comprises: a setting unit and a saving unit;
the setting unit is configured to set an index structure of the multilayer register index according to the hierarchical correspondence, where the index structure is that a first layer register index in the multilayer register index is composed of a group of address nodes, each address node in the first layer register index points to a group of register segment sub-nodes in a second layer register index, and each register segment sub-node in the second layer register index points to a group of value sub-nodes in a third layer register index; the group of address nodes, the group of register segmentation sub-nodes and the group of value sub-nodes are composed of a singly linked list structure;
the storage unit is configured to sequentially store the address information of the register into the group of address nodes, sequentially store the segment information corresponding to the address information into the group of register segment sub-nodes, and sequentially store the value range corresponding to the segment information into the group of value sub-nodes.
Optionally, the establishing unit is further configured to establish a corresponding relationship between the multiple layers of register indexes and the register paraphrase database by pointing each value-taking child node in the third layer of register indexes to corresponding interpretation data in the register paraphrase database.
Optionally, the apparatus further comprises: a sorting unit;
the sorting unit is used for sorting the address information of the register according to the size of the offset address value to obtain the sorted address information;
the storage unit is further configured to sequentially store the sorted address information into the group of address nodes.
Optionally, the apparatus further comprises: an adjustment unit;
the adjusting unit is used for eliminating reserved subsection information in the subsection information corresponding to the address information to obtain adjusted subsection information;
the setting unit is further configured to set the group of register segment sub-nodes based on the adjusted segment information.
Optionally, the register segment information is a start offset and an end offset corresponding to the register segment child node, and the apparatus further includes: a determination unit and a division unit;
the determining unit is configured to determine at least one bit value occupied by the at least one register segment information based on at least one start offset and at least one corresponding end offset;
the dividing unit is used for dividing the register data into at least one segment of register data based on the at least one bit value;
the conversion unit 13 is further configured to perform binary conversion on the at least one segment of register data to obtain the at least one register value.
The register checking device provided by the embodiment of the application reads a register address and register data in a target chip; sequentially searching an address node corresponding to the register address and at least one register segmented sub-node corresponding to the address node from the multi-layer register index; analyzing the at least one register segmentation child node to obtain at least one register segmentation information, and converting the register data into at least one register value based on the at least one register segmentation information; the number of the at least one register value is the same as the number of the at least one register segment child node; respectively searching a value subnode corresponding to each register segmentation subnode from the multi-layer register index based on at least one register value to obtain at least one value subnode; and according to the at least one value-taking sub-node, retrieving at least one register interpretation data segment from a register interpretation database corresponding to the multi-layer register index so as to realize register check based on the at least one register interpretation data segment. Therefore, according to the device provided by the embodiment, the multilayer register indexes and the register paraphrase database corresponding to the multilayer register indexes are preset, after the register address and the register segmentation information in the target chip are read, at least one dereferencing child node is determined based on the multilayer register indexes, and at least one register paraphrase data segment is retrieved from the register paraphrase database based on the at least one dereferencing child node, so that the paraphrase data corresponding to the register can be quickly positioned, the checking efficiency is improved, and the time consumption problem is reduced.
Fig. 7 is a schematic diagram of a second configuration of the register inspection apparatus 1 according to an embodiment of the present application, and in practical applications, based on the same public concept of the foregoing embodiment, as shown in fig. 7, the apparatus 1 of the present embodiment includes: a processor 15, a memory 16, and a communication bus 17.
In the process of the Specific embodiment, the reading unit 10, the searching unit 11, the parsing unit 12, the converting unit 13, the retrieving unit 14, the extracting unit, the establishing unit, the setting unit, the saving unit, the sorting unit, the adjusting unit, the determining unit and the dividing unit may be implemented by a Processor 15 located on the apparatus 1, and the Processor 15 may be at least one of an Application Specific Integrated Circuit (ASIC), a Digital Signal Processor (DSP), a Digital Signal Processing Device (DSPD), a Programmable Logic Device (PLD), a Field Programmable Gate Array (FPGA), a CPU, a controller, a microcontroller and a microprocessor. It is understood that the electronic device for implementing the above processor function may be other devices, and the embodiment is not limited in particular.
In the embodiment of the present application, the communication bus 17 is used for realizing connection communication between the processor 15 and the memory 16; the processor 15 implements the following register check method when executing the execution program stored in the memory 16:
reading a register address and register data in a target chip; sequentially searching an address node corresponding to the register address and at least one register segmentation sub-node corresponding to the address node from the multi-layer register index; analyzing the at least one register segmentation child node to obtain at least one register segmentation information, and converting the register data into at least one register value based on the at least one register segmentation information; the number of the at least one register value is the same as the number of the at least one register segmentation child node; based on the at least one register value, respectively searching a value sub-node corresponding to each register segmentation sub-node from the multi-layer register index to obtain at least one value sub-node; and according to the at least one value sub-node, retrieving at least one register interpretation data segment from a register interpretation database corresponding to the multi-layer register index, so as to realize register check based on the at least one register interpretation data segment.
Further, the processor 15 is further configured to extract address information of the register, segment information corresponding to the address information, a value range corresponding to the segment information, and interpretation data of each value in the value range from the original hardware specification standard document; establishing the register paraphrasing database according to the interpretation data; establishing the multi-layer register index based on the address information of the register, the segmentation information corresponding to the address information and the hierarchy corresponding relationship between the value ranges corresponding to the segmentation information; and establishing the corresponding relation between the multilayer register index and the register paraphrase database according to the corresponding relation between the interpretation data and each value in the value range.
Further, the processor 15 is further configured to set an index structure of the multilayer register index according to the hierarchical correspondence, where the index structure is that a first layer register index in the multilayer register index is composed of a group of address nodes, each address node in the first layer register index points to a group of register segment sub-nodes in a second layer register index, and each register segment sub-node in the second layer register index points to a group of value sub-nodes in a third layer register index; the group of address nodes, the group of register segmentation sub-nodes and the group of value sub-nodes are composed of a single linked list structure; sequentially storing the address information of the register into the group of address nodes, sequentially storing the segmentation information corresponding to the address information into the group of register segmentation sub-nodes, and sequentially storing the value range corresponding to the segmentation information into the group of value sub-nodes.
Further, the processor 15 is further configured to establish a corresponding relationship between the multi-layer register index and the register paraphrase database by pointing each value-taking child node in the third-layer register index to corresponding interpretation data in the register paraphrase database.
Further, the processor 15 is further configured to sort the address information of the register according to the size of the offset address value, so as to obtain the sorted address information; and sequentially storing the sequenced address information into the group of address nodes.
Further, the processor 15 is further configured to remove reserved segment information from segment information corresponding to the address information to obtain adjusted segment information; setting the set of register segment sub-nodes based on the adjusted segment information.
Further, the register segment information is a start offset and an end offset corresponding to the register segment sub-node,
said processor 15 is further configured to determine at least one bit value occupied by said at least one register segment information based on at least one start offset and corresponding at least one end offset; dividing the register data into at least one segment of register data based on the at least one bit value; and carrying out binary conversion on the at least one segment of register data to obtain the at least one register value.
The embodiment of the present application provides a storage medium, on which a computer program is stored, where the computer readable storage medium stores one or more programs, and the one or more programs are executable by one or more processors and applied to a register checking apparatus, and the computer program implements the register checking method as described above.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a component of' 8230; \8230;" does not exclude the presence of another like element in a process, method, article, or apparatus that comprises the element.
Through the description of the foregoing embodiments, it is clear to those skilled in the art that the method of the foregoing embodiments may be implemented by software plus a necessary general hardware platform, and certainly may also be implemented by hardware, but in many cases, the former is a better implementation. Based on such understanding, the technical solutions of the present disclosure may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling an image display device (e.g., a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method according to the embodiments of the present disclosure.
The above description is only a preferred embodiment of the present application, and is not intended to limit the scope of the present application.
Claims (10)
1. A register checking method, the method comprising:
reading a register address and register data in a target chip; sequentially searching an address node corresponding to the register address and at least one register segmented sub-node corresponding to the address node from the multi-layer register index;
analyzing the at least one register segmentation sub-node to obtain at least one register segmentation information, and converting the register data into at least one register value based on the at least one register segmentation information; the number of the at least one register value is the same as the number of the at least one register segment child node;
based on the at least one register value, respectively searching a value subnode corresponding to each register segmentation subnode from the multi-layer register index to obtain at least one value subnode;
and according to the at least one value sub-node, retrieving at least one register interpretation data segment from a register interpretation database corresponding to the multi-layer register index, so as to realize register check based on the at least one register interpretation data segment.
2. The method according to claim 1, wherein before sequentially searching the address node corresponding to the register address and the at least one register segment sub-node corresponding to the address node from the multi-layer register index, the method further comprises:
extracting address information of a register, segmentation information corresponding to the address information, a value range corresponding to the segmentation information and interpretation data of each value in the value range from an original hardware specification standard document;
establishing the register paraphrasing database according to the interpretation data;
establishing the multi-layer register index based on the address information of the register, the segmentation information corresponding to the address information and the hierarchy corresponding relationship between the value ranges corresponding to the segmentation information;
and establishing the corresponding relation between the multilayer register index and the register paraphrase database according to the corresponding relation between the interpretation data and each value in the value range.
3. The method according to claim 2, wherein the establishing the multi-level register index based on a hierarchical correspondence between address information of the register, segment information corresponding to the address information, and a value range corresponding to the segment information includes:
setting an index structure of the multilayer register indexes according to the hierarchical correspondence, wherein the index structure is that a first layer register index in the multilayer register indexes is composed of a group of address nodes, each address node in the first layer register index points to a group of register segment sub-nodes in a second layer register index, and each register segment sub-node in the second layer register index points to a group of value sub-nodes in a third layer register index; the group of address nodes, the group of register segmentation sub-nodes and the group of value sub-nodes are composed of a singly linked list structure;
sequentially storing the address information of the register into the group of address nodes, sequentially storing the segmentation information corresponding to the address information into the group of register segmentation sub-nodes, and sequentially storing the value range corresponding to the segmentation information into the group of value sub-nodes.
4. The method of claim 3, wherein establishing a correspondence between the multi-level register index and the register paraphrase database based on the correspondence between the interpretation data and each value in the range of values comprises:
and establishing the corresponding relation between the multi-layer register index and the register paraphrase database by pointing each dereferencing child node in the third-layer register index to corresponding interpretation data in the register paraphrase database.
5. The method of claim 3, further comprising:
sorting the address information of the register according to the size of the offset address value to obtain the sorted address information;
and sequentially storing the sequenced address information into the group of address nodes.
6. The method of claim 3, further comprising:
removing reserved subsection information in subsection information corresponding to the address information to obtain adjusted subsection information;
setting the set of register segment sub-nodes based on the adjusted segment information.
7. The method of claim 1, wherein the register segment information is a start offset and an end offset corresponding to a register segment subnode, and wherein converting the register data into at least one register value based on the at least one register segment information comprises:
determining at least one bit value occupied by the at least one register segment information based on at least one start offset and a corresponding at least one end offset;
dividing the register data into at least one segment of register data based on the at least one bit value;
and carrying out binary conversion on the at least one segment of register data to obtain the at least one register value.
8. A register checking apparatus, characterized in that the apparatus comprises:
the reading unit is used for reading the register address and the register data in the target chip;
the searching unit is used for sequentially searching an address node corresponding to the register address and at least one register segmentation sub-node corresponding to the address node from the multi-layer register index;
the analysis unit is used for analyzing the at least one register segmentation sub-node to obtain at least one register segmentation information;
a conversion unit for converting the register data into at least one register value based on the at least one register segmentation information; the number of the at least one register value is the same as the number of the at least one register segment child node;
the searching unit is further configured to search, based on the at least one register value, one value subnode corresponding to each register segment subnode from the multi-layer register index, to obtain at least one value subnode;
and the retrieval unit is used for retrieving at least one register interpretation data segment from a register interpretation database corresponding to the multi-layer register index according to the at least one value sub-node so as to realize register check based on the at least one register interpretation data segment.
9. A register checking apparatus, characterized in that the apparatus comprises: a processor, a memory; the processor, when executing the execution program stored in the memory, implements the method of any of claims 1-7.
10. A storage medium on which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 1 to 7.
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