CN115718626A - SOC (system on chip) system capable of being awakened quickly and quick awakening method - Google Patents

Abstract

The application provides a SOC system and a quick awakening method for quick awakening.A Central Processing Unit (CPU) is used for configuring a register of a power consumption control unit through a bus; receiving a sleep instruction or a wake-up instruction, and sending a sleep signal after receiving the sleep instruction; the sleeping working area peripheral module sends out a wake-up command when receiving the wake-up behavior; the power consumption management module comprises a DMA interaction unit and a dormancy control unit; after receiving a sleep signal, the DMA interaction unit carries a preloaded program to an instruction cache unit, and the sleep control unit controls the SOC system to enter a low power consumption state when receiving the sleep signal; and when the CPU receives the wake-up signal, the CPU reads the pre-loading program through the instruction cache unit and sends out the wake-up signal, and the sleep control unit controls the SOC system to exit from the low power consumption state. The invention greatly improves the efficiency of low power consumption state awakening.

Description

SOC (system on chip) system capable of being awakened quickly and quick awakening method

Technical Field

The application relates to the technical field of computers, in particular to a quick wake-up SOC system and a quick wake-up method.

Background

The SOC (system on chip) enters a dormant low-power-consumption working state, so that the dynamic power consumption and the static power consumption of the whole SOC system are effectively reduced, and meanwhile, the low-power-consumption clock domain peripheral is in a normal low-frequency working mode. At this time, after receiving the wake-up behavior, the SOC needs to wake up the entire system quickly to generate a response behavior in time. Therefore, fast wake-up techniques are needed to meet the real-time requirements.

In a conventional fast wake-up scheme in a low power consumption state, when a CPU exits a sleep mode, an instruction needs to be read from a nonvolatile memory module again and executed, but the nonvolatile memory module needs to be in a power-down state under low power consumption due to excessive static leakage power consumption, and therefore, after the CPU wakes up from the low power consumption state, power-up processing needs to be performed on the nonvolatile memory module again. The re-powering up of a non-volatile memory module requires certain power-up timing requirements and pre-loading operations within the module. These processing flows all bring too much delay of the wake-up time, and cannot satisfy the application scenario with low delay of the wake-up time.

Disclosure of Invention

In order to solve the above problem, embodiments of the present application provide a fast wake-up SOC system and a fast wake-up method, which greatly improve the efficiency of low power consumption sleep wake-up.

The application provides a SOC system capable of being awakened quickly, which comprises a CPU, a dormant working area peripheral module and a power consumption control module;

the CPU is used for configuring a register of the power consumption control unit through a bus; receiving a sleep instruction or a wake-up instruction, and sending a sleep signal after receiving the sleep instruction;

the sleeping working area peripheral module sends out a wake-up command when receiving the wake-up behavior;

the power consumption management module comprises a DMA interaction unit and a dormancy control unit; after receiving a sleep signal, the DMA interaction unit carries a preloaded program to an instruction cache unit, and the sleep control unit controls the SOC system to enter a low power consumption state when receiving the sleep signal;

and when the CPU receives the wake-up signal, the CPU reads the pre-loading program through the instruction cache unit and sends out the wake-up signal, and the sleep control unit controls the SOC system to exit from the low power consumption state.

Optionally, with reference to any one of the foregoing aspects, in another implementation manner of this aspect, the power consumption management unit further includes a storage module interaction unit, where the storage module interaction unit is connected to the storage module controller, and after receiving the hibernation signal, the hibernation control unit controls the storage module to be turned off through the storage module interaction unit; under the normal working state, the CPU reads the instruction stored in the storage module through the storage module controller to complete the working action.

Optionally, with reference to any one of the foregoing aspects, in another implementation manner of this aspect, a DMA controller is further provided, and the DMA interaction unit is connected to the DMA controller; and after the DMA interaction unit receives the sleep signal, the DMA controller is controlled to carry the pre-loading program stored by the storage module to the instruction cache unit.

Optionally, with reference to any one of the foregoing aspects, in another implementation manner of this aspect, the power consumption management module further includes a register configuration unit, where the register configuration unit receives configuration information of a CPU through a bus, and a configuration register controls a low power consumption behavior of the power consumption control module.

Optionally, with reference to any one of the foregoing aspects, in another implementation manner of this aspect, the power consumption management unit is further provided with a clock low-power-consumption interaction unit, the clock low-power-consumption interaction unit is connected to a system clock controller, and the clock low-power-consumption interaction unit controls a behavior of the whole SOC clock system when entering a low-power-consumption state or exiting the low-power-consumption state through the system clock controller.

The present application further provides a fast wake-up method for an SOC system, which is applied to any one of the above-mentioned SOC systems for fast wake-up, and the method includes the following steps:

s1, receiving a sleep instruction, and sending a sleep signal by a Central Processing Unit (CPU); after receiving the dormancy signal, the power consumption management module controls the DMA interaction unit to transfer the preloaded program to the instruction cache unit according to a DMA trigger mechanism;

s2, determining that the handling of the preloaded program is finished according to an overtime handshake judgment mechanism of the power consumption management module and the DMA interaction unit, and enabling the SOC to enter a low power consumption state;

and S3, after the peripheral module in the sleep working area receives the awakening instruction, the CPU reads the pre-loading program in the instruction cache unit, and the SOC exits the low power consumption state.

Optionally, with reference to any one of the foregoing aspects, in another implementation manner of this aspect, the power consumption management module and the timeout handshake determination mechanism of the DMA interaction unit are specifically configured to, when the DMA controller receives a request signal sent by the power consumption management module, return an acknowledgement signal to the power consumption management unit when the DMA controller carries a piece of preload program to the instruction cache unit; after the DMA control finishes all the carrying tasks, the count value of an overtime counter built in the DMA interaction unit is compared with a preset threshold value, and when the count value of the overtime counter is larger than the preset threshold value, the carrying of the preloading program is finished.

Optionally, with reference to any one of the foregoing aspects, in another implementation manner of the present aspect, the step S3 further includes the following steps:

step S31, after the peripheral module of the sleep working area receives a wake-up instruction, the clock low-power-consumption interaction unit opens a system clock through the system clock controller;

step S32, the storage interaction module powers on the storage module through the storage module controller; in the power-on process, the CPU exits from the low power consumption state, the CPU reads the pre-loading program in the instruction cache unit to complete quick awakening, and the SOC exits from the low power consumption state.

Optionally, with reference to any one of the foregoing aspects, in another implementation manner of this aspect, after the transferring of the preloaded program is completed, the method further includes the following steps:

and S21, closing the storage module in the storage interaction unit through the storage module controller, and closing the system clock in the clock low-power-consumption interaction unit through the system clock controller.

Optionally, with reference to any one of the above aspects, in another implementation manner of this aspect, the preload program includes an interrupt handler and a wake-up standby handler.

As described above, the present application provides a fast wake-up SOC system and a fast wake-up method, when the SOC system enters a low power consumption operating state, the SOC can be quickly woken up after receiving a wake-up signal, and the CPU quickly reads the preload program of the instruction cache unit during the wake-up process, so that the SOC system enters a normal operating mode. The system and the method have the advantages of quick response and low delay, and effectively meet the real-time requirement of system application.

The above summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. The above summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. The claimed subject matter is not limited to implementations that solve any or all disadvantages noted in the background.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application. In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments will be briefly described below, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise. These drawings and written description are not intended to limit the scope of the inventive concepts in any manner, but rather to illustrate the inventive concepts to those skilled in the art by reference to specific embodiments.

Fig. 1 is a block diagram of a fast wake-up SOC system according to the present disclosure;

fig. 2 is a schematic diagram illustrating a sleep flow of a fast wake-up method of an SOC system according to the present disclosure;

fig. 3 is a schematic diagram illustrating a wake-up flow of a fast wake-up method of an SOC system according to the present application;

fig. 4 is an interaction schematic of a DMA interaction unit of a fast wake-up method of an SOC system provided in the present application.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the application, as detailed in the appended claims.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the recitation of a claim "comprising a" 8230a "\8230means" does not exclude the presence of additional identical elements in the process, method, article or apparatus in which the element is incorporated, and further, similarly named components, features, elements in different embodiments of the application may have the same meaning or may have different meanings, the specific meaning of which should be determined by its interpretation in the specific embodiment or by further combination with the context of the specific embodiment.

It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope herein. The word "if" as used herein may be interpreted as "at" \8230; "or" when 8230; \8230; "or" in response to a determination ", depending on the context. Also, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes" and/or "including," when used in this specification, specify the presence of stated features, steps, operations, elements, components, items, species, and/or groups, but do not preclude the presence, or addition of one or more other features, steps, operations, elements, components, species, and/or groups thereof. The terms "or," "and/or," "including at least one of the following," and the like, as used herein, are to be construed as inclusive or mean any one or any combination. An exception to this definition will occur only when a combination of elements, functions, steps or operations are inherently mutually exclusive in some way.

It should be understood that, although the steps in the flowcharts in the embodiments of the present application are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and may be performed in other orders unless explicitly stated herein. Moreover, at least some of the steps in the figures may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, in different orders, and may be performed alternately or at least partially with respect to other steps or sub-steps of other steps.

The words "if", as used herein, may be interpreted as "at \8230; \8230when" or "when 8230; \823030, when" or "in response to a determination" or "in response to a detection", depending on the context. Similarly, the phrase "if determined" or "if detected (a stated condition or event)" may be interpreted as "upon determining" or "in response to determining" or "upon detecting (a stated condition or event)" or "in response to detecting (a stated condition or event)", depending on the context.

It should be understood that the specific embodiments described herein are merely illustrative of and not restrictive on the broad application.

Referring to fig. 1, the present application provides a fast wake-up SOC system and a fast wake-up method, which greatly improve the efficiency of low power consumption sleep wake-up.

The SOC system comprises a CPU, a sleep working area peripheral module and a power consumption control module. The CPU central processing unit can configure a register of the power consumption control unit through a bus; and receiving a sleep instruction or a wake-up instruction, and sending a sleep signal after receiving the sleep instruction. And the external module of the sleep working area is still in a normal working state when the SOC system enters the sleep working state, and generates a wake-up instruction to control the power consumption management unit when receiving an external wake-up behavior.

The power consumption management module comprises a register configuration unit, a dormancy control unit, a nonvolatile storage module interaction unit, a clock low-power-consumption interaction unit and a DMA interaction unit, and the SOC system is controlled to enter/exit a low-power-consumption state through the units. The register configuration unit receives configuration information of a Central Processing Unit (CPU) through a bus, controls low power consumption behaviors of the power consumption control module through a register in the configuration unit, and reads current state information of the power consumption management module through a state register read by software. The sleep control unit controls the SOC system to enter a low power consumption state after receiving a sleep signal of the CPU, and controls the SOC system to exit the low power consumption state after receiving a wake-up signal sent by a peripheral module working in the low power consumption state

And the DMA interactive unit is an important control unit for quick wake-up and is connected with the DMA controller. And after receiving the sleep signal, the DMA interaction unit carries the preloading program stored in the storage module to the instruction cache unit through the DMA controller. The DMA controller can also set the target address and the program size of the preloading program through configuration so as to meet various application scenes.

The power consumption management unit is further provided with a nonvolatile storage module interaction unit, the storage module interaction unit is connected with the storage module controller, the dormancy control unit controls the storage module to be closed through the storage module interaction unit after receiving the dormancy signal, and the nonvolatile storage module is started in the awakening process. Under a normal working state, the CPU reads the instruction stored in the storage module through the storage module controller to complete a working action, and the CPU needs to interact with the flash memory particles to control the time sequence for a long time when reading the instruction normally.

The power consumption management unit is also provided with a clock low-power consumption interaction unit, the clock low-power consumption interaction unit is connected with a system clock controller, and the clock low-power consumption interaction unit controls the behavior of the whole SOC clock system when entering a low-power consumption state or exiting the low-power consumption state through the system clock controller. And the system clock is turned off in the process of entering the low power consumption state to save power consumption, and the system clock is turned on in the process of exiting the sleep working mode to restore the normal working mode of the system.

The SOC system reasonably designs the low-power-consumption entering and exiting mechanism, and the CPU quickly accesses the nonvolatile storage module instruction program in the process of exiting the low-power-consumption working state and timely and quickly responds to the awakening action. Next, a fast wake-up method of the SOC system will be described in detail.

As shown in fig. 2 and 3, the method comprises the following steps:

s1, receiving a sleep instruction, and sending a sleep signal by a Central Processing Unit (CPU); and the power consumption management module controls the DMA interaction unit to carry the pre-loading program to the instruction cache unit according to the DMA trigger mechanism. The CPU central processing unit receives a software WFI instruction, sends a sleep signal, and in the process of entering a low power consumption state, the power consumption management module appoints a pre-loading program, namely a target address and a program size, through a general DMA controller or a special DMA controller and reads a program to be executed in a nonvolatile storage module. Only the reading operation of the one-way DMA is needed to be executed, and the cache of the preloaded program is realized, so that the CPU can be rapidly read in the subsequent awakening process.

And S2, determining that the pre-loaded program is transported completely according to an overtime handshake judgment mechanism of the power consumption management module and the DMA interaction unit, and enabling the SOC system to enter a low power consumption state.

The TIMEOUT handshake determination mechanism of the power management module and the DMA interaction unit is specifically, as shown in fig. 4, related to signal interaction between the DMA interaction unit in the power management unit and the DMA controller, and the determination mechanism is a handshake determination mechanism of req-ack TIMEOUT. The dormancy controller is not limited to the length and the address of the preloading program, is specified by a DMA controller channel configured by a user, and when the DMA controller receives a req request signal sent by the power consumption management module, the DMA controller returns an ack confirmation signal to the power consumption management unit every time the DMA controller carries a preloading program to the instruction cache unit; after the DMA control finishes all the carrying tasks, the count value of a TIMEOUT TIMEOUT counter built in the DMA interaction unit is compared with a preset threshold value, when the count value of the TIMEOUT counter is larger than the preset threshold value, it indicates that no expected carrying event of the preloaded program occurs in a specified time interval, and the hardware can judge that the DMA carrying action is finished and then the carrying of the preloaded program is finished. And then clearing the count value of the TIMEOUT TIMEOUT counter, and enabling the system to enter a low power consumption state after the preloading operation is completed.

After the pre-loading program is carried out, the method further comprises the following steps:

and S21, closing the storage module through the storage module controller in the storage interaction unit, closing a system clock through the system clock controller in the clock low-power-consumption interaction unit, and enabling the SOC to enter a low-power-consumption state, so that the dynamic power consumption and the static power consumption of the whole SOC are effectively reduced.

And S3, after the peripheral module in the sleep working area receives the awakening instruction, the CPU reads the pre-loading program in the instruction cache unit, and the SOC exits the low power consumption state.

The step S3 further comprises the following steps:

step S31, after the peripheral module of the sleep working area receives a wake-up instruction, the clock low-power-consumption interaction unit opens a system clock through the system clock controller;

step S32, the storage interaction module powers on the storage module through the storage module controller; in the power-on process, the CPU exits from the low power consumption state, a pre-loading program in the instruction cache unit is read, the quick awakening is completed, and the SOC exits from the low power consumption state. After the system clock is started, the power consumption management module can selectively electrify the nonvolatile storage module unit again, does not wait for the completion of the electrifying time sequence of the flash memory or the completion of the electrifying preloading operation, and can immediately recover to a normal working state. In the process of power-on recovery of the nonvolatile storage module, the CPU can respond to interrupt and execute program operation behaviors after awakening in parallel, command mapping addresses do not need to be switched, response commands are read from the nonvolatile storage module addresses, the preloaded programs are directly returned through the cache, and the read commands cannot be issued to the nonvolatile storage module controller, so that the time of the processor waiting for flash memory recovery is saved, and high-efficiency and rapid awakening recovery operation is realized.

In the whole process of quick awakening of the SOC system, only the sleep working area peripheral module receives the awakening instruction and is triggered by software, all the rest actions are completed by hardware independently, software participation is not needed, the low-power-consumption sleep awakening efficiency is greatly improved, and software operation is facilitated.

The application provides a quick awakening SOC system and a quick awakening method, when the SOC system enters a low-power-consumption working state, the SOC can be quickly awakened after an awakening signal is received, and a CPU (central processing unit) quickly reads a preloading program of an instruction cache unit in the awakening process to enable the SOC system to enter a normal working mode. The system and the method have the advantages of quick response and low delay, and effectively meet the real-time requirement of system application.

The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.

In the present application, the same or similar term concepts, technical solutions and/or application scenario descriptions will be generally described only in detail at the first occurrence, and when the description is repeated later, the detailed description will not be repeated in general for brevity, and when understanding the technical solutions and the like of the present application, reference may be made to the related detailed description before the description for the same or similar term concepts, technical solutions and/or application scenario descriptions and the like which are not described in detail later.

In the present application, each embodiment is described with emphasis, and reference may be made to the description of other embodiments for parts that are not described or illustrated in any embodiment.

The technical features of the technical solution of the present application may be arbitrarily combined, and for brevity of description, all possible combinations of the technical features in the embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, the scope of the present application should be considered as being described in the present application.

Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (e.g., an electric device or a network device) to execute the method of each embodiment of the present application.

The above description is only a preferred embodiment of the present application, and not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application, or which are directly or indirectly applied to other related technical fields, are included in the scope of the present application.

Claims (10)

1. A SOC system capable of being awakened quickly is characterized by comprising a CPU, a dormant working area peripheral module and a power consumption control module;

the CPU is used for configuring a register of the power consumption control unit through a bus; receiving a sleep instruction or a wake-up instruction, and sending a sleep signal after receiving the sleep instruction;

the sleeping working area peripheral module sends out a wake-up command when receiving the wake-up behavior;

the power consumption management module comprises a DMA interaction unit and a dormancy control unit; after receiving a sleep signal, the DMA interaction unit carries a preloaded program to an instruction cache unit, and the sleep control unit controls the SOC system to enter a low power consumption state when receiving the sleep signal;

and when the CPU receives the wake-up signal, the CPU reads the pre-loading program through the instruction cache unit and sends out the wake-up signal, and the sleep control unit controls the SOC system to exit from the low power consumption state.

2. The SOC system according to claim 1, wherein the power management unit further comprises a storage module interface unit, the storage module interface unit is connected to the storage module controller, and the sleep control unit controls the storage module to be turned off through the storage module interface unit after receiving the sleep signal; under the normal working state, the CPU reads the instruction stored in the storage module through the storage module controller to complete the working action.

3. A fast wake up SOC system as claimed in claim 2, wherein: the DMA interaction unit is connected with the DMA controller; and after receiving the sleep signal, the DMA interaction unit controls the DMA controller to transfer the pre-loading program stored by the storage module to the instruction cache unit.

4. A fast wake up SOC system as claimed in claim 3, wherein: the power consumption management module also comprises a register configuration unit, the register configuration unit receives configuration information of a Central Processing Unit (CPU) through a bus, and a configuration register controls the low power consumption behavior of the power consumption control module.

5. The fast wake up SOC system of claim 4, wherein: the power consumption management unit is also provided with a clock low-power consumption interaction unit, the clock low-power consumption interaction unit is connected with a system clock controller, and the clock low-power consumption interaction unit controls the behavior of the whole SOC clock system when entering a low-power consumption state or exiting the low-power consumption state through the system clock controller.

6. A fast wake-up method for SOC system, which is applied to the fast wake-up SOC system as claimed in any one of claims 1 to 5, the method comprising the steps of:

s1, receiving a sleep instruction, and sending a sleep signal by a Central Processing Unit (CPU); after receiving the dormancy signal, the power consumption management module controls the DMA interaction unit to carry the preloaded program to the instruction cache unit according to a DMA trigger mechanism;

s2, determining that the handling of the preloaded program is finished according to an overtime handshake judgment mechanism of the power consumption management module and the DMA interaction unit, and enabling the SOC to enter a low power consumption state;

and S3, after the peripheral module in the sleep working area receives the awakening instruction, the CPU reads the pre-loading program in the instruction cache unit, and the SOC exits the low power consumption state.

7. The fast wake-up method of a SOC system of claim 2, wherein: the overtime handshake judgment mechanism of the power consumption management module and the DMA interaction unit is specifically that when the DMA controller receives a request signal sent by the power consumption management module, the DMA controller returns a confirmation signal to the power consumption management unit every time the DMA controller carries a pre-loading program to the instruction cache unit; after the DMA control finishes all the carrying tasks, the count value of an overtime counter built in the DMA interaction unit is compared with a preset threshold value, and when the count value of the overtime counter is larger than the preset threshold value, the carrying of the preloading program is finished.

8. The fast wake-up method of a SOC system of claim 7, wherein: the step S3 further includes the following steps:

step S31, after the peripheral module of the sleep working area receives a wakeup instruction, the clock low-power-consumption interaction unit opens a system clock through the system clock controller;

step S32, the storage interaction module powers on the storage module through the storage module controller; in the power-on process, the CPU exits from the low power consumption state, the CPU reads the pre-loading program in the instruction cache unit to complete quick awakening, and the SOC exits from the low power consumption state.

9. The fast wake-up method of a SOC system of claim 7, wherein: in the step S2, after the transferring of the preloaded program is completed, the method further includes the following steps:

and S21, closing the storage module in the storage interaction unit through the storage module controller, and closing the system clock in the clock low-power-consumption interaction unit through the system clock controller.

10. The fast wake-up method of a SOC system of claim 6, wherein: the pre-loading program comprises an interrupt processing program and a wake-up standby program.

Images