CN115706012A - Method for forming semiconductor structure - Google Patents

Abstract

A method of forming a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a base and a plurality of fin parts which are positioned on the base and are separated from each other, and an isolation layer is arranged on the surface of the base; forming a plurality of mutually-separated gate structures on the isolation layer, wherein the gate structures cross the fin parts and comprise gate electrodes and side walls; forming source and drain openings in the fin parts on two sides of the gate structure; attaching defect seeds to the surface of the side wall, and forming a sacrificial film on the surface of the defect seeds by adopting a selective epitaxial growth process after the source-drain opening is formed, wherein the sacrificial film is also positioned between the surface of the defect seeds and the surface of the side wall; removing the sacrificial film by adopting a pre-cleaning process to strip the defect seeds; and forming a source drain structure in the source drain opening after the pre-cleaning process, wherein the top surface of the source drain structure is higher than or flush with the top surface of the fin part. The semiconductor structure formed by the method has good reliability.

Description

Method for forming semiconductor structure

Technical Field

The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.

Background

As the integrated circuit is developed to the ultra-large scale integrated circuit, the circuit density inside the integrated circuit is increased, the number of the contained components is increased, and the sizes of the components are reduced. As the size of semiconductor structures decreases, the channels of devices in the semiconductor structures are reduced. As the channel shrinks, the graded channel approximation no longer holds, but various adverse physical effects (especially short channel effects) are highlighted, which degrade device performance and reliability, limiting further device scaling.

In order to overcome the short channel effect of the device and suppress the leakage current, the prior art proposes a Fin field effect transistor (Fin FET), which is a common multi-gate device, and the structure of the Fin FET includes: the isolation layer covers a part of the side wall of the fin part, and the surface of the isolation layer is lower than the top of the fin part; the grid electrode structure is positioned on the surface of the isolation layer, the top of the fin part and the surface of the side wall; and the source region and the drain region are positioned in the fin parts at two sides of the grid structure.

However, the reliability of the semiconductor structure still needs to be improved in the prior art.

Disclosure of Invention

The invention provides a method for forming a semiconductor structure, which aims to improve the reliability of the semiconductor structure.

In order to solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a base and a plurality of fin parts which are positioned on the base and are separated from each other, an isolation layer is arranged on the surface of the base, the isolation layer is also positioned between the adjacent fin parts, and the surface of the isolation layer is lower than the top surfaces of the fin parts; forming a plurality of mutually-separated gate structures on the isolation layer, wherein the gate structures cross the fin parts and comprise gate oxide layers, gate electrodes positioned on the surfaces of the gate oxide layers and side walls positioned on the side walls of the gate oxide layers and the gate electrodes; forming source and drain openings in the fin parts on two sides of the gate structure; attaching defect seeds to the surface of the side wall, and forming a sacrificial film on the surface of the defect seeds by adopting a selective epitaxial growth process after the source drain opening is formed, wherein the sacrificial film is also positioned between the surface of the defect seeds and the surface of the side wall; removing the sacrificial film by adopting a pre-cleaning process to strip the defect seeds; and forming a source drain structure in the source drain opening after the pre-cleaning process, wherein the top surface of the source drain structure is higher than or flush with the top surface of the fin portion.

Optionally, in the process of forming the sacrificial film by using a selective epitaxial growth process, a growth rate of a material of the sacrificial film on the surface of the sidewall is less than a growth rate of a material of the sacrificial film on the surface of the defect seed.

Optionally, the sacrificial film is made of silicon germanium with a germanium concentration within a preset range, the pre-cleaning process is a dry cleaning process, and a reaction gas adopted by the dry cleaning process includes hydrogen chloride gas.

Optionally, in the material of the sacrificial film, the concentration range of germanium is 10% to 20%.

Optionally, the parameters of the selective epitaxial growth process for forming the sacrificial film include: the pressure range is 10 torr to 30 torr.

Optionally, the parameters of the selective epitaxial growth process for forming the sacrificial film further include: the gas comprises GeH ₄ And, geH ₄ The flow rate of (c) is in the range of 15 standard milliliters/minute to 25 standard milliliters/minute.

Optionally, the parameters of the pre-cleaning process further include: the flow range of the hydrogen chloride gas is 100 standard milliliters/minute to 200 standard milliliters/minute.

Optionally, the parameters of the pre-cleaning process further include: the pressure range is 5 to 20 torr; the temperature range is 600 ℃ to 700 ℃.

Optionally, the sacrificial film is further located on at least a part of an inner wall surface of the source-drain opening, and the sacrificial film on the inner wall surface of the source-drain opening is removed in the process of removing the sacrificial film by using a pre-cleaning process.

Optionally, the source-drain structure includes silicon phosphide.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:

in the method for forming the semiconductor structure provided by the technical scheme of the invention, the defect seeds are attached to the surface of the side wall when the source/drain opening is formed, or the defect seeds are attached to the surface of the side wall before the source/drain opening is formed. Because a sacrificial film is formed on the surface of the defect seed by adopting a selective epitaxial growth process and the sacrificial film is also positioned between the surface of the defect seed and the surface of the side wall, the sacrificial film with a known material can be selectively formed on the surface of the defect seed so as to select corresponding reaction gas according to the known material, so that in the pre-cleaning process performed by the pre-cleaning process, the chemical reaction between the reaction gas and the sacrificial film is stronger and the controllability is better, and therefore, the effects of removing the sacrificial film and stripping the defect seed wrapped by the sacrificial film are better. Therefore, in the process of forming the source-drain structure, the risk of forming more defect structures with larger volume on the surface of the side wall is low, and therefore the risk of short circuit of the semiconductor device is low, and the reliability of the semiconductor structure is improved.

Furthermore, the chemical reaction of the hydrogen chloride gas and the silicon is stronger and has better controllability. On one hand, because the material of the sacrificial film comprises silicon germanium and the concentration of germanium in the material of the sacrificial film is within a preset range, and on the other hand, because the dry cleaning process that the reaction gas comprises hydrogen chloride gas is adopted, the chemical reaction with stronger strength and good controllability can be realized between the reaction gas and the sacrificial film, and therefore, the effects of removing the sacrificial film and stripping the defect seeds wrapped by the sacrificial film are good.

Drawings

FIGS. 1-2 are schematic cross-sectional views of steps in a process for forming a semiconductor structure;

FIG. 3 is a distribution diagram of the defects of FIG. 2 on a semiconductor structure;

FIGS. 4-9 are schematic cross-sectional views illustrating steps of a method of forming a semiconductor structure according to an embodiment of the present invention;

figure 10 is a distribution diagram of a defective structure on a semiconductor structure in an embodiment of the present invention.

Detailed Description

As described in the background, the reliability of existing semiconductor structures still remains to be improved. Reference will now be made in detail to the following drawings.

Fig. 1 to 2 are schematic cross-sectional views of steps in a process for forming a semiconductor structure.

Referring to fig. 1, a substrate (not shown) is provided, the substrate having a plurality of fins 100 separated from each other; forming an isolation layer (not shown) on the surface of the substrate, wherein the isolation layer is also located between adjacent fins 100, and the surface of the isolation layer is lower than the top surfaces of the fins 100; a number of mutually discrete gate structures 110 are formed on the isolation layer.

Referring to fig. 2, a source-drain opening (not shown) is formed in the fin 100 at two sides of the gate structure 110; a selective epitaxy process is employed to form a source drain structure 120 within the source drain opening.

In the above method, in the process of forming the source/drain structure 120 by using the selective epitaxy process, the material of the source/drain structure 120 selectively grows on the inner wall surface of the source/drain opening, and at the same time, the material is easily attached to the surface of the defect seed 111 (as shown in fig. 1) on the sidewall of the gate structure 110 to grow, where the defect seed 111 is, for example, a residue on the surface of the gate structure 110 in the preceding process of forming the source/drain structure 120. Therefore, when the source-drain structure 120 is formed, a large number of defects 130 (as shown in fig. 2 and fig. 3) with a large volume are formed on the surface of the gate structure 110, which results in a high risk of short circuit of the formed semiconductor device and poor reliability of the semiconductor device.

In order to solve the problem of forming more and bulky defects 130 on the surface of the gate structure 110, another method for forming a semiconductor structure is proposed. In the forming method, before the source-drain structure 120 is formed by adopting a selective epitaxial process, the surface of the gate structure 110 is pre-cleaned to remove the defect seeds 111, so as to achieve the purpose of reducing the defects 130.

However, since the material of the defect seed 111 is difficult to determine, the controllability of the chemical reaction between the reaction gas used for the pre-cleaning and the defect seed 111 is poor, so that the pre-cleaning has a poor effect of removing the defect seed 111, and thus more defects 130 with larger volume are still formed on the surface of the gate structure 110. Thus, the reliability of the semiconductor device is still poor.

In order to solve the technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, in which a sacrificial film is formed on a surface of a defect seed, and a precleaning process is used to remove the sacrificial film to strip the defect seed, so that reliability of the formed semiconductor structure can be effectively improved.

In the pre-cleaning process performed by the pre-cleaning process, the chemical reaction between the reaction gas and the sacrificial film is strong and has good controllability, so that the effects of removing the sacrificial film and stripping the defect seeds wrapped by the sacrificial film are good. Therefore, in the process of forming the source-drain structure, the risk of forming more defect structures with larger volume on the surface of the gate structure is low, so that the risk of short circuit of a semiconductor device is low, and the reliability of the semiconductor structure is improved.

In order to make the aforementioned objects, features and advantages of the present invention more comprehensible, embodiments accompanying figures are described in detail below.

Fig. 4 to 9 are schematic cross-sectional views of steps of a method for forming a semiconductor structure according to an embodiment of the invention.

Referring to fig. 4 and 5, fig. 4 is a schematic perspective view of fig. 5, and fig. 5 is a schematic cross-sectional view taken along the direction X1-X2 in fig. 4, providing a substrate 200.

The substrate 200 includes: the semiconductor device comprises a substrate 201 and a plurality of mutually-separated fin parts 202 located on the substrate 201, wherein an isolation layer 203 is arranged on the surface of the substrate 201, the isolation layer 203 is also located between the adjacent fin parts 202, and the surface of the isolation layer 203 is lower than the top surfaces of the fin parts 202.

The role of the spacer layer 203 is to: electrically isolating adjacent fins 202 and the semiconductor device from the substrate 201.

In other embodiments, the substrate is a planar substrate.

The material of the substrate 200 comprises a semiconductor material.

Specifically, the material of the substrate 200 includes silicon.

In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-element semiconductor material of group iii-v elements, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. The multielement semiconductor material composed of III-V group elements comprises InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP and the like.

Referring to fig. 6, fig. 6 is a view in the same direction as fig. 5, and several gate structures 210 are formed separately on the isolation layer 203 (as shown in fig. 4), where the gate structures 210 cross over the top surface and part of the sidewall surface of the fin 202.

In this embodiment, the gate structure 210 includes: the gate oxide layer 211, the gate 212 positioned on the surface of the gate oxide layer 211, and the sidewall 213 positioned on the sidewalls of the gate oxide layer 211 and the gate 212.

The gate oxide layer 211 comprises silicon oxide, the gate electrode 212 comprises polysilicon or amorphous silicon, and the sidewall spacer 213 comprises a low-k dielectric material (k is less than 3.9) or a combination of low-k dielectric materials, wherein the low-k dielectric material comprises SiOC, siOCN, siOCH, etc.

The sidewall spacers 213 are used to define the positions of the source and drain openings in the following.

In the present embodiment, the method for forming the gate structure 210 includes: forming a gate oxide material film (not shown) on the isolation layer 203; forming a gate material layer (not shown) on the surface of the gate oxide material film; forming a plurality of gate mask structures 214 separated from each other on the surface of the gate material layer; etching the gate material layer and the gate oxide material film by taking the gate mask structure 214 as a mask until the surface of the isolation layer 203 is exposed to form the gate 212 and the gate oxide layer 211; and forming a side wall 213 on the side walls of the gate oxide layer 211 and the gate electrode 212.

The forming process of the gate material layer comprises the following steps: an epitaxial growth process, a deposition process, or the like, the deposition process including a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or the like.

The gate mask structure 214 is used to pattern a gate oxide material film and a gate material layer to form the gate oxide layer and the gate electrode 211. In addition, the gate mask structure 214 and the sidewall 213 are used to protect the surfaces of the gate electrode 212 and the gate oxide layer 211, so as to reduce damage to the gate electrode 212 and the gate oxide layer 211 in the subsequent etching process for forming the source-drain structure. Moreover, in the subsequent selective epitaxial growth process for forming the source/drain structure, the selectivity of the epitaxial growth process is realized through the gate mask structure 214 and the side wall 213 which are made of different materials from the substrate 200.

In the present embodiment, the material of the gate mask structure 214 includes silicon nitride.

In other embodiments, the material of the gate mask structure includes silicon nitride and silicon oxide, the silicon oxide being located between the gate and the silicon nitride.

With continued reference to fig. 6, source-drain openings 230 are formed in the fin 202 at two sides of the gate structure 210.

The source and drain openings 230 provide space for the subsequent formation of source and drain structures.

Defect seeds 220 are attached to the surfaces of the side walls 213210. The defect seeds 220 are, for example, residues, contaminants, etc. on the surface of the gate structure 210 during the processes of forming the gate structure 210 and the source/drain openings 230, or during the transfer process between the cavities and the machines.

The defect seeds 220 are, for example, metal materials, silicon, small organic molecules, acid ions, metal ion attachments, silicon atom aggregates in localized regions of silicon-based materials, and the like.

In this embodiment, the method for forming the source/drain opening 230 includes: forming a source-drain mask layer (not shown) on the surface of the substrate 200 and the surface of the gate structure 210, wherein the source-drain mask layer exposes the surface of the fin portion 202 between the adjacent gate structures 210; and etching the fin portion 202 by using the source/drain mask layer and the side walls 213 as masks, and forming source/drain openings 230 in the fin portion 202 on two sides of the gate structure 210.

In this embodiment, the etching process for forming the source/drain opening 230 includes: at least one of a dry etching process and a wet etching process.

In other embodiments, the substrate is a planar substrate. On the basis, source-drain openings are formed in the substrate on two sides of the gate structure.

In this embodiment, after the source/drain opening 230 is formed, the source/drain mask layer is removed.

Referring to fig. 7, the view directions of fig. 7 and fig. 6 are the same, and a selective epitaxial growth process is adopted to form a sacrificial film 240 on the surface of the defect seed 220 (as shown in fig. 6), where the sacrificial film 240 is further located between the surface of the defect seed 220 and the surface of the sidewall 213 (as shown in the region a).

The sacrificial film 240 located on the surface of the defect seed 220 (including the sacrificial film 240 located between the surface of the defect seed 220 and the surface of the sidewall spacer 213) functions as: a subsequent pre-cleaning process is combined to strip the defect seed 220.

In this embodiment, since the sacrificial film 240 is formed after the source/drain opening 230 is formed, not only the defect seeds 220 remaining on the surface of the sidewall 213 in the previous process before the source/drain opening 230 is formed, but also the defect seeds 220 remaining on the surface of the sidewall 213 in the etching process for forming the source/drain opening 230, and the like can be stripped. Therefore, by combining with the subsequent precleaning process, the defect seeds 220 on the surface of the side wall 213 can be further reduced, and the reliability of the semiconductor structure can be better improved.

In this embodiment, in the process of forming the sacrificial film 240 by using a selective epitaxial growth process, the growth rate of the material of the sacrificial film 240 on the surface of the sidewall 213 is less than the growth rate of the material of the sacrificial film 240 on the surface of the defect seed 220.

In the present embodiment, the material of the sacrificial film 240 includes silicon germanium, and the concentration of germanium in the silicon germanium is within a predetermined range.

The purpose of having the concentration of germanium within a preset range is to: the material of the sacrificial film 240 can be made to react better in a subsequent preclean process.

Preferably, the concentration of germanium in the material of the sacrificial film 240 ranges from 10% to 20%.

In this embodiment, the parameters of the selective epitaxial growth process for forming the sacrificial film 240 include: the pressure range is 10 torr to 30 torr.

By adopting the above parameters to perform the selective epitaxy process, the material of the sacrificial film 240 can be grown slowly, the controllability of the selective epitaxy process is improved, and the sacrificial film 240 with continuous and uniform thickness can be formed on the surface of the defect seed 220, so that the formed sacrificial film 240 can better wrap the defect seed 220, thereby further facilitating the removal of the sacrificial film 240 and the peeling of the defect seed 220 in the subsequent precleaning process. Meanwhile, by adopting the above parameters to perform the selective epitaxy process, the concentration range of germanium in the material of the sacrificial film 240 can also be controlled to be 10% -20%, so that in the subsequent precleaning process, the material of the sacrificial film 240 can be better reacted.

In this embodiment, the parameters of the selective epitaxial growth process for forming the sacrificial film 240 further include: the gas comprises GeH ₄ And, geH ₄ The flow rate of (c) is in the range of 15 to 25 standard ml/min.

In this embodiment, since the sacrificial film 240 is formed after the source-drain openings 230 are formed, the sacrificial film 240 is also located on at least part of the inner wall surfaces of the source-drain openings 230. The sacrificial film 240 on the inner wall surface of the source-drain opening 230 will be removed together with the sacrificial film 240 on the surface of the defect seed 220 in the subsequent precleaning process.

It should be understood that, the purpose of forming the sacrificial film 240 is to combine with a subsequent precleaning process to strip the defect seed 220, and the sacrificial film 240 on the inner wall surface of the source/drain opening 230 and the sacrificial film 240 on the surface of the defect seed 220 are removed together in the subsequent precleaning process, so that the shape, thickness and other parameters of the sacrificial film 240 on the inner wall surface of the source/drain opening 230 have no influence on the technical solution of the present invention, and the sacrificial film 240 on the inner wall surface of the source/drain opening 230 is not necessarily continuous.

Referring to fig. 8, in a view direction consistent with that of fig. 7, the sacrificial film 240 is removed by a pre-cleaning process to strip the defect seeds 220 (shown in fig. 6).

Because the sacrificial film 240 is formed on the surface of the defect seed 220 by adopting a selective epitaxial growth process, and the sacrificial film 240 is also positioned between the surface of the defect seed 220 and the surface of the sidewall 213, the sacrificial film 240 with a known material can be selectively formed on the surface of the defect seed 220, so that the corresponding reaction gas is selected according to the known material, and the chemical reaction between the reaction gas and the sacrificial film 240 is stronger and the controllability is better in the process of pre-cleaning by adopting the pre-cleaning process, so that the effects of removing the sacrificial film 240 and peeling the defect seed 220 covered by the sacrificial film 240 are good. Therefore, in the subsequent process of forming the source-drain structure, the risk of forming more defect structures with larger volume on the surface of the side wall 213 is low, and therefore, the risk of short circuit of the semiconductor device is low, and the reliability of the semiconductor structure is improved.

It should be understood that, in this embodiment, by using the pre-cleaning process, not only the sacrificial film 240 on the surface of the sidewall 213 but also the sacrificial film 240 on the inner wall surface of the source/drain opening 230 are removed.

Since the sacrificial film 240 on the inner wall surface of the source-drain opening 230 is removed, the performance of the source-drain structure formed subsequently is prevented from being affected by the sacrificial film 240 formed on the inner wall surface of the source-drain opening 230.

In this embodiment, the pre-cleaning process is a dry cleaning process, and the reaction gas used in the dry cleaning process includes hydrogen chloride gas (HCL).

The chemical reaction of the hydrogen chloride gas and the silicon is stronger and the controllability is better. On one hand, because the material of the sacrificial film 240 includes silicon germanium and the concentration of germanium in the material of the sacrificial film 240 is within the preset range, and on the other hand, because the dry cleaning process that the reaction gas includes hydrogen chloride gas is adopted, a strong and well-controllable chemical reaction between the reaction gas and the sacrificial film 240 can be realized, and thus, the effects of removing the sacrificial film 240 and peeling the defect seeds 220 wrapped by the sacrificial film 240 are good.

In this embodiment, the parameters of the pre-cleaning process further include: the flow range of the hydrogen chloride gas is 100 standard milliliters/minute to 200 standard milliliters/minute.

By setting the flow range of the hydrogen chloride gas in the precleaning process to be 100-200 standard ml/min, on one hand, the controllability of the precleaning process is further improved, so that the hydrogen chloride gas and the sacrificial film 240 can better react to strip the defect seeds 220, and on the other hand, damage to the exposed substrate 200 can be reduced while the sacrificial film 240 is etched and the defect seeds 220 are stripped.

In this embodiment, the parameters of the pre-cleaning process further include: the pressure range is 5 to 20 torr; the temperature range is 600 ℃ to 700 ℃.

The pressure range is close to the growth pressure of the sacrificial film 240, thereby reducing repeated changes in the pressure in the reaction chamber. The temperature range is used to match the flow range of the hydrogen chloride gas to achieve a suitable etching rate for the sacrificial film 240.

Next, referring to fig. 9 to 10, fig. 9 is a view in the same direction as fig. 8, and fig. 10 is a distribution diagram of a defect structure on a semiconductor structure according to an embodiment of the present invention, and after the pre-cleaning process, source and drain structures 250 are formed in the substrate on both sides of the gate structure 210.

In the present embodiment, the top surface of the source/drain structure 250 is flush with the top surface of the fin 202.

In other embodiments, the top surface of the source drain structure is higher than the top surface of the fin portion.

It should be noted that, for ease of understanding and observation, fig. 10 schematically shows a distribution of defect structures 251 formed on a semiconductor structure (wafer) due to the material of source-drain structures 250 grown on the surface of defect seeds 220. Specifically, the defect structures 251 on the surface of the gate structure 210 can be effectively reduced by the sacrificial film 240 (shown in fig. 7) and the precleaning process (shown in fig. 8) formed in the present embodiment.

Specifically, a source-drain structure 250 is formed in the source-drain opening 230 (as shown in fig. 8), and the source-drain structure 250 is located in the fin portion 202 on both sides of the gate structure 210.

In the present embodiment, the process of forming the source and drain structures 250 includes a selective epitaxial growth process.

In the present embodiment, the material of the source/drain structure 250 includes silicon phosphide.

In this embodiment, the source-drain structure 250 includes: a buffer layer (not shown) located on the inner wall surface of the source/drain opening 230, a bulk layer (not shown) located on the surface of the buffer layer, and a cap layer (not shown) located on the surface of the bulk layer.

In this embodiment, the method for forming a semiconductor structure further includes: after forming the source-drain structure 250, forming a dielectric layer (not shown) on the surfaces of the substrate 200, the source-drain structure 250 and the gate structure 210, wherein the dielectric layer exposes the top surface of the gate structure 210; after the dielectric layer is formed, at least the gate mask structure 214 and the gate electrode 212 are removed, and a gate opening (not shown) is formed in the dielectric layer; after the gate opening is formed, a metal gate (not shown) is formed within the gate opening.

In other embodiments, the source and drain openings are formed after the pre-cleaning process, so that the influence of the processes of forming the sacrificial film and removing the sacrificial film on the appearance of the source and drain openings is further avoided, and the effects of removing defective seeds and improving the appearance of the source and drain structure are considered.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (10)

1. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises a base and a plurality of fin parts which are positioned on the base and are separated from each other, an isolation layer is arranged on the surface of the base, the isolation layer is also positioned between the adjacent fin parts, and the surface of the isolation layer is lower than the top surfaces of the fin parts;

forming a plurality of mutually-separated gate structures on the isolation layer, wherein the gate structures cross the fin parts and comprise gate oxide layers, gate electrodes positioned on the surfaces of the gate oxide layers and side walls positioned on the side walls of the gate oxide layers and the gate electrodes;

forming source and drain openings in the fin parts on two sides of the gate structure;

attaching defect seeds to the surface of the side wall, and forming a sacrificial film on the surface of the defect seeds by adopting a selective epitaxial growth process after the source drain opening is formed, wherein the sacrificial film is also positioned between the surface of the defect seeds and the surface of the side wall;

removing the sacrificial film by adopting a pre-cleaning process to strip the defect seeds;

and forming a source drain structure in the source drain opening after the pre-cleaning process, wherein the top surface of the source drain structure is higher than or flush with the top surface of the fin portion.

2. The method of claim 1, wherein a growth rate of the material of the sacrificial film on the surface of the sidewall is less than a growth rate of the material of the sacrificial film on the surface of the defect seed during the formation of the sacrificial film by a selective epitaxial growth process.

3. The method according to claim 1, wherein a material of the sacrificial film comprises silicon germanium having a germanium concentration within a predetermined range, the pre-cleaning process is a dry cleaning process, and a reaction gas used in the dry cleaning process comprises hydrogen chloride gas.

4. The method of claim 3, wherein a concentration of germanium in the material of the sacrificial film is in a range from 10% to 20%.

5. The method of forming a semiconductor structure of claim 3, wherein the parameters of the selective epitaxial growth process to form the sacrificial film comprise: the pressure range is 10 torr to 30 torr.

6. The method of forming a semiconductor structure of claim 5, wherein the parameters of the selective epitaxial growth process to form the sacrificial film further comprise: the gas comprises GeH ₄ And, geH ₄ The flow rate of (c) is in the range of 15 to 25 standard ml/min.

7. The method of forming a semiconductor structure according to claim 3, wherein the parameters of the preclean process further comprise: the flow range of the hydrogen chloride gas is 100 standard milliliters/minute to 200 standard milliliters/minute.

8. The method of forming a semiconductor structure of claim 7, wherein the parameters of the preclean process further comprise: the pressure range is 5 to 20 torr; the temperature range is 600 ℃ to 700 ℃.

9. The method for forming the semiconductor structure according to claim 1, wherein the sacrificial film is further located on at least a part of an inner wall surface of the source-drain opening, and the sacrificial film on the inner wall surface of the source-drain opening is removed in a process of removing the sacrificial film by using a precleaning process.

10. The method for forming a semiconductor structure according to claim 1, wherein the material of the source and drain structures comprises silicon phosphide.

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