CN115687188A - Display interface signal output conversion circuit and related method - Google Patents

Abstract

The invention discloses a DP signal output conversion circuit, which comprises a decoder, a clock generation circuit, a DP signal generation circuit and a symbol count value comparison circuit. The decoder is used for decoding a USB signal to generate a plurality of packets, the clock generating circuit is used for generating a clock signal, the DP signal generating circuit is used for generating a DP signal according to the packets and outputting the DP signal according to the clock signal CLK, and the symbol count value comparison circuit is used for obtaining a first count value according to the symbol number corresponding to the packets in real time, counting by using the clock signal to obtain a second count value, and comparing the first count value with the second count value to generate a control signal to the clock generating circuit so as to adjust the frequency of the clock signal.

Description

Display interface signal output conversion circuit and related method

Technical Field

The present invention relates to a display interface (DisplayPort) signal output conversion circuit applied to a Universal Serial Bus (USB) device.

Background

In the specification of USB version 4 (hereinafter USB 4), which provides a tunnel (tunnel) to transfer data of other protocols, for example, USB4 may support a tunneling protocol of a tunnel (DP tunneling) based on a DP signal. For example, when one or more electronic devices transmit DP signals using USB4 compliant signals, assuming that the current DP signal operates at 2.7GHz, the symbol rate (link symbol rate) of a DP signal input converter (DP in adapter) will also be 2.7GHz, and the DP signal input converter will transmit each symbol (symbol) seamlessly through the associated circuitry and interface of USB4 under some degree of compression; then, after receiving the transport layer signal of USB4, a DP signal output converter circuit (DP out adapter) decompresses the transport layer signal to generate image data, and transmits the image data to a back-end display using a clock signal generated by a built-in clock generation circuit, wherein the frequency of the clock signal must be the same as the symbol transmission rate of the DP signal input converter circuit, for example, 2.7GHz. In short, the frequency of the DP signal received by the DP signal input conversion circuit must be the same as the frequency of the output DP signal of the DP signal output conversion circuit to ensure the integrity of the data content. However, the internal clock signals used by the DP signal input conversion circuit and the DP signal output conversion circuit may have a deviation in frequency, which may cause data loss for a long time.

In order to solve the above problem, the DP signal input converting circuit transmits a clock synchronization packet (clock synchronization packet) to the DP signal output converting circuit at a specific time to perform frequency correction of a clock signal. However, since the transmission time of the clock synchronization packet is usually about 2 ms, that is, the DP signal output conversion circuit will adjust the frequency of the clock signal once within about 2 ms, and the 2 ms will transmit about 170 ten thousand symbols, the adjustment method may cause the adjustment of the clock signal to be severe due to the large frequency difference, and a large register is required inside the DP signal output conversion circuit to avoid the symbols that may be missed due to the clock signal deviation within the 2 ms period.

Disclosure of Invention

Therefore, one of the objectives of the present invention is to provide a DP signal output converting circuit, which can shorten the interval of frequency adjustment of the clock signal without affecting the transmission of other signals, so as to solve the problems in the prior art.

In one embodiment of the present invention, a DP signal output converting circuit is disclosed, which comprises a decoder, a clock generating circuit, a DP signal generating circuit and a symbol count value comparing circuit. The decoder is used for decoding a USB signal to generate a plurality of packets, the clock generating circuit is used for generating a clock signal, the DP signal generating circuit is used for generating a DP signal according to the packets and outputting the DP signal according to the clock signal CLK, and the symbol count value comparison circuit is used for obtaining a first count value according to the symbol number corresponding to the packets in real time, counting by using the clock signal to obtain a second count value and comparing the first count value with the second count value to generate a control signal to the clock generating circuit so as to adjust the frequency of the clock signal.

In another embodiment of the present invention, a DP signal output conversion method is disclosed, which comprises the following steps: decoding a USB signal to generate a plurality of packets; using a clock generating circuit to generate a clock signal; using a DP signal generating circuit to generate a DP signal according to the plurality of packets and output the DP signal according to the clock signal CLK; obtaining a first count value in real time according to the symbol numbers corresponding to the packets; counting by using the clock signal to obtain a second count value; and comparing the first count value with the second count value to generate a control signal to the clock generating circuit for adjusting the frequency of the clock signal.

Drawings

FIG. 1 is a diagram of a USB4 system according to an embodiment of the present invention.

Fig. 2 is a schematic diagram of a DP signal output conversion circuit according to an embodiment of the present invention.

Fig. 3 is a diagram illustrating a symbol count value comparator according to an embodiment of the invention.

Fig. 4 is a diagram illustrating the operation of an SST symbol decoder and accumulator according to an embodiment of the invention.

Fig. 5 is a diagram illustrating operation of an MST symbol decoder and accumulator according to an embodiment of the invention.

Description of the symbols

110: DP signal source device

120: USB4 host

122: DP signal input conversion circuit

130: USB4 concentrator

132: DP signal output conversion circuit

140: DP signal receiving device

210: decoder

220: temporary storage device

230: DP signal generating circuit

240: synchronous packet processing circuit

250: symbol count value comparator

260: clock generation circuit

310: demultiplexer

320: SST symbol decoder

330: MST symbol decoder

340: multiplexer

350,360: accumulator

370: adjusting circuit

AN1, AN2: count value

CLK: clock signal

SEL: selection signal

Vc1, vc2: control signal

Detailed Description

FIG. 1 is a diagram of a USB4 system according to an embodiment of the present invention. As shown in fig. 1, the USB4 system includes a DP signal source device 110, a USB4 host 120, a USB4 hub 130, and a DP signal sink device 140, wherein the USB4 host 120 includes a DP signal input converting circuit 122, and the USB4 hub 130 includes a DP signal output converting circuit 132. In this embodiment, the DP signal source device 110 may be any device or apparatus capable of generating image data according to the DP video interface standard, and the DP signal input conversion circuit 122 in the USB4 host 120 is used for converting the DP signal into a USB4 signal and transmitting the USB4 signal to the USB4 hub 130 through the USB4 interface; then, the DP signal output conversion circuit 132 in the USB4 hub 130 converts the USB4 signal from the USB4 host 120 into a DP signal, and transmits the DP signal to the DP signal receiving device 140 (e.g., a display) for playing.

As described in the prior art, since it is not desirable to miss any symbol during the transmission of the DP signal, the clock signals used by the DP signal input converting circuit 122 and the DP signal output converting circuit 132 have the same frequency, for example, 2.7GHz, however, since the clock signals in different devices are inevitably biased, the DP signal output converting circuit 132 needs to continuously adjust the frequency of its own clock signal, so as to avoid the problem of missing the symbol of the DP signal due to the difference in the frequency of the clock signals of the DP signal input converting circuit 122 and the DP signal output converting circuit 132. The present embodiment proposes a design of the DP signal output switching circuit 132, which can quickly determine the frequency difference between the time signals of the DP signal input switching circuit 122 and the DP signal output switching circuit 132, so as to quickly adjust the clock signal of the DP signal output switching circuit 132.

Specifically, please refer to fig. 2, which is a schematic diagram of the DP signal output converting circuit 132 according to an embodiment of the present invention. As shown in fig. 2, the DP signal output converting circuit 132 comprises a decoder 210, a register 220, a DP signal generating circuit 230, a synchronization packet processing circuit 240, a symbol count value comparator 250, and a clock generating circuit 260. In the operation of the DP signal output converting circuit 132, the decoder 210 may be a decoder conforming to the USB4 specification for "hot 9" and is used for decoding the USB4 Transport layer signal to generate a plurality of Single Stream Transport (SST) packets or a plurality of Multi-Stream Transport (MST) packets, and the plurality of SST packets or the plurality of MST packets are stored in the register 220. At this time, the synchronization packet processing circuit 240 receives the clock synchronization packet sent from the USB4 host 120 about every 2 ms, and generates a control signal Vc1 according to the content of the clock synchronization packet to instruct the clock generation circuit 260 to increase or decrease the frequency of the clock signal CLK. For example, the DP signal input conversion circuit 122 of the USB4 host 120 has a counter therein, wherein the counter uses the internal clock signal to count continuously, and generates a count value every 2^21 nanoseconds (nano-second), and after performing some Infinite Impulse Response (IIR) filtering operations on the count value, transmits the filtered count value to the USB hub 130 through the clock synchronization packet. Meanwhile, the synchronous packet processing circuit 240 in the DP signal output conversion circuit 132 also includes a counter for counting continuously by using the clock signal CLK and generating a count value every 2^21 nanoseconds. Therefore, the synchronization packet processing circuit 240 can determine to decrease or increase the frequency of the clock signal CLK according to the count value generated by itself and the count value from the clock synchronization packet. For example, if the count value generated by the synchronization packet processing circuit 240 itself is higher than the count value in the clock synchronization packet, the control signal Vc1 is generated to instruct the clock generation circuit 260 to decrease the frequency of the clock signal CLK; if the count value generated by the synchronization packet processing circuit 240 itself is lower than the count value in the clock synchronization packet, the control signal Vc1 is generated to instruct the clock generation circuit 260 to increase the frequency of the clock signal CLK.

On the other hand, since the synchronous packet processing circuit 240 generates the control signal Vc1 every 2^21 nanoseconds to instruct the clock generation circuit 260 to adjust the frequency of the clock signal CLK, the difference between the frequencies of the internal clock signals of the DP signal input conversion circuit 122 and the DP signal output conversion circuit 132 cannot be reflected quickly, and therefore, the present embodiment provides the symbol count value comparator 250 which can generate the control signal Vc2 in real time to instruct the clock generation circuit 260 to adjust the frequency of the clock signal CLK when receiving each packet. Specifically, referring to the schematic diagram of the symbol count value comparator 250 shown in fig. 3, it comprises a demultiplexer 310, an SST symbol decoder 320, an MST symbol decoder 330, a multiplexer 340, two accumulators 350,360 and an adjusting circuit 370. In the operation of the symbol count value comparator 250, first, the demultiplexer 310 determines to transmit the packet decoded by the decoder 210 to the SST symbol decoder 320 or the MST symbol decoder 330 according to a selection signal SEL, wherein the selection signal SEL is used to indicate whether the packet decoded by the decoder 210 is the SST packet or the MST packet, if the SST packet is the SST symbol decoder 320, and if the MST packet is the MST symbol decoder 330.

In one example, if the packet is SST packet, the SST symbol decoder 320 decodes the SST packet to calculate the number of symbols of the DP signal actually corresponding to the currently received packet, and transmits the calculated number of symbols to the accumulator 350 through the multiplexer 340. In detail, referring to fig. 4, in an example, the DP signal generated by the DP signal source device 110 includes, in order, blank Start (BS), padding data of 5 symbols, second data Start (SS), second data of 10 symbols (second data), second data End (SE), padding data of 8 symbols, blank End (BE), video data of 20 symbols, padding Start (FS), padding data of 8 symbols, padding End (FE), video data of 20 symbols, …, and the like, and the padding data may BE regarded as redundant data or invalid since the padding data corresponds to the blank area of the video rather than display data in the DP signal, the DP signal input conversion circuit 122 of the USB4 host 120 removes the padding data, but the padding data corresponds to the number of each symbol recorded in the DP signal. For example, in FIG. 4, the USB4 signal generates a second data packet based on the DP signal, a video data packet …, etc., wherein the second data packet has a header (header) with padding data having 5 symbols before the second data, and the header of the video data packet has padding data having 8 symbols before the video data. Therefore, the SST symbol decoder 320 can determine how many symbols of the actual DP signal are for the accumulator 350 to accumulate when each packet is received. As shown in fig. 4, SST symbol decoder 320 decodes the second data packet to know that the second data corresponds to 10 symbols and there is padding data of 5 symbols before the second data, so accumulator 350 can add "15" to the original count value (assuming "0"); then, the SST symbol decoder 320 decodes the video data packet to know that the video data corresponds to 20 symbols and the video data has 8 symbols of padding data before the video data, so the accumulator 350 can add "28" to the current count value to become "43"; then, the SST symbol decoder 320 decodes the next video data packet to know that the video data corresponds to 20 symbols and has 8 symbols of padding data before the video data, so the accumulator 350 can add "28" to the current count value to become "71", and so on.

It should be noted that the above calculation is only used as an example, and not a limitation of the present invention, that is, as long as the SST symbol decoder 320 decodes each packet to obtain the symbol number of the DP signal actually corresponding to each packet, it may have different calculation and determination mechanisms. For example, SST symbol decoder 320 may determine the symbol number of the DP signal actually corresponding to each packet according to the number of start of blank fields (BS) or the number of other fields received in the SST packet. In another embodiment, the counting value of the accumulator 350 is only illustrated as an example, and is not limited by the present invention, that is, as long as the accumulator 350 calculates the counting value according to a decoding result of the SST symbol decoder 320, the decoding result may be a value obtained by decoding each packet to obtain the symbol number of the DP signal actually corresponding to each packet, or a value corresponding to the symbol number of the DP signal actually corresponding to each packet (for example, a value proportional to the symbol number of the DP signal actually corresponding to each packet, or a value calculated according to the symbol number of the DP signal actually corresponding to each packet). For example, the incremented count value of the accumulator 350 may be proportional to the number of symbols of the DP signal actually corresponding to each packet.

On the other hand, in the case of an MST packet, the MST symbol decoder 330 decodes the MST packet to calculate the number of symbols of the DP signal actually corresponding to the currently received packet, and transmits the calculated number of symbols to the accumulator 350 through the multiplexer 340. In detail, referring to fig. 5, in the MST packet transmission mechanism, 64 time slots (time slots) are planned to transmit different streams in a time division multiplexing manner. Since a packet is transmitted in time slot "0", the MST symbol decoder 330 can inform the accumulator 350 to add "64" to the current count value, as shown in fig. 5, as long as it determines that the received packet corresponds to time slot "0".

It should be noted that fig. 5 is only an example, and based on similar concepts, in other embodiments, the symbol count value comparison circuit 250 decodes each packet to determine whether the packet corresponds to a specific time slot, and adds a predetermined value to the first count value if the packet corresponds to the specific time slot, wherein the specific time slot is not limited to the time slot "0" shown in fig. 5, and the predetermined value is not limited to "64" in the embodiment of fig. 5, for example, the predetermined value may be the number of used time slot numbers, or any value that can indicate the number of received symbols, or a value proportional to the number of received symbols.

Referring to fig. 4 and 5, the accumulator 360 starts counting at the same time as the accumulator 350, but the accumulator 360 is simply counted by the clock signal CLK generated by the clock generation circuit 260, that is, the count value generated by the accumulator 360 can be regarded as how many cycles of the clock signal CLK have passed after the start of counting.

Then, the adjusting circuit 370 receives the count value AN1 from the accumulator 350 and the count value AN2 from the accumulator 360, compares the count value AN1 with the count value AN2 to determine whether to increase or decrease the frequency of the clock signal CLK, and accordingly generates the control signal Vc2. For example, considering that the count value AN1 is updated after decoding the packet, rather than continuously updating according to the clock signal CLK as the count value AN2 is updated, the adjusting circuit 370 may determine whether the difference between the count value AN1 and the count value AN2 is greater than a threshold value to determine whether to increase or decrease the frequency of the clock signal CLK. Specifically, if the count value AN1 is greater than the count value AN2 plus a threshold value TH, i.e., AN1> (AN 2+ TH), the control signal Vc2 is generated to increase the frequency of the clock signal CLK; if the count value AN2 is greater than the count value AN1 plus the threshold value TH, i.e., AN2> (AN 1+ TH), the control signal Vc2 is generated to decrease the frequency of the clock signal CLK. In addition, if the difference between the count value AN1 and the count value AN2 is not greater than the threshold value, i.e., (AN 1-AN 2) < TH, the control signal Vc2 is not generated or the control signal Vc2 is generated such that the clock signal CLK maintains the current frequency.

It should be noted that, in the above embodiment, the counting value AN1 is obtained according to the symbol number of the DP signal actually corresponding to the currently received packet output by the SST symbol decoder 320 or the MST symbol decoder 330, and the counting value AN2 is how many cycles of the clock signal CLK have passed after the counting is started, however, the invention is not limited thereto. In other embodiments, as long as the count value AN1 and the count value AN2 are obtained according to the same calculation method, for example, the count value AN1 is obtained by calculating the number of symbols of the DP signal actually corresponding to the currently received packet using a calculation method (e.g., proportional calculation), and the count value AN2 is also obtained by calculating how many cycles of the clock signal CLK have passed after the start of counting using the same calculation method, and these design changes should fall within the scope of the present invention.

Finally, referring back to fig. 2, the DP signal generating circuit 230 reads the SST packet or the MST packet stored in the register 220, reconstructs the DP signal, and transmits the DP signal to the DP signal receiving device 140 according to the clock signal CLK.

It should be noted that the DP signal output converting circuit 132 shown in fig. 2 includes the synchronization packet processing circuit 240 and the symbol count value comparator 250 to generate the control signals Vc1 and Vc2 to control the frequency of the clock signal CLK generated by the clock generating circuit 260, however, in other embodiments of the present invention, the synchronization packet processing circuit 240 may be removed from the DP signal output converting circuit 132, and the clock generating circuit 260 only adjusts the frequency of the clock signal CLK according to the control signal Vc2 generated by the symbol count value comparator 250, and these related changes should fall within the scope of the present invention.

Briefly summarized, in the DP signal output conversion circuit and the related method of the present invention, the content of the packets is analyzed in time to obtain the symbol number of the DP signal corresponding to each packet, and the symbol numbers corresponding to the packets are accumulated to obtain a first count value, an internal clock signal is used to count to obtain a second count value, and the first count value and the second count value are compared to generate a control signal to the clock generation circuit for adjusting the frequency of the clock signal, so that the interval of the frequency adjustment of the clock signal can be shortened to avoid the problem caused by the overlong interval of the frequency adjustment in the prior art.

The above-mentioned embodiments are only preferred embodiments of the present invention, and all equivalent changes and modifications made by the claims of the present invention should be covered by the scope of the present invention.

Claims (10)

1. A display interface signal output conversion circuit comprises:

a decoder for decoding a USB signal to generate a plurality of packets;

a clock generating circuit for generating a clock signal;

a display interface signal generating circuit for generating a display interface signal according to the plurality of packets and outputting the display interface signal according to the clock signal CLK; and

a symbol count value comparison circuit, which is used to obtain a first count value according to the symbol number corresponding to the packets in real time, and use the clock signal to count to obtain a second count value, and compare the first count value and the second count value to generate a control signal to the clock generation circuit for adjusting the frequency of the clock signal.

2. The display interface signal output conversion circuit according to claim 1, wherein the USB4 signal is the USB serial bus signal.

3. The display interface signal output conversion circuit of claim 2, wherein if the plurality of packets are single stream transmission packets, the symbol count value comparison circuit decodes each packet and calculates the first count value according to a decoding result, wherein the decoding result is the number of symbols of the display interface signal actually corresponding to each packet or the value corresponding to the number of symbols of the display interface signal actually corresponding to each packet.

4. The display interface signal output conversion circuit of claim 2, wherein if the plurality of packets are multi-stream transmission packets, the symbol count value comparison circuit decodes each packet to determine whether the packet corresponds to a specific time slot; and if the packet corresponds to the specific time slot, the symbol count value comparison circuit adds a predetermined value to the first count value.

5. The display interface signal output conversion circuit according to claim 4, wherein the specific time slot is time slot "0", and the predetermined value is the number of time slot numbers used.

6. The display interface signal output conversion circuit of claim 1, wherein the symbol count value comparison circuit comprises:

a single stream transmission symbol decoder, wherein if the plurality of packets are single stream transmission packets, the single stream transmission symbol decoder decodes each packet to obtain the symbol number of the display interface signal actually corresponding to each packet;

a multiple stream transmission symbol decoder, wherein if the plurality of packets are multiple stream transmission packets, the multiple stream transmission symbol decoder decodes each packet to determine whether the packet corresponds to a specific time slot; and if the packet corresponds to the specific time slot, the MSG decoder generates a predetermined value; and

a first accumulator for continuously receiving the symbol number of the display interface signal actually corresponding to each packet from the single stream transmission symbol decoder or the predetermined value generated by the multi-stream transmission symbol decoder for generating the first count value.

7. The display interface signal output conversion circuit of claim 6, wherein the symbol count value comparison circuit further comprises:

a second accumulator for continuously using the clock signal to count for generating the second count value.

8. The display interface signal output conversion circuit of claim 7, wherein the symbol count value comparison circuit further comprises:

and the adjusting circuit is used for judging whether the difference between the first counting value and the second counting value is larger than a critical value or not so as to generate the control signal to the clock generating circuit for adjusting the frequency of the clock signal.

9. The display interface signal output conversion circuit of claim 8, wherein if the first count value is greater than the second count value plus the threshold value, the adjustment circuit generates the control signal to the clock generation circuit to increase the frequency of the clock signal; and if the second count value is larger than the first count value plus the critical value, the adjusting circuit generates the control signal to the clock generating circuit so as to reduce the frequency of the clock signal.

10. A display interface signal output conversion method comprises the following steps:

decoding a universal serial bus signal to generate a plurality of packets;

using a clock generating circuit to generate a clock signal;

using a display interface signal generating circuit to generate a display interface signal according to the plurality of packets and output the display interface signal according to the clock signal CLK;

obtaining a first count value in real time according to the symbol numbers corresponding to the packets;

counting by using the clock signal to obtain a second count value; and

comparing the first count value with the second count value to generate a control signal to the clock generating circuit for adjusting the frequency of the clock signal.

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