CN115667954A

CN115667954A - Detection circuit for keeping time allowance

Info

Publication number: CN115667954A
Application number: CN202080101665.5A
Authority: CN
Inventors: 王卓; 董紫剑; 李梅
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-08-28
Filing date: 2020-08-28
Publication date: 2023-01-31
Also published as: WO2022041154A1

Abstract

The embodiment of the application discloses a detection circuit for keeping time allowance, relates to the technical field of circuits, and solves the problem that in the prior art, the detection precision of the time allowance kept in a chip is poor. The specific scheme is as follows: the detection circuit includes: a generator and a decision circuit; the generator comprises at least one group of test circuits, each group of test circuits comprises N first registers, N second registers and N data delay units, time delays of the N data delay units are sequentially increased, and the time delay difference between two adjacent data delay units is smaller than or equal to a preset value; the data output ends of the N first registers are respectively connected with the input ends of the N data delay units, the output ends of the N data delay units are respectively connected with the data input ends of the N second registers, and the data output ends of the N second registers are connected with the judgment circuit.

Description

Detection circuit for keeping time allowance

Technical Field

The embodiment of the application relates to the technical field of circuits, in particular to a detection circuit for keeping a time margin.

Background

Timing design and analysis are one of the important links of chip design, and in the design of a large-scale System On Chip (SOC), a Static Timing Analysis (STA) method is usually adopted to ensure the timeliness of a design iteration period. STA is an analysis method of coverage boundary conditions, and can simulate performance changes of different tubes inside a chip due to process deviation, voltage drop and temperature change by pessimizing the coverage boundary conditions. However, if the boundary conditions are set too strictly, the design difficulty will be greatly increased, and at the same time, too many resources in Die are occupied, so that the product competitiveness is reduced. If the boundary condition setting is too relaxed, quality problems can be caused, and a series of index problems can be caused to the chip, and the chip can not work.

Fig. 1 shows an existing Intellectual Property (IP) design (patent number: US7930663B 2), as shown in fig. 1, a data output terminal Q0 of a register (flip flop, FF 0) is connected to a data input terminal D of a register FF1, a data output terminal Q1 of the register FF1 is connected to a data input terminal D of a register FF2, a delay line delay0 (delay line) is formed between a clock terminal of the register FF0 and a clock terminal Clk1 of the register FF1 by using standard cells (stdcell), a delay line delay0 is formed between the clock terminal Clk1 of the register FF1 and the clock terminal Clk2 of the register FF2 by using stdcell, an initial state of a circuit is configured to be in a success state, different delay values are selected by adjusting signal configurations of delay selection modules delay 1 and delay se2 until a hold failure (hold fail) state of the circuit occurs, a peripheral circuit and the hold state of the circuit are successfully configured to be in a fail state, and a detection result is read by a bus to provide a next generation of a detection chip according to a detection time for a next generation of the hold failure.

In the IP design, the delay line (delay line) composed of standard cells stdcell has poor accuracy of detecting the hold time (hold time). However, in processes of 28nm and below, the number of timing violations (timing violations) caused by 1ps of uncertainty may be hundreds of thousands or even millions, depending on the size of the SOC. Therefore, if the lack of precision is applied to a practical project, the method is likely to face a great risk of timing violation, and therefore, the scheme has no obvious practical engineering significance.

Disclosure of Invention

The embodiment of the application provides a detection circuit for maintaining a time margin, which can improve the detection precision of the time margin.

In order to achieve the above purpose, the embodiment of the present application adopts the following technical solutions:

in a first aspect of the embodiments of the present application, there is provided a detection circuit for maintaining a time margin, the detection circuit including: a controller, a generator and a decision circuit; the generator comprises at least one group of test circuits, each group of test circuits comprises N first registers, N second registers and N data delay units, time delay of the N data delay units is sequentially increased, time delay difference between two adjacent data delay units is smaller than or equal to a preset value, and N is an integer larger than 1; the clock ends of the controller and the N first registers and the clock ends of the N second registers are connected to the same clock output end of the controller, the data output ends of the N first registers are respectively connected with the input ends of the N data delay units, the output ends of the N data delay units are respectively connected with the data input ends of the N second registers, and the data output ends of the N second registers are connected with the decision circuit; the decision circuit is used for detecting the output states of the N second registers and transmitting the output states of the N second registers to the controller. Based on the scheme, N data delay units are arranged between N first registers and N second registers, and the time delay of the N data delay units is sequentially increased, so that the time delay of data paths of N groups of registers is different. The output state of the second register is a hold success state because the time delay of the data path from the first register to the second register is greater than the time delay of the clock path; and when the time delay of a data path from the first register to the second register is less than the time delay of a clock path, the output state of the second register is a holding failure state. Therefore, by arranging N data delay units with sequentially increasing time delay between the N first registers and the N second registers, the time delay of data paths from the N first registers to the N second registers is different, the output state of one part of the N second registers is a holding failure state, the output state of the other part of the N registers is a holding success state, and a holding time margin can be detected from holding failure to holding success according to the second registers. It will be appreciated that a first register and a second register coupled to the first register via a data delay unit may be referred to as a set of registers.

With reference to the first aspect, in a possible implementation manner, the N data delay units respectively include N S-shaped metal windings, and lengths of the N S-shaped metal windings are sequentially increased. Based on the scheme, the time delay of the data path of the N groups of registers is sequentially increased through sequentially increasing the lengths of the N S-shaped metal windings, the detection precision of the retention time allowance can be controlled through designing the length difference between two adjacent S-shaped metal windings, and the precision of the detected retention time allowance is higher.

With reference to the first aspect and the foregoing possible implementation manners, in another possible implementation manner, the length difference between two adjacent S-shaped metal windings in the N S-shaped metal windings is the same. Based on the scheme, the detection precision of the retention time allowance can be controlled by setting the length difference between two adjacent S-shaped metal windings, so that the precision of the detected retention time allowance is higher. It can be understood that due to the non-linear characteristic of the metal, when the lengths of the N S-shaped metal windings are sequentially increased and two adjacent S-shaped windings are increased by the same length, the time delays of the N data delay units are sequentially increased, but the time delay differences (step accuracy) of two adjacent data delay units are not completely the same.

With reference to the first aspect and the foregoing possible implementation manners, in another possible implementation manner, the S-shaped metal winding includes a first turning portion, a second turning portion, and one or more spliceable portions, and the number of spliceable portions included in different S-shaped metal windings is different. Based on the scheme, the S-shaped metal winding is designed into the splicing modules, so that S-shaped metal windings with different lengths can be realized by increasing the number of splicing parts, the method has good controllability, splicing can be freely realized according to different design scales and different delay values, secondary inspection is facilitated, and the method has good practical engineering significance.

With reference to the first aspect and the possible implementation manners described above, in another possible implementation manner, the first turning portion includes an input end of the S-shaped metal winding and an output end of the S-shaped metal winding; alternatively, the second turn portion includes an input terminal of the S-shaped metal winding and an output terminal of the S-shaped metal winding. Based on the scheme, the input end of the S-shaped metal winding and the output end of the S-shaped metal winding can be arranged on the same side.

With reference to the first aspect and the foregoing possible implementation manners, in another possible implementation manner, the first turning part includes an input end of the S-shaped metal winding, and the second turning part includes an output end of the S-shaped metal winding; alternatively, the first turn portion includes an output terminal of the S-shaped metal winding, and the second turn portion includes an input terminal of the S-shaped metal winding. Based on this scheme, S type metal wire-wound input and S type metal wire-wound output can not the unilateral setting.

With reference to the first aspect and the foregoing possible implementation manners, in another possible implementation manner, the detection circuit further includes a clock selector and a clock delay circuit, the controller is connected to the input terminal of the clock selector, the data selection terminal of the clock selector, and the clock terminals of the N first registers, the output terminal of the clock selector is connected to the input terminal of the clock delay circuit, and the output terminal of the clock delay circuit is connected to the clock terminals of the N second registers. Based on the scheme, the clock selector is used for selecting the clock selection module to carry out wide-range adjustment, so that the output states of the N second registers have a hold failure (hold fail) state and a hold pass (hold pass) state.

With reference to the first aspect and the foregoing possible implementation manners, in another possible implementation manner, the clock delay circuit includes M clock delay units, and the M clock delay units respectively have M different time delays. Based on the scheme, the time delay on the clock path can be adjusted through the clock delay units with M different time delays.

With reference to the first aspect and the foregoing possible implementation manners, in another possible implementation manner, the controller is specifically configured to time-divisionally control the clock selector to sequentially select each clock delay unit of the M clock delay units. Based on the scheme, the controller selects different clock delay units in a time-sharing manner, and can perform wide-range adjustment, so that the output states of the N second registers have a hold failure (hold fail) state and a hold pass (hold pass) state.

With reference to the first aspect and the foregoing possible implementation manners, in another possible implementation manner, the controller is specifically configured to: controlling a clock selector to select a first clock delay unit of the M clock delay units; if the output states of the N second registers are successfully kept, the controller controls the clock selector to select a second clock delay unit in the M clock delay units, and the time delay of the second clock delay unit is greater than that of the first clock delay unit; and if the output states of the N second registers are all failed to be kept, the controller controls the clock selector to select a third clock delay unit in the M clock delay units, and the time delay of the third clock delay unit is smaller than that of the first clock delay unit. Based on the scheme, the controller controls the clock selector to select the clock delay unit in a closed loop mode, so that the output states of the N second registers have a hold failure (hold fail) state and a hold pass (hold pass) state.

With reference to the first aspect and the foregoing possible implementation manners, in another possible implementation manner, the detection circuit further includes an interface circuit, the controller is connected to the interface circuit, and the controller is further configured to transmit the output states of the N second registers to the interface circuit. Based on the scheme, the output states of the N second registers can be transmitted to the external equipment through the interface circuit, and whether the boundary condition of the design stage is too tight or too loose can be determined based on the output states of the N second registers and the simulation result.

With reference to the first aspect and the foregoing possible implementation manners, in another possible implementation manner, process voltage temperatures PVT of the N first registers and the N second registers in the same group of test circuits are the same, where PVT is a standard voltage threshold SVT, a low voltage threshold LVT, or an ultra-low voltage threshold ULVT. Based on the scheme, the detection circuit can be provided with test circuits of different PVTs, and can adapt to the processes of different chips.

In a second aspect of the embodiments of the present application, a device is provided, where the device includes a circuit board and a detection circuit for maintaining a time margin as described in the first aspect or any one of the possible implementation manners of the first aspect.

Drawings

Fig. 1 is an IP design schematic diagram of detecting a time margin according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a synchronous timing circuit according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a detection circuit for maintaining a time margin according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of a data delay unit according to an embodiment of the present application;

fig. 5 is a schematic diagram of a delay and a step precision of a data delay unit according to an embodiment of the present application;

fig. 6 is a schematic diagram of a simulation result and a test result provided in an embodiment of the present application;

FIG. 7 is a schematic diagram of another simulation result and test result provided in the embodiments of the present application;

fig. 8 is a schematic diagram illustrating a division of an S-shaped metal winding according to an embodiment of the present disclosure;

fig. 9 is a schematic wiring diagram of an S-shaped metal winding according to an embodiment of the present disclosure;

FIG. 10 is a schematic diagram of another S-shaped metal winding according to an embodiment of the present application;

FIG. 11 is a schematic diagram of another detection circuit for maintaining a time margin according to an embodiment of the present disclosure;

FIG. 12 is a schematic diagram of another detection circuit for maintaining a time margin according to an embodiment of the present disclosure;

FIG. 13 is a schematic diagram of another detection circuit for maintaining a time margin according to an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. In the present application, "at least one group" means one or more groups, and "a plurality of groups means two or more groups. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone, wherein A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a and b, a and c, b and c, or a and b and c, wherein a, b and c can be single or multiple. In addition, for the convenience of clearly describing the technical solutions of the embodiments of the present application, in the embodiments of the present application, the words "first", "second", and the like are used to distinguish the same items or similar items with basically the same functions and actions, and those skilled in the art can understand that the words "first", "second", and the like do not limit the quantity and execution order. For example, the "first" in the first register and the "second" in the second register in the embodiment of the present application are only used to distinguish different registers. The descriptions of the first, second, etc. appearing in the embodiments of the present application are only for illustrating and differentiating the objects, and do not represent the order or the particular limitation of the number of the devices in the embodiments of the present application, and do not constitute any limitation to the embodiments of the present application.

It is noted that, in the present application, words such as "exemplary" or "for example" are used to mean exemplary, illustrative, or descriptive. Any embodiment or design described herein as "exemplary" or "such as" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

FIG. 2 shows a synchronous timing circuit, as shown in FIG. 2, the data output terminal Q of the register D1 is connected to the input terminal of the combinational logic (combinational logic), and the output terminal of the combinational logic is connected to the data input terminal D of the register D2. The clock terminal CP of the register D1 and the clock terminal CP of the register D2 are connected to a clock signal CLK. The clock active edge of the clock terminal of the register D1 and the register D2 may be a rising edge or a falling edge. When the clock active edge of the register D1 and the register D2 is a falling edge, the register D1 or the register D2 samples the data input terminal when the clock terminal changes from a high level to a low level, and supplies the sampled value to the data output terminal. And when the clock end is in other conditions, the data output end maintains the original sampling value until the clock end is changed from the high level to the low level for the second time. It will be appreciated that the output of the combinational logic at any time is dependent only on the input at that time, independent of the original state of the circuit, and does not involve the processing of signal transition edges. The output of the sequential logic at any time is not only dependent on the input at that time, but also depends on the original state of the circuit, and when the active edge (rising edge or falling edge) of the clock arrives, the output may change.

To achieve proper synchronization of the circuit shown in fig. 2, the data must be stable for a period of time before a clock active edge (e.g., rising or falling edge) arrives, which is the setup time. The data must also stabilize for a period of time after the arrival of the clock active edge, which is the hold time. I.e. the data input must remain stable until the actual sampling time arrives, and likewise the data input must be maintained for some time after the sampling time. That is, the circuits can be properly synchronized only if the setup time and hold time are met.

It will be appreciated that in performing the timing analysis of the circuit of fig. 2, it can be determined by the delays of the data path (data path) and the clock path (clock path) whether the timing requirements of the setup time (setup time) and hold time (hold time) are met. As shown in fig. 2. The data path refers to a path taken by data from the whole transmission input end to the transmission output end, and the clock path refers to a path taken by a clock to each register. The hold time (hold time) will only meet the timing requirement when the delay of the data path (data path) is greater than the delay of the clock path (clock path). The setup time (setup time) will only meet the timing requirement when the delay of the data path (data path) is less than the delay of the clock path (clock path).

In the chip design process, simulation is usually performed based on a process file (spice model) issued by a manufacturer (foundry) specially responsible for producing and manufacturing chips, and the time delay inside the chip is fixed during simulation. However, during the manufacturing process of the chip, due to process variations, voltage drop and temperature variation, the delay inside the chip may not be a fixed value but a random value. In order to make the difference between the chip design and the manufacturing closer, a Static Timing Analysis (STA) method can be generally adopted to guarantee the timeliness of the design iteration cycle.

For example, on-chip variation (OCV) can be used in STA to simulate the performance variation due to process variation, voltage drop, and temperature variation among different devices inside a chip. In analyzing hold timing violations, the coverage boundary condition may be pessimized by multiplying the delay value on the data path (data path) by a coefficient less than 1 and multiplying the delay value on the clock path (clock path) by a coefficient greater than 1. However, if the boundary conditions are set too strictly, the design difficulty will be greatly increased, and at the same time, too many resources in Die are occupied, so that the competitiveness of the product is reduced. If the boundary condition setting is too relaxed, quality problems can be caused, and a series of index problems can be caused to the chip, and the chip can not work.

In order to release a part of the boundary conditions to improve the product competitiveness of the chip under the condition that the boundary conditions are set too severely, a test circuit can be arranged in the chip to detect the retention time margin of the chip and adjust the design of the next generation chip according to the retention time margin, so that the product competitiveness of the next generation chip can be improved.

Fig. 1 is an IP design for detecting a time margin, as shown in fig. 1, the IP mainly uses stdcell to form delay line, the initial state of the circuit is configured to be hold successful (hold pass), different delay values can be selected by adjusting the signal configuration of delaySel until the circuit has a hold failed (hold fail) state, the peripheral circuit detects the pass and fail states of the circuit to be detected, and then the detection result is read out through a bus to obtain the margin of the hold time, thereby providing a basis for upgrading the next generation chip.

However, in the IP design shown in fig. 1, when the retention time margin is detected by the delay line composed of stdcell, the accuracy of the retention time of stdcell detection is ideally about 7 to 8 ps. However, in the 28nm and below process, the number of timing violations (timing violations) caused by 1ps hold uncertainties may be hundreds of thousands or even millions, depending on the size of the SOC. Therefore, if the loss of the precision of 7-8 ps is applied to a practical project, the method is likely to face a great time sequence violation risk, and therefore, the scheme has no obvious practical engineering significance.

In order to improve the problem of poor detection accuracy of the retention time margin in the chip, the embodiment of the application provides the detection circuit for the retention time margin, the retention time margin detected by the detection circuit has high accuracy, and a basis can be provided for the design of the next generation chip so as to improve the product competitiveness of the next generation chip.

It should be noted that the following embodiments of the present application provide a detection circuit that, when detecting the retention time margin of a chip, the default chip meets the timing requirement of the setup time.

Fig. 3 is a detection circuit for maintaining a time margin according to an embodiment of the present application, and as shown in fig. 3, the detection circuit includes: a controller, a generator and a decision circuit. The generator comprises at least one group of test circuits, each group of test circuits comprises N first registers, N second registers and N data delay units, time delays of the N data delay units are sequentially increased progressively, the time delay difference of two adjacent data delay units is smaller than or equal to a preset value, and N is an integer larger than 1. The clock ends (CP ends of the first registers) of the N first registers and the clock ends (CP ends of the second registers) of the N second registers are connected to the same clock output end of the controller, the data output ends (QN ends of the first registers) of the N first registers are respectively connected with the input ends of the N data delay units, the output ends of the N data delay units are respectively connected with the data input ends (D ends of the second registers) of the N second registers, and the data output ends (Q ends of the second registers) of the N second registers are connected with the decision circuit. The decision circuit is used for detecting the output states of the N second registers and transmitting the output states of the N second registers to the controller.

For example, fig. 3 illustrates an example in which the data output terminal of the first register is the QN terminal. As shown in fig. 3, when the data output terminal of the first register is the QN terminal, the data input terminal of the first register (the D terminal of the first register) is connected to the data output terminal of the first register (the QN terminal of the first register). Optionally, the data output end of the first register may also be a Q end, and when the data output end of the first register is the Q end, the data input end of the first register (the D end of the first register) is connected to the data output end of the first register (the Q end of the first register) through an inverter. It will be appreciated that the data output QN of the first register is the inverse of the data input D of the first register.

For example, in the embodiment of the present application, a specific value of N is not limited, and in practical application, the value of N may be determined by combining a range of clock delay, where the value of N affects a magnitude of delay on a data path, and the value may enable delay on a data path of a part of registers in the N groups of registers to be smaller than delay on a clock path, and delay on a data path of another part of registers to be larger than delay on the clock path. It will be appreciated that a first register and a second register coupled to the first register via a data delay unit may be referred to as a set of registers. In the embodiment of the present application, N is only 94 as an example.

Illustratively, the N data delay units respectively include N S-type metal windings. The data delay units can be made of S-shaped metal winding wires, and the length of the S-shaped metal winding wires of different data delay units in the N data delay units is different. It can be understood that the turning portion of the S-shaped metal winding may be a right-angle turning, an obtuse-angle turning, or a curved turning, which is not limited in the embodiments of the present application. The following embodiments are only illustrated by taking the turning portion of the S-shaped metal winding as a right angle.

For example, as shown in fig. 4, each data delay unit is made of S-shaped metal winding, N data delay units are made of N S-shaped metal windings, and the lengths of the N S-shaped metal windings are sequentially increased, so that the time delays of the N data delay units are sequentially increased.

Illustratively, the delay difference between two adjacent data delay units in the N data delay units is related to the length difference between two adjacent S-shaped metal windings, and the smaller the length difference between two adjacent S-shaped metal windings is, the smaller the delay difference between two adjacent data delay units is, and the higher the stepping precision of the delay time is. The larger the length difference between two adjacent S-shaped metal windings is, the larger the time delay difference between two adjacent data delay units is, and the lower the stepping precision of the delay time is. It can be understood that the time delay difference of two data delay units can be adjusted by designing the length difference between two adjacent S-shaped metal windings to ensure that the detection accuracy of the retention time margin is high.

Optionally, the length difference between two adjacent S-shaped metal windings in the N S-shaped metal windings may be equal, that is, the lengths of the N S-shaped metal windings are sequentially increased, and the increased lengths of the two adjacent S-shaped windings are the same. It should be noted that due to the non-linear characteristic of metal, when the lengths of N S-shaped metal windings are sequentially increased and two adjacent S-shaped windings are increased by the same length, the time delays of N data delay units are sequentially increased, but the time delay differences (step accuracy) of two adjacent data delay units are not completely the same.

For example, as shown in fig. 5, when the lengths of the S-shaped metal windings of the data delay units 0 to 21 are sequentially increased by the same value, the delays of the data delay units 0 to 21 are sequentially increased, but the delay difference between two adjacent data delay units is nonlinear, i.e., the step precision of the delay times of two adjacent data delay units is nonlinear. As can be seen from fig. 5, since the step precision of the delay times of the two adjacent data delay units is about 1.5ps, the precision of the hold time margin detected by the detection circuit is high.

Illustratively, as shown in conjunction with fig. 3 and 5, the delays of the N data delay units connected between the data output terminals of the N first registers and the data input terminals of the N second registers are different, so that the delays on the data paths of the N sets of registers are different. When the time delay of the data delay unit is smaller, if the delay of the data path from the first register to the second register is smaller than the delay of the clock path, the output state of the second register is hold fail (hold fail), that is, the timing requirement of the chip holding time is not satisfied. When the time delays of the data delay units are sequentially increased to be larger delays, if the delays of the data paths from the first register to the second register are larger than the delays of the clock paths, the output state of the second register is hold success (hold pass), that is, the timing requirement of the chip holding time is met.

It can be understood that, because the delay on the data path of the N groups of registers is sequentially incremented, the output states of a part of the N second registers may be a hold fail (hold fail) state, and the output states of another part of the N second registers may be a hold success (hold pass) state. Based on the output states of the N second registers, and combined with a simulation result obtained by adding the OCV during design or simulation, whether the boundary condition of the design is too tight or too loose can be determined.

For example, taking the test result that the output states of the second register 0 to the second register 9 are the hold fail (hold fail) state, and the output states of the second register 10 to the second register 93 are the hold success (hold pass) state as an example, as shown in fig. 6, if the simulation result after OCV is added is that the output states of the second register 0 to the second register 7 are the hold fail (hold fail) state, and the output states of the second register 8 to the second register 93 are the hold success (hold pass) state. Then, it can be determined according to the test result that the reserved time margin in the design stage is insufficient, which results in the existence of hold violation risk in the test result, i.e. the boundary condition of the design stage is too loose, which results in the existence of violation risk in the chip. It is to be understood that fig. 6 only shows the simulation result and the test result of the second register 0 to the second register 11, and since the delay of the data path from the second register 0 to the second register 93 is sequentially increased, if the simulation result or the test result of the second register 11 is hold success (hold pass), the simulation result or the test result of the second register 12 to the second register 93 is also hold success (hold pass), and fig. 6 only shows the simulation result and the test result of the second register 0 to the second register 11 by way of example. Note that Pass in fig. 6 represents hold success (hold Pass), and Fail represents hold failure (hold Fail).

For another example, if the test result is that the output states of the second register 0 to the second register 4 are a hold fail (hold fail) state, and the output states of the second register 5 to the second register 93 are a hold success (hold pass) state, as shown in fig. 7, if the simulation result after adding OCV is that the output states of the second register 0 to the second register 7 are a hold fail (hold fail) state, the output states of the second register 8 to the second register 93 are a hold success (hold pass) state. Then, according to the test result and the simulation result, because the hold failure (hold fail) of the test is between the simulation result without OCV (without OCV) and the simulation result with OCV, it can be determined that the reserved time margin in the design stage is too much (i.e. the boundary condition in the design stage is too strict), and the partial constraint can be properly relaxed according to the test result, and a part of the boundary condition is released, so that the next generation chip has more product competitiveness.

Optionally, as shown in fig. 7, if it is determined that the boundary condition of the design stage is too tight according to the test result, the boundary conditions of two stages may be released when designing the next-generation chip based on the test result and the simulation result, so that the next-generation product has more product competitiveness.

It can be understood that, in the test circuit in the embodiment of the present application, by disposing N S-shaped metal windings between N first registers and N second registers, and sequentially increasing the lengths of the N S-shaped metal windings, the incremental step precision is related to the length difference between two adjacent S-shaped metal windings, so that the detection precision of the retention time margin can be controlled by designing the length difference between two adjacent S-shaped metal windings, so that the precision of the detected retention time margin is higher, and therefore, a powerful basis can be provided for the design of the next-generation chip based on the detection result, so that the product competitiveness of the next-generation chip is stronger.

Because in the process of chip physical design, the control to the metal winding is difficult and is difficult to carry out secondary inspection, so the S-shaped metal winding in the embodiment of the application can be designed into a splicing module, and the actual physical splicing is carried out in the top module, and the stepping S-shaped winding is indirectly obtained.

For example, the S-shaped metal wire may include a first turn portion, a spliceable portion, and a second turn portion. The S-shaped metal winding can be a left S-shaped winding, a right S-shaped winding or an upper S-shaped winding and a lower S-shaped winding. When the S-shaped metal winding is a left S-shaped winding and a right S-shaped winding, the first turning part is a turning part on the left side, the second turning part is a turning part on the right side, and the part which is not turned in the middle is a part which can be spliced. When the S-shaped metal winding is an upper S-shaped winding and a lower S-shaped winding, the first turning part is a turning part on the upper side, the second turning part is a turning part on the lower side, and the part which is not turned in the middle is a part which can be spliced.

Illustratively, different S-shaped metal windings include different numbers of spliceable sections. Fig. 8 illustrates an example in which the S-shaped metal winding is a left and right S-shaped winding, and as shown in fig. 8 (a), the S-shaped metal winding includes a first turn portion, a second turn portion, and a spliceable portion. As shown in fig. 8 (b), the S-shaped metal wire includes a first turn portion, a second turn portion, and two spliceable portions. That is, the S-shaped metal wire windings with different lengths can be realized by increasing the number of spliceable parts. The method has good controllability, can freely realize splicing according to different design scales and different required delay values, is convenient for secondary inspection, and has good practical engineering significance. It can be understood that the present application can modularize the S-shaped metal windings, each of which can include three parts (a first turning part, a spliceable part, and a second turning part), so that the S-shaped metal windings with different lengths can be made by increasing the number of spliceable parts, and thus, in the multi-turn design or tape-out process, the length of the S-shaped metal winding can be changed by changing the number of spliceable parts to adjust the delay time of the data delay unit.

For example, the input end and the output end of the S-shaped metal winding may be disposed on the same side or different sides. When the input end and the output end of the S-shaped metal winding are arranged on the same side, the first turning part comprises the input end and the output end of the S-shaped metal winding, or the second turning part comprises the input end and the output end of the S-shaped metal winding. When the input end and the output end of the S-shaped metal winding are arranged on different sides, the first turning part comprises the input end of the S-shaped metal winding, and the second turning part comprises the output end of the S-shaped metal winding; alternatively, the first turn portion includes an output terminal of the S-shaped metal winding, and the second turn portion includes an input terminal of the S-shaped metal winding.

It will be appreciated that the inputs of the S-shaped metal windings are coupled to the data output QN of the first register, and the outputs of the S-shaped metal windings are coupled to the data input D of the second register. That is, the input end of the S-shaped metal winding is the starting point of the S-shaped metal winding, and the output end of the S-shaped metal winding is the end point of the S-shaped metal winding.

Optionally, the input end and the output end of the S-shaped metal winding may be located on the same horizontal line, or may be located on different horizontal lines.

For example, in fig. 9, the S-shaped metal winding is taken as a left S-shaped winding and a right S-shaped winding, as shown in (a) of fig. 9, the first turning portion includes an input end of the S-shaped metal winding and an output end of the S-shaped metal winding, and the input end of the S-shaped metal winding and the output end of the S-shaped metal winding are located on different horizontal lines. As shown in (b) of fig. 9, the second turning part includes an input terminal of the S-type metal winding line and an output terminal of the S-type metal winding line, which are located on different horizontal lines. As shown in (c) of fig. 9, the first turn portion includes an input terminal of the S-shaped metal winding line, the second turn portion includes an output terminal of the S-shaped metal winding line, and the input terminal of the S-shaped metal winding line and the output terminal of the S-shaped metal winding line are located on different horizontal lines. As shown in (d) of fig. 9, the second turn portion includes an input end of the S-shaped metal winding, the first turn portion includes an output end of the S-shaped metal winding, and the input end of the S-shaped metal winding and the output end of the S-shaped metal winding are located on different horizontal lines.

For another example, in fig. 10, the S-shaped metal winding is taken as an upper S-shaped winding and a lower S-shaped winding, as shown in (a) of fig. 10, the second turning portion includes an input end of the S-shaped metal winding and an output end of the S-shaped metal winding, and the input end of the S-shaped metal winding and the output end of the S-shaped metal winding are located on the same horizontal line. As shown in (b) of fig. 10, the first turning part includes an input end of the S-shaped metal winding and an output end of the S-shaped metal winding, and the input end of the S-shaped metal winding and the output end of the S-shaped metal winding are located on the same horizontal line. As shown in (c) of fig. 10, the second turn portion includes an input end of the S-shaped metal winding, the first turn portion includes an output end of the S-shaped metal winding, and the input end of the S-shaped metal winding and the output end of the S-shaped metal winding are located on different horizontal lines. As shown in (d) of fig. 10, the first turn portion includes an input end of the S-shaped metal winding, the second turn portion includes an output end of the S-shaped metal winding, and the input end of the S-shaped metal winding and the output end of the S-shaped metal winding are located on different horizontal lines.

Optionally, the detection circuit provided in this embodiment of the application may further include a clock selector and a clock delay circuit, as shown in fig. 11, the controller is connected to the input terminal of the clock selector, the data selection terminal of the clock selector, and the clock terminals of the N first registers, the output terminal of the clock selector is connected to the input terminal of the clock delay circuit, and the output terminal of the clock delay circuit is connected to the clock terminals of the N second registers.

Illustratively, as shown in fig. 11, the clock delay circuit may include M clock delay units, each having a different time delay. In the embodiment of the present application, the value of M is not limited, and fig. 11 illustrates only that M is 32.

The controller is specifically configured to time-divisionally control the clock selector to sequentially select each of the M clock delay units.

For example, the clock selector may be a multiplexer MUX, and the controller may time-share control of the multiplexer MUX. The MUX can be a selector of selecting 1 from M, and the data selection end A in the MUX ₀ To A _k The number of (c) is related to the specific value of M. For example, the controller controls the multiplexer MUX to select one of the 32 clock delay units at intervals to obtain the output states of a group of N second registers, and the controller sequentially selects each of the 32 clock delay units to obtain 32 groups of output results, where each group of output results is used to indicate the output state of each second register. It is understood that when 32 clock delay units are included in the clock delay circuit, the MUX may be a selector of 1 from 32, and the number of data selection terminals may be 5, i.e., the data selection terminals may be a ₀ To A ₄ 。

It should be noted that, when all output results of the N second registers are in a hold fail (hold fail) state or all output results are in a hold pass (hold pass) state, the detection result has no practical guiding significance, and the hold time margin cannot be determined. And determining whether the boundary condition of the design stage is too tight or too loose according to the detection result and the simulation result of the design stage only when the output states of the N second registers have a hold failure (hold fail) state and a hold success (hold pass) state. Therefore, the controller selects different clock delay units in a time-sharing manner, and can perform wide-range adjustment, so that the output states of the N second registers have a hold failure (hold fail) state and a hold pass (hold pass) state.

Optionally, the controller may further control the clock selector to select the first clock delay unit in the clock delay module; if the output states of the N second registers are all successfully maintained (threshold pass), the controller controls the clock selector to select a second clock delay unit in the clock delay module, and the time delay of the second clock delay unit is larger than that of the first clock delay unit; if the output states of the N second registers are all hold fail (hold fail), the controller controls the clock selector to select a third clock delay unit in the clock delay module, and the time delay of the third clock delay unit is smaller than that of the first clock delay unit. Through the closed-loop control of the controller, the output states of the N second registers can be enabled to have a hold failure (hold fail) state and a hold pass (hold pass) state.

Optionally, the detection circuit provided in this embodiment of the application may further include an interface circuit, as shown in fig. 12, the controller is connected to the interface circuit, and the controller is further configured to transmit the output states of the N second registers to the interface circuit. The interface circuit is used for transmitting data to other devices. For example, the interface circuit may transmit the detection result of the test circuit to the external device.

For example, fig. 3, fig. 8 and fig. 9 are only illustrated by the example that the generator includes a set of test circuits. The specific number of test circuits included in the generator is not limited in the embodiments of the present application, and for example, the generator may also include two sets of test circuits or three sets of test circuits.

It should be noted that the Process Voltage Temperature (PVT) of the N first registers and the N second registers included in the same set of test circuits is the same, and the PVT may be a Standard Voltage Threshold (SVT), a Low Voltage Threshold (LVT), or an Ultra Low Voltage Threshold (ULVT).

For example, as shown in fig. 13, the generator includes three sets of test circuits, and PVTs of N first registers and N second registers in the first set of test circuits are SVTs. The PVTs of the N first registers and the N second registers in the second group of test circuits are both LVTs. The PVTs of the N first registers and the N second registers in the third group of test circuits are both ULVT.

The test circuit in the embodiment of the application arranges the N S-shaped metal windings between the N first registers and the N second registers, the lengths of the N S-shaped metal windings are sequentially increased, and the increasing stepping precision is related to the length difference between the two adjacent S-shaped metal windings, so that the detection precision of the retention time margin can be controlled by designing the length difference between the two adjacent S-shaped metal windings, the precision of the detected retention time margin is higher, a powerful basis can be provided for the design of a next generation chip based on the detection result, and the product competitiveness of the next generation chip is stronger.

The steps of a method or algorithm described in connection with the disclosure herein may be embodied in hardware or in software instructions executed by a processor. The software instructions may be comprised of corresponding software modules that may be stored in Random Access Memory (RAM), flash Memory, erasable Programmable read-only Memory (EPROM), electrically Erasable Programmable read-only Memory (EEPROM), registers, a hard disk, a removable disk, a compact disc read-only Memory (CD-ROM), or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. Of course, the storage medium may also be integral to the processor. The processor and the storage medium may reside in an ASIC. Additionally, the ASIC may reside in a core network interface device. Of course, the processor and the storage medium may reside as discrete components in a core network interface device.

Those skilled in the art will recognize that, in one or more of the examples described above, the functions described in this invention may be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.

The above-mentioned embodiments, objects, technical solutions and advantages of the present invention are further described in detail, it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made on the basis of the technical solutions of the present invention should be included in the scope of the present invention.

Claims

A detection circuit for maintaining a time margin, the detection circuit comprising: a controller, a generator and a decision circuit; the generator comprises at least one group of test circuits, each group of test circuits comprises N first registers, N second registers and N data delay units, time delays of the N data delay units are sequentially increased, the time delay difference between two adjacent data delay units is smaller than or equal to a preset value, and N is an integer larger than 1; the clock ends of the N first registers and the clock ends of the N second registers are connected to the same clock output end of the controller, the data output ends of the N first registers are respectively connected with the input ends of the N data delay units, the output ends of the N data delay units are respectively connected with the data input ends of the N second registers, and the data output ends of the N second registers are connected with the decision circuit;

the decision circuit is used for detecting the output states of the N second registers and transmitting the output states of the N second registers to the controller.
The circuit of claim 1, wherein the N data delay units comprise N S-shaped metal windings, respectively, and wherein the N S-shaped metal windings have sequentially increasing lengths.
The circuit of claim 2, wherein a difference in length between adjacent ones of the N S-shaped metal windings is the same.
The circuit of claim 3, wherein the S-shaped metal wire comprises a first turn portion, a second turn portion, and one or more spliceable portions, wherein different S-shaped metal wires comprise different numbers of spliceable portions.
The circuit of claim 4, wherein the first transition portion comprises an input end of the S-shaped metal winding and an output end of the S-shaped metal winding; or, the second turning part comprises an input end of the S-shaped metal winding and an output end of the S-shaped metal winding.
The circuit of claim 4, wherein the first turn portion comprises an input of the S-shaped metal winding and the second turn portion comprises an output of the S-shaped metal winding; alternatively, the first turning part includes an output end of the S-shaped metal winding, and the second turning part includes an input end of the S-shaped metal winding.
The circuit of any of claims 1-6, wherein the detection circuit further comprises a clock selector and a clock delay circuit, the controller is coupled to an input of the clock selector, a data select terminal of the clock selector, and a clock terminal of the N first registers, an output of the clock selector is coupled to an input of the clock delay circuit, and an output of the clock delay circuit is coupled to a clock terminal of the N second registers.
The circuit of claim 7, wherein the clock delay circuit comprises M clock delay units, each of the M clock delay units having M different time delays.
The circuit of claim 8, wherein the controller is specifically configured to time-divisionally control the clock selector to sequentially select each of the M clock delay units.
The circuit of claim 8, wherein the controller is specifically configured to:

controlling the clock selector to select a first clock delay cell of the M clock delay cells;

if the output states of the N second registers are successfully kept, the controller controls the clock selector to select a second clock delay unit in the M clock delay units, and the time delay of the second clock delay unit is greater than that of the first clock delay unit;

and if the output states of the N second registers are all failed to be maintained, the controller controls the clock selector to select a third clock delay unit in the M clock delay units, and the time delay of the third clock delay unit is smaller than that of the first clock delay unit.
The circuit of any of claims 1-10, wherein the detection circuit further comprises an interface circuit, and wherein the controller is coupled to the interface circuit, the controller further configured to transmit the output states of the N second registers to the interface circuit.
The circuit according to any one of claims 1-11, wherein the process voltage temperatures PVT of the N first registers and the N second registers in the same group of test circuits are the same, and the PVT is a standard voltage threshold SVT, a low voltage threshold LVT or an ultra-low voltage threshold ULVT.
An apparatus comprising a circuit board and a detection circuit to maintain a time margin as claimed in any one of claims 1 to 12.