CN115664625A

CN115664625A - Clock phase determination method and device, near field communication equipment and readable storage medium

Info

Publication number: CN115664625A
Application number: CN202211593025.8A
Authority: CN
Inventors: 黄金煌
Original assignee: Beijing Unigroup Tsingteng Microsystems Co Ltd
Current assignee: Beijing Unigroup Tsingteng Microsystems Co Ltd
Priority date: 2022-12-13
Filing date: 2022-12-13
Publication date: 2023-01-31
Anticipated expiration: 2042-12-13
Also published as: CN115664625B

Abstract

The application relates to the technical field of near field communication and discloses a clock phase determining method. In a plurality of sampling phases, the method determines a target clock phase meeting a field intensity condition according to the radio frequency field intensity corresponding to each sampling phase. Compared with the clock generated by the phase-locked loop, the time for sampling on each sampling phase and obtaining the field intensity is shorter, so that the target phase can be quickly determined by the field intensity, the clock adjustment time is shortened, and the digital communication efficiency is improved. The application also discloses a clock phase determining device, near field communication equipment and a readable storage medium.

Description

Clock phase determining method and device, near field communication equipment and readable storage medium

Technical Field

The present application relates to the field of near field communication technologies, and in particular, to a clock phase determining method and apparatus, a near field communication device, and a readable storage medium.

Background

In an NFC (Near Field Communication) Communication PCD (Proximity coupling device) mode, in order to ensure that a sampling clock can accurately sample a peak value of a received carrier, calibration of a clock phase needs to be completed, so that clock frequency phases of a card reader and a card are kept consistent.

To ensure that the transmit and receive clocks remain consistent, a digital phase-locked loop (DPLL) is typically used to generate the clocks to maintain phase alignment with the recovered clock in the communication field.

However, in the process of implementing the embodiment of the present disclosure, it is found that at least the following problems exist in the related art:

in some special application environments, once the clock phase changes, the digital phase-locked loop technology needs a long time to adjust the phase, and further needs a long time to perform digital communication.

It is noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the application and therefore may include information that does not constitute prior art that is already known to a person of ordinary skill in the art.

Disclosure of Invention

The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview nor is intended to identify key/critical elements or to delineate the scope of such embodiments but rather as a prelude to the more detailed description that is presented later.

The embodiment of the disclosure provides a clock phase determining method and device, near field communication equipment and a readable storage medium, so as to improve the accuracy of data sending and receiving of the near field communication equipment.

In some embodiments, the method comprises: acquiring a plurality of sampling phases of a radio frequency device; wherein the phase values of any two of the plurality of sampling phases are different; setting a clock of the radio frequency device on each sampling phase to perform multiple sampling, and obtaining multiple radio frequency field strengths corresponding to each sampling phase; and determining the sampling phase corresponding to the radio frequency field intensity meeting the preset field intensity condition as the target clock phase of the radio frequency device.

Optionally, the plurality of sampling phases includes a clock phase of an initial clock of the radio frequency device; the step of obtaining a plurality of sampling phases of the radio frequency device comprises: acquiring phase increment; and increasing the clock phase of the initial clock by one or more phase increments to obtain a plurality of sampling phases meeting a preset phase condition.

Optionally, the preset phase condition is that the number of the sampling phases reaches a preset number threshold.

Optionally, the preset phase condition is that a maximum phase of all the sampling phases is smaller than a preset phase threshold.

Optionally, the phase increment is 10 degrees.

Optionally, the step of setting the clock of the radio frequency device at each sampling phase to perform multiple sampling includes: and after setting the clock of the radio frequency device on each sampling phase, carrying out multiple times of sampling within the preset clock establishing time.

Optionally, the step of determining a sampling phase corresponding to the radio frequency field strength meeting the preset field strength condition as a target clock phase of the radio frequency device includes: selecting the maximum radio frequency field intensity from the radio frequency field intensities; and determining the maximum radio frequency field intensity as the radio frequency field intensity meeting the preset field intensity condition, and determining the sampling phase corresponding to the maximum radio frequency field intensity as the target clock phase of the radio frequency device.

In some embodiments, the apparatus comprises: a phase acquisition module configured to acquire a plurality of sampling phases of a radio frequency device; wherein the phase values of any two of the plurality of sampling phases are different; the sampling module is configured to set a clock of the radio frequency device on each sampling phase to perform multiple sampling, so as to obtain multiple radio frequency field strengths corresponding to each sampling phase; the phase determination module is configured to determine a sampling phase corresponding to the radio frequency field intensity meeting a preset field intensity condition as a target clock phase of the radio frequency device.

In some embodiments, the clock phase determination apparatus includes a processor and a memory storing program instructions, and the processor is configured to execute the clock phase determination method in the above embodiments when executing the program instructions.

In some embodiments, the near field communication device comprises: an apparatus main body; and the clock phase determining apparatus in the above embodiment, which is installed in the device main body.

The clock phase determining method and device, the near field communication device and the readable storage medium provided by the embodiment of the disclosure can achieve the following technical effects:

and in the plurality of sampling phases, determining a target clock phase meeting the field intensity condition according to the radio frequency field intensity corresponding to each sampling phase. Compared with the clock generated by the phase-locked loop, the time for sampling on each sampling phase and obtaining the field intensity is shorter, so that the target phase can be quickly determined by the field intensity, the clock adjustment time is shortened, and the digital communication efficiency is improved.

The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.

Drawings

One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the accompanying drawings and not in limitation thereof, in which elements having the same reference numeral designations are shown as like elements and not in limitation thereof, and wherein:

fig. 1 is a schematic structural diagram of a transceiving path in an NFC communication PCD mode;

fig. 2 is a signal diagram of each clock in the NFC chip;

fig. 3 is a schematic flowchart of a clock phase determining method according to an embodiment of the disclosure;

fig. 4 is a schematic flowchart of another clock phase determining method according to an embodiment of the disclosure;

fig. 5 is a schematic flowchart of a method for determining a target clock phase in an actual application scenario according to an embodiment of the present disclosure;

fig. 6 is a timing diagram of a clock phase determination method provided by an embodiment of the present disclosure;

fig. 7 is a schematic diagram of clock phase switching obtained by a clock phase determination method according to an embodiment of the disclosure;

fig. 8 is a schematic structural diagram of a clock phase determining apparatus according to an embodiment of the present disclosure;

fig. 9 is a schematic structural diagram of another clock phase determining apparatus according to an embodiment of the present disclosure;

fig. 10 is a schematic structural diagram of a near field communication device according to an embodiment of the present disclosure.

Detailed Description

So that the manner in which the features and elements of the disclosed embodiments can be understood in detail, a more particular description of the disclosed embodiments, briefly summarized above, may be had by reference to the embodiments, some of which are illustrated in the appended drawings. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may be practiced without these details. In other instances, well-known structures and devices may be shown in simplified form in order to simplify the drawing.

The terms "first," "second," and the like in the description and in the claims, and the above-described drawings of embodiments of the present disclosure, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged as appropriate for the embodiments of the disclosure described herein. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion.

The term "plurality" means two or more, unless otherwise specified.

In the embodiment of the present disclosure, the character "/" indicates that the preceding and following objects are in an or relationship. For example, A/B represents: a or B.

The term "and/or" is an associative relationship that describes objects, meaning that three relationships may exist. E.g., a and/or B, represents: a or B, or A and B.

NFC (Near Field Communication) operates at a frequency of 13.56MHz within a distance of 20 cm, and has three transmission speeds of 106 Kbit/s, 212 Kbit/s, or 424 Kbit/s. The method specifically comprises three working modes: a peer-to-peer communication mode, a PCD (Card reader) reader mode, and a PICC (near field communication Card or Proximity Integrated Circuit Card) Card emulation mode.

Fig. 1 is a schematic structural diagram of a transceiving path in a PCD mode for NFC communication. As shown in fig. 1, the NFC device includes a digital processing module 101, a transmitting module 102, and a receiving module 103, where the digital processing module 101 generates a transmitting clock tx _ clk and a receiving clock rx _ clk, and the transmitting clock transmits a 13.56M radio frequency field through the transmitting module 102, and transmits data to be transmitted based on the radio frequency field. Accordingly, the receiving module 103 receives data coupled from the antenna based on the receive clock.

Fig. 2 is a schematic diagram of signals of respective clocks in the NFC chip. As can be seen from fig. 2, the field on the tx antenna generated by the transmitting module 102 has a certain delay from the tx clock tx _ clk, and the field on the rx antenna generated by the receiving module 103 also has a delay after passing through the antenna, so that it is not accurate to sample data by using the rx clock rx _ clk. With further reference to fig. 2, ideal clk is the theoretical ideal sampling clock, and at the rising edge of the ideal clk, the field strength of the field collected on the rx antenna is at a maximum. Based on this theory, the embodiments of the present disclosure propose to find a phase, which makes the field strength satisfy a preset condition, from among a plurality of phases, as a target phase of the transmission clock and the reception clock.

Referring to fig. 3, a clock phase determining method provided for the embodiment of the present disclosure includes the following steps:

s301: the NFC chip acquires a plurality of sampling phases of the radio frequency device.

Wherein the phase values of any two of the plurality of sampling phases are different. The plurality of sampling phases of the radio frequency device may be acquired in various manners, and the plurality of sampling phases required by the embodiment of the disclosure may be acquired as long as the phase values of every two sampling phases in the plurality of acquired sampling phases are different.

S302: and the NFC chip sets the clock of the radio frequency device on each sampling phase to perform multiple sampling, and multiple radio frequency field intensities corresponding to each sampling phase are obtained.

After the plurality of sampling phases are determined, the NFC chip sets the clock of the radio frequency device at each sampling phase and performs a plurality of samplings at each sampling phase. Specifically, the number of times sampling is performed at each sampling phase may be the same or different. The time at which sampling is performed at each sampling phase may be the same or different. The disclosed embodiment does not limit the duration, number and interval of sampling.

S303: and the NFC chip determines the sampling phase corresponding to the radio frequency field intensity meeting the preset field intensity condition as the target clock phase of the radio frequency device.

According to the clock phase determining method provided by the embodiment of the disclosure, in a plurality of sampling phases, a target clock phase satisfying a field intensity condition is determined according to a radio frequency field intensity obtained by sampling at each sampling phase. Compared with the clock generated by the phase-locked loop, the time for sampling on each sampling phase and obtaining the field intensity is shorter, so that the target phase can be quickly determined by the field intensity, the clock adjustment time is shortened, and the digital communication efficiency is improved.

In the step S301, multiple sampling phases of the radio frequency device are obtained, and the multiple sampling phases may be obtained in multiple ways, in some examples, the multiple sampling phases may be randomly selected within a certain range, and the phase difference between two adjacent sampling phases may be the same or different.

However, this way of randomly selecting the sampling phases may result in that the selected sampling phases are not uniform, so that the phases of a certain region are missed.

Optionally, the plurality of sampling phases in step S301 includes a clock phase of an initial clock of the radio frequency device; the step of obtaining a plurality of sampling phases of the radio frequency device comprises:

(1) The phase increment is obtained.

(2) And increasing the clock phase of the initial clock by one or more phase increment to obtain a plurality of sampling phases meeting a preset phase condition.

The specific address, phase increment may be preset, for example, manually through experience. The phase increment can also be temporarily set each time according to actual needs. The setting time and the setting mode of the phase increment are not limited in the embodiment of the disclosure.

The initial clock is the current clock of the rf device before performing phase calibration. The initial clock is generated by an external crystal oscillator after the NFC chip is powered on. The sampling phase may be a plurality of phases obtained based on the clock phase of the initial clock, and the target clock phase is found with a high probability in the vicinity of the clock phase of the initial clock, and therefore, the clock phase of the initial clock is included in the plurality of sampling phases. And determining the other of the plurality of sampling phases based on the clock phase of the initial clock. For example, the clock phase of the initial clock may be set to P0. The plurality of sampling phases may be irregular phase values, such as P0+10 °, P0+15 °, P0+23 °, and so on. The plurality of sampling phases may also be a plurality of phase values obtained according to a preset rule, for example, the phase interval is 10 °, and the obtained plurality of sampling phases are P0+10 °, P0+20 °, P0+30 °, and the like.

Optionally, the preset phase condition is that the number of the sampling phases reaches a preset number threshold. Specifically, after increasing a plurality of phase increments to the clock phase of the initial clock, the number of the obtained sampling phases is equal to the preset number, and it is determined that the obtained sampling phases satisfy the preset phase condition.

Alternatively, the preset number threshold may be set to 36. For example, continuing to take the clock phase of the initial clock as P0 as an example, one phase increment is added to P0 to obtain a sampling phase P1, two phase increments are added to P0 to obtain a sampling phase P2, and so on until 35 phase increments are added to P0 to obtain a sampling phase P35, and then 36 sampling phases P0-P35 constitute a plurality of sampling phases.

Optionally, the phase increment is 10 degrees. Thus, starting from 0 degrees, 10 degrees are added each time, 36 sampling phases are obtained in total, and the 36 sampling phases form one sampling period, so that the whole sampling period can be covered, and omission of a certain area is avoided. The digital circuit in the embodiment of the disclosure selects by using 36 equally spaced 13.56MHz sampling clocks, and increases the accuracy of the phase calibration to 10 °. Each time the phase of 36 paths is changed by 10 degrees, a path of clock clk [0] is generated, and so on, and clk [1] to clk [35]36 paths of clocks are generated in total. Since the field signal of the antenna is a sine wave, the clock signal is a square wave, one complete cycle is 360 °, and for calculation convenience, the phase is switched every 10 °, so 36 paths are provided.

In order to obtain more accurate phase values, the phase increment can also be set smaller, for example 8 °, 6 °, 5 °. Accordingly, the preset number is set to be more so that the values of all sampling phases cover the whole sampling period.

In order to increase the efficiency of the phase determination, the phase increment may also be set larger, and correspondingly, the preset number may be set smaller. Therefore, the target clock phase can be obtained quickly, and the phase adjustment time is saved.

For example, after a phase increment is added to the clock phase of the initial clock each time, it is determined whether the obtained new sampling phase is smaller than a preset phase threshold, and if so, the phase increment is continuously added until the new sampling phase is greater than or equal to the preset phase threshold, and the generation of the new sampling phase is stopped.

Step S302 in the above embodiment (setting the clock of the radio frequency device to perform multiple sampling at each sampling phase) may perform multiple sampling at equal time intervals. The number of samples in each sampling phase may or may not be equal. Multiple samples may also be taken at different time intervals.

Optionally, the step of setting the clock of the radio frequency device at each sampling phase to perform multiple sampling includes: and setting the clock of the radio frequency device on each sampling phase, and then carrying out multiple times of sampling within the setup time of the preset clock.

Referring specifically to fig. 2, at the rising edge of rx _ clk, the corresponding field strength is sampled and recorded. And switching the clock phase after sampling for n times according to the preset sampling times, repeating the steps, traversing all the phase clocks, and finding out the maximum field intensity signal according to the field intensity recorded by sampling, namely finding out the optimal clock phase. Therefore, sampling is carried out for the same times at the same time on each sampling phase, the corresponding field intensity on each phase can be objectively reflected, and the target clock phase determined according to the field intensity is more accurate.

The preset field strength condition in step S303 in the above embodiment may be a field strength condition of various forms. For example, the predetermined field strength condition is that the radio frequency field strength is greater than a predetermined threshold. Therefore, as long as the radio frequency field intensity which is larger than the preset threshold value is found, the target clock phase is determined, and the phase calibration efficiency can be improved.

Optionally, the preset field strength condition may be further configured to select a maximum radio frequency field strength from the radio frequency field strengths. The method comprises the following steps of determining a sampling phase corresponding to the radio frequency field intensity meeting the preset field intensity condition as a target clock phase of the radio frequency device, wherein the steps comprise: selecting the maximum radio frequency field intensity from the radio frequency field intensities; and determining the maximum radio frequency field intensity as the radio frequency field intensity meeting the preset field intensity condition, and determining the sampling phase corresponding to the maximum radio frequency field intensity as the target clock phase of the radio frequency device.

The larger the field intensity is, the smaller the delay between the field corresponding to the phase and the clock signal is, so that the consistency of the clock can be further improved by selecting the target phase corresponding to the maximum field intensity.

With reference to fig. 4, another clock phase determining method provided for the embodiment of the present disclosure includes the following steps:

s401: the NFC chip acquires the phase increment.

S402: and the NFC chip increases the clock phase of the initial clock by one or more phase increment to obtain a plurality of sampling phases meeting the preset phase condition.

S403: and after the NFC chip sets the clock of the radio frequency device on each sampling phase, sampling for multiple times within the preset clock establishing time to obtain multiple radio frequency field strengths corresponding to each sampling phase.

S404: and the NFC chip selects the maximum radio frequency field intensity from the radio frequency field intensities, and determines the sampling phase corresponding to the maximum radio frequency field intensity as the target clock phase of the radio frequency device.

By the method provided by the embodiment of the disclosure, a plurality of sampling phases can be generated based on the clock phase of the initial clock, and the sampling phases generated based on the clock phase of the initial clock can be finely adjusted based on the clock phase of the initial clock, so that the phase meeting the condition can be determined quickly. And selecting the field intensity generated by the plurality of sampling phases, and selecting the sampling phase corresponding to the maximum field intensity as a target clock phase. The sampling phase selected based on the maximum field intensity can enable the receiving clock to be more consistent with the sending clock, and accuracy and stability of sending data and receiving data are improved.

How to determine the target clock phase in the practical application scenario is described in detail below with reference to fig. 5.

S501: the NFC chip acquires system configuration.

The radio frequency equipment is NFC equipment, and a special NFC chip is arranged in an NFC communication system. The NFC chip integrates the clock phase determination method provided in the embodiments of the present disclosure, and may select whether to start the algorithm through register configuration. The user can select whether to start the method or not through register configuration when using the method.

If the user is determined to open the method, system configuration is obtained. The system configuration includes the clock phase of the initial clock, the time of each sample, the number of times of each sample, the phase difference between every two sampling phases, etc.

S502: the clock is fixed at the nth sampling phase and the received field strength is sampled with equally spaced 13.56MHz candidate clocks.

Wherein N is a positive integer of 0 to 35. And N starts from 0, and when N is 0, the corresponding sampling phase is the clock phase of the initial clock of the NFC chip. The N sampling phases are 36 phases corresponding to the clock phase of the initial clock, and the difference value between each phase and the adjacent phase is 10 degrees.

Fig. 6 is a timing diagram of a clock phase determination method according to an embodiment of the disclosure. Fig. 7 is a schematic diagram of clock phase switching obtained by the clock phase determining method according to the embodiment of the disclosure. As shown in fig. 6 and 7, the START signal is pulled high to indicate that the clock phase determination method is started, the value of the ADC _ DATA indicates the magnitude of the sampled field strength, tsetup and Tstable time are configured according to requirements, the clock phase selection signal is traversed from 0 to 35, and the DONE signal is pulled high to indicate that the method is ended.

S503: judging whether N is less than or equal to 35, if so, executing step S504; otherwise, step S505 is executed.

S504: n is incremented by 1 and step S502 is re-executed.

S505: and calculating the maximum field intensity in the 36 sampling results, and determining the sampling phase corresponding to the field intensity as the target clock phase.

For example, it is calculated that the maximum field strength is determined to occur at the clock phase +40 ° of the initial clock, and thus the target clock phase is +40 ° of the clock phase of the initial clock.

As shown in fig. 8, an embodiment of the present disclosure provides a clock phase determination apparatus 800, which includes a phase obtaining module 801, a sampling module 802, and a phase determination module 803. Wherein the phase acquisition module 801 is configured to acquire a plurality of sampling phases of the radio frequency device; wherein the phase values of any two of the plurality of sampling phases are different. The sampling module 802 is configured to set a clock of the radio frequency device at each of the sampling phases to perform multiple sampling, and obtain multiple radio frequency field strengths corresponding to each of the sampling phases. The phase determination module 803 is configured to determine a sampling phase corresponding to the radio frequency field strength satisfying a preset field strength condition as a target clock phase of the radio frequency device.

By adopting the clock phase determining device provided by the embodiment of the disclosure, in a plurality of sampling phases, the target clock phase meeting the field intensity condition is determined according to the radio frequency field intensity corresponding to each sampling phase. Compared with the clock generated by the phase-locked loop, the time for sampling on each sampling phase and obtaining the field intensity is shorter, so that the target phase can be quickly determined by the field intensity, the clock adjustment time is shortened, and the digital communication efficiency is improved.

Optionally, the plurality of sampling phases includes a clock phase of an initial clock of the radio frequency device; the phase obtaining module 801 is specifically configured to: acquiring phase increment; and increasing the clock phase of the initial clock by one or more phase increments to obtain a plurality of sampling phases meeting a preset phase condition.

Optionally, the phase increment is 10 degrees.

Optionally, the sampling module 802 is specifically configured to: and after setting the clock of the radio frequency device on each sampling phase, carrying out multiple times of sampling within the preset clock establishing time.

Optionally, the phase determining module 803 is specifically configured to: selecting the maximum radio frequency field intensity from the radio frequency field intensities; and determining the maximum radio frequency field intensity as the radio frequency field intensity meeting the preset field intensity condition, and determining the sampling phase corresponding to the maximum radio frequency field intensity as the target clock phase of the radio frequency device.

As shown in fig. 9, an embodiment of the present disclosure provides a clock phase determining apparatus 900, which includes a processor (processor) 100 and a memory (memory) 101. Optionally, the apparatus may also include a Communication Interface (Communication Interface) 102 and a bus 103. The processor 100, the communication interface 102, and the memory 101 may communicate with each other through the bus 103. The communication interface 102 may be used for information transfer. The processor 100 may call logic instructions in the memory 101 to perform the clock phase determination method of the above embodiments.

In addition, the logic instructions in the memory 101 may be implemented in the form of software functional units and stored in a computer readable storage medium when the logic instructions are sold or used as independent products.

The memory 101 is used as a computer readable storage medium for storing software programs, computer executable programs, such as program instructions/modules corresponding to the methods in the embodiments of the present disclosure. The processor 100 executes functional applications and data processing, i.e., implements the clock phase determination method in the above-described embodiments, by executing program instructions/modules stored in the memory 101.

The memory 101 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the terminal device, and the like. In addition, the memory 101 may include a high-speed random access memory, and may also include a nonvolatile memory.

As shown in fig. 10, an embodiment of the present disclosure provides a near field communication device 1000, including: a product body, and a clock phase determination device 800 shown in fig. 8 or a clock phase determination device 900 shown in fig. 9. The clock phase determination apparatus 800 (900) is mounted to the product body. The installation relationship stated herein is not limited to being placed inside the product, but also includes installation connection with other components of the product, including but not limited to physical connection, electrical connection, or signal transmission connection. It will be appreciated by those skilled in the art that the clock phase determination means 800 (900) may be adapted to a feasible near field communication device, thereby enabling other feasible embodiments.

Embodiments of the present disclosure provide a computer-readable storage medium storing computer-executable instructions configured to perform the clock phase determination method described above.

Embodiments of the present disclosure provide a computer program product comprising a computer program stored on a computer readable storage medium, the computer program comprising program instructions which, when executed by a computer, cause the computer to perform the above-mentioned clock phase determination method.

The computer readable storage medium described above may be a transitory computer readable storage medium or a non-transitory computer readable storage medium.

The technical solution of the embodiments of the present disclosure may be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for enabling a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present disclosure. And the aforementioned storage medium may be a non-transitory storage medium comprising: a U-disk, a portable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other media capable of storing program codes, and may also be a transient storage medium.

The above description and the drawings sufficiently illustrate embodiments of the disclosure to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. The examples merely typify possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in or substituted for those of others. Furthermore, the words used in the specification are words of description only and are not intended to limit the claims. As used in the description of the embodiments and the claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Similarly, the term "and/or" as used in this application is meant to encompass any and all possible combinations of one or more of the associated listed. Furthermore, the terms "comprises" and/or "comprising," when used in this application, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Without further limitation, an element defined by the phrase "comprising one of 8230," does not exclude the presence of additional like elements in a process, method or device comprising the element. In this document, each embodiment may be described with emphasis on differences from other embodiments, and the same and similar parts between the respective embodiments may be referred to each other. For methods, products, etc. of the embodiment disclosure, reference may be made to the description of the method section for relevance if it corresponds to the method section of the embodiment disclosure.

Those of skill in the art would appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software may depend upon the particular application and design constraints imposed on the technical solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments. It can be clearly understood by the skilled person that, for convenience and brevity of description, the specific working processes of the system, the apparatus and the unit described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the embodiments disclosed herein, the disclosed methods, products (including but not limited to devices, apparatuses, etc.) may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units may be merely a logical division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form. The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to implement the present embodiment. In addition, functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. In the description corresponding to the flowcharts and block diagrams in the figures, operations or steps corresponding to different blocks may also occur in different orders than disclosed in the description, and sometimes there is no specific order between the different operations or steps. For example, two sequential operations or steps may in fact be executed substantially concurrently, or they may sometimes be executed in the reverse order, depending upon the functionality involved. Each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Claims

1. A method of clock phase determination, the method comprising:

acquiring a plurality of sampling phases of a radio frequency device; wherein the phase values of any two of the plurality of sampling phases are different;

setting a clock of the radio frequency device on each sampling phase to perform multiple sampling, and obtaining multiple radio frequency field intensities corresponding to each sampling phase;

and determining the sampling phase corresponding to the radio frequency field intensity meeting the preset field intensity condition as the target clock phase of the radio frequency device.

2. The method of claim 1, wherein the plurality of sampling phases comprises a clock phase of an initial clock of the radio frequency device; the step of acquiring a plurality of sampling phases of the radio frequency device comprises:

acquiring phase increment;

and increasing the clock phase of the initial clock by one or more phase increments to obtain a plurality of sampling phases meeting a preset phase condition.

3. The method of claim 2, wherein the predetermined phase condition is that the number of sampling phases reaches a predetermined number threshold.

4. The method of claim 2, wherein the predetermined phase condition is that a maximum phase of all the sampling phases is less than a predetermined phase threshold.

5. The method of claim 2, wherein the phase increment is 10 degrees.

6. The method of claim 1, wherein setting the clock of the radio frequency device to perform a plurality of samples at each of the sampling phases comprises:

and after setting the clock of the radio frequency device on each sampling phase, carrying out multiple times of sampling within the preset clock establishing time.

7. The method of claim 1, wherein the step of determining the sampling phase corresponding to the radio frequency field intensity satisfying the preset field intensity condition as the target clock phase of the radio frequency device comprises:

selecting the maximum radio frequency field intensity from the radio frequency field intensities;

and determining the maximum radio frequency field intensity as the radio frequency field intensity meeting the preset field intensity condition, and determining the sampling phase corresponding to the maximum radio frequency field intensity as the target clock phase of the radio frequency device.

8. A clock phase determination apparatus, comprising:

a phase acquisition module configured to acquire a plurality of sampling phases of a radio frequency device; wherein the phase values of any two of the plurality of sampling phases are different;

the sampling module is configured to set a clock of the radio frequency device on each sampling phase to perform multiple sampling, so as to obtain multiple radio frequency field strengths corresponding to each sampling phase;

the phase determination module is configured to determine a sampling phase corresponding to the radio frequency field intensity meeting a preset field intensity condition as a target clock phase of the radio frequency device.

9. A clock phase determination apparatus comprising a processor and a memory having stored thereon program instructions, wherein the processor is configured to perform the clock phase determination method of any one of claims 1 to 7 when executing the program instructions.

10. A near field communication device, comprising:

an apparatus main body; and the number of the first and second groups,

the clock phase determination apparatus of claim 8 or 9, mounted within the device body.

11. A computer-readable storage medium having stored thereon computer-executable instructions configured to perform the clock phase determination method of any one of claims 1 to 7.