CN115658575B - Data serial port communication system and method and electronic equipment - Google Patents
Data serial port communication system and method and electronic equipment Download PDFInfo
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Abstract
The present disclosure relates to the technical field of computers, and discloses a data serial port communication system, a method and an electronic device, wherein the system comprises: firmware, a data transceiving engine, and a universal asynchronous receiver/transmitter, wherein: the firmware is used for writing target data into an internal cache of the data transceiving engine; the data transceiving engine is used for sending the data in the internal cache to the universal asynchronous receiver-transmitter; the universal asynchronous transceiver is used for transmitting received data to be transmitted to a receiving end according to a serial port communication protocol, and transmitting an interrupt signal to the data receiving and transmitting engine after transmitting the data to the receiving end, wherein the interrupt signal is used for indicating the data receiving and transmitting engine to transmit the data to the universal asynchronous transceiver. The embodiment of the disclosure can improve the operating efficiency of the firmware.
Description
Technical Field
The present disclosure relates to the field of computer technologies, and in particular, to a serial data communication system and method, and an electronic device.
Background
In embedded software development, firmware (Firmware) runs on a hardware development board, and software and hardware state information is printed to a serial port tool of a computer (PC) end through a Universal Asynchronous Receiver/Transmitter (UART) serial port, so that development and debugging are facilitated for developers, and the serial port tool of the PC end is used for example Putty and the like. The printed status information includes some information that the developer needs to view during the development process in order to know the operating status of the hardware development board.
Fig. 1 is a block diagram showing a data serial communication system in a development board, and as shown in fig. 1, firmware in the development board transmits data byte by byte into a hardware buffer (buffer) of a UART internal transmission module (Tx). In this process, after the firmware sends a byte to the buffer of the Tx in the UART, it needs to wait for a period of time (ms level) until the Tx of the UART sends an interrupt to the firmware, indicating that the byte has been successfully sent from the buffer of the Tx to the PC, and the firmware can write the next byte to the buffer of the Tx.
The length of this waiting time depends on the baud rate of the UART. The lower the baud rate, the longer the waiting time is required. Taking a project of an 8051 chip actually developed as an example, an operating frequency of a Micro Controller Unit (MCU) of the 8051 chip is 20M, and a baud rate is 19200bps. According to our experimental statistics, printing a string of 128 bytes in length requires a total of about 7ms for writing the string to Tx buffer and 64ms for waiting for the UART to send the string to the PC. If the UART baud rate is lower, e.g., 9600bps, this latency will also increase by a factor of about 1.
In summary, in the related art, the firmware has a long waiting time and a low efficiency when sending data to the computer through the UART.
Disclosure of Invention
The present disclosure provides a data serial port communication technical scheme.
According to an aspect of the present disclosure, there is provided a serial data communication system, the system including: firmware, a data transceiving engine, and a universal asynchronous receiver/transmitter, wherein: the firmware is used for writing target data into an internal cache of the data transceiving engine; the data transceiving engine is used for sending the data in the internal cache to the universal asynchronous receiver-transmitter; the universal asynchronous receiver/transmitter is used for transmitting the received data to be transmitted to a receiving end according to a serial port communication protocol, and transmitting an interrupt signal to the data receiving/transmitting engine after transmitting the data to the receiving end, wherein the interrupt signal is used for indicating the data receiving/transmitting engine to transmit the data to the universal asynchronous receiver/transmitter.
In a possible implementation manner, the data transceiver engine is a digital logic circuit disposed on a chip, and the data transceiver engine and the universal asynchronous receiver/transmitter are disposed in the same chip.
In one possible implementation, the data transceiving engine comprises: a first recording unit, a second recording unit, and a firmware write operation control unit; the first recording unit is used for recording a first data volume of target data written into an internal cache of the data transceiving engine by firmware; the second recording unit is used for recording a second data volume of the data sent to the universal asynchronous receiver/transmitter by the data receiving/transmitting engine; and the firmware writing operation control unit is used for controlling the firmware to write data to the data transceiving engine according to the first data volume and the second data volume.
In a possible implementation manner, the first recording unit includes a write pointer, and in a case where the firmware writes one byte of data into an internal buffer of the data transceiving engine, the write pointer value is incremented by one; the second recording unit comprises a read pointer, and the value of the read pointer is increased by one under the condition that the data transceiving engine sends one byte to the universal asynchronous receiver/transmitter; and the firmware write operation control unit controls the firmware to execute the data write operation to the data transceiving engine according to the read pointer value and the write pointer value.
In a possible implementation manner, the firmware write operation control unit includes a status register, and when the write pointer makes one more turn than the read pointer, and the read pointer value is equal to the write pointer value, the status in the status register is set to a first status, where the first status is used to indicate that the data transceiving engine is in a write-full state, and when the pointer re-points to the first storage unit in the internal cache, the status indicates that the pointer makes one turn, and the pointer includes the write pointer and the read pointer.
In one possible implementation, the firmware is configured to: and acquiring the state in the state register, and suspending the writing of data into the data transceiving engine under the condition that the state in the state register is the first state.
In a possible implementation manner, the data transceiving engine includes a free capacity statistical logic module, configured to perform real-time statistics on a free capacity of an internal cache in the data transceiving engine.
In one possible implementation, in response to a free capacity of an internal cache in a data transceiving engine being greater than or equal to a data amount of the target data, the firmware writes the target data to the data transceiving engine at one time, the data amount of the target data being greater than or equal to one byte.
In a possible implementation manner, in the case that the free capacity is smaller than the data amount of the target data, the partial data in the target data is written to the free capacity at one time.
According to an aspect of the present disclosure, a serial data communication method is provided, which is applied to a serial data communication system, where the system includes firmware, a data transceiving engine, and a universal asynchronous receiver/transmitter, and the method includes: the firmware writes target data into an internal cache of the data transceiving engine; the data transceiving engine sends the data in the internal cache to a universal asynchronous receiver-transmitter; the universal asynchronous transceiver transmits the received data to be transmitted to a receiving end according to a serial port communication protocol, and transmits an interrupt signal to the data receiving and transmitting engine after transmitting the data to the receiving end, wherein the interrupt signal is used for indicating the data receiving and transmitting engine to transmit the data to the universal asynchronous transceiver.
In one possible implementation, the data transceiving engine includes: a first recording unit, a second recording unit, and a firmware write operation control unit; the first recording unit is used for recording a first data volume of target data written into an internal cache of the data transceiving engine by the firmware; the second recording unit is used for recording a second data volume of the data sent to the universal asynchronous receiver-transmitter by the data receiving-transmitting engine; and the firmware writing operation control unit controls the firmware to write data to the data transceiving engine according to the first data volume and the second data volume.
In a possible implementation manner, the first recording unit includes a write pointer, and in a case where the firmware writes one byte of data into an internal buffer of the data transceiving engine, the write pointer value is incremented by one; the second recording unit comprises a read pointer, and the value of the read pointer is increased by one under the condition that the data transceiving engine sends one byte to the universal asynchronous receiver/transmitter; and the firmware writing operation control unit controls the firmware to write data to the data transceiving engine according to the reading pointer value and the writing pointer value.
In a possible implementation manner, the firmware write operation control unit includes a status register, and when the write pointer makes one more turn than the read pointer and the read pointer value is equal to the write pointer value, the status in the status register is set to a first status, where the first status indicates that the data transceiving engine is in a write-full status, and when the pointer redirects to the first storage unit in the internal cache, the status indicates that the pointer makes one turn, and the pointer includes the write pointer and the read pointer.
In a possible implementation manner, the firmware acquires the state in the state register, and suspends the writing of the data into the data transceiving engine when the state in the state register is the first state.
In a possible implementation manner, the data transceiving engine includes a free capacity statistical logic module, and the free capacity statistical logic module performs real-time statistics on the free capacity of an internal cache in the data transceiving engine.
In one possible implementation, in response to a free capacity of an internal cache in a data transceiving engine being greater than or equal to a data amount of the target data, the firmware writes the target data to the data transceiving engine at one time, the data amount of the target data being greater than or equal to one byte.
In one possible implementation, in a case where the free capacity is smaller than the data amount of the target data, the firmware writes part of the data in the target data to the free capacity at a time.
According to an aspect of the present disclosure, there is provided an electronic device including: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to invoke the memory-stored instructions to operate the system described above.
According to an aspect of the disclosure, there is provided a computer readable storage medium having stored thereon computer program instructions which, when executed by a processor, operate the above system.
In an embodiment of the present disclosure, a data communication system includes firmware, a data transceiving engine, and a universal asynchronous receiver/transmitter, wherein: the firmware is used for writing target data into an internal cache of the data transceiving engine; the data transceiving engine is used for sending the data in the internal cache to the universal asynchronous receiver-transmitter; the universal asynchronous receiver/transmitter is used for transmitting the received data to be transmitted to a receiving end according to a serial port communication protocol, and transmitting an interrupt signal to the data receiving/transmitting engine after transmitting the data to the receiving end, wherein the interrupt signal is used for indicating the data receiving/transmitting engine to transmit the data to the universal asynchronous receiver/transmitter. Therefore, after the target data is written into the internal cache of the data transceiving engine, the data transceiving engine can execute the work of sending the data and waiting for interruption, the firmware does not need to wait for the interruption of the Tx of the universal asynchronous receiver/transmitter (UART) any more, and the firmware is not delayed from executing other tasks, so that the operating efficiency of the firmware is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the disclosure.
Fig. 1 shows a frame diagram of a data serial communication system in a development board.
Fig. 2 shows a frame diagram of a serial data communication system according to an embodiment of the present disclosure.
Fig. 3 shows a frame diagram of another data serial communication system according to an embodiment of the present disclosure.
Fig. 4 shows a frame diagram of another data serial communication system according to an embodiment of the present disclosure.
Fig. 5 shows a flowchart of a serial data communication method according to an embodiment of the present disclosure.
Fig. 6 shows a block diagram of an electronic device of an embodiment of the disclosure.
Fig. 7 shows a block diagram of an electronic device of an embodiment of the disclosure.
Detailed Description
Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
The term "and/or" herein is merely an association describing an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of a, B, and C, and may mean including any one or more elements selected from the group consisting of a, B, and C.
Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the subject matter of the present disclosure.
In the related art, the firmware has a long waiting time and low efficiency when sending data to the computer end through the UART. Based on this, in order to improve the operating efficiency of the firmware, a new data communication system is proposed to reduce the print interruption waiting time.
Fig. 2 shows a frame diagram of a serial data communication system according to an embodiment of the present disclosure, and as shown in fig. 2, the serial data communication system includes: firmware 101, a data transceiving engine 102, and a universal asynchronous receiver/transmitter 103, wherein: the firmware 101 is configured to write target data into an internal cache of the data transceiver engine 102; the data transceiving engine 102 is configured to send the data in the internal cache to the universal asynchronous receiver/transmitter 103; the universal asynchronous receiver/transmitter 103 is configured to transmit received data to be transmitted to a receiving end according to a serial port communication protocol, and send an interrupt signal to the data receiving/transmitting engine after sending the data to the receiving end, where the interrupt signal is used to instruct the data receiving/transmitting engine to send the data to the universal asynchronous receiver/transmitter.
The target data is data which is to be sent to the computer end by the firmware through the UART, and can be software state information and/or hardware state information in a development board where the firmware is located, and the information comprises some information which needs to be checked by a developer in the development process, so that the developer can develop and debug the functions of the development board conveniently.
The data transceiving engine is used for temporarily storing the target data written by the firmware into the internal cache and then transmitting the target data to the universal asynchronous receiver/transmitter, the capacity of the internal cache of the data transceiving engine is more than one byte, namely the internal cache can store the data more than one byte, therefore, the firmware can write the target data more than one byte into the internal cache of the data transceiving engine, the data transceiving engine executes the work of transmitting the data and waiting for interruption, the firmware does not need to spend time for waiting for Tx interruption of the universal asynchronous receiver/transmitter, and other tasks executed by the firmware are not delayed, so that the operating efficiency of the firmware is improved.
After receiving the data sent by the data receiving and sending engine, the universal asynchronous receiver-transmitter sends the data to the computer receiving end according to the serial port communication protocol, namely, sends the data to the computer receiving end byte by byte, and after sending the data of one byte each time, the universal asynchronous receiver-transmitter can send an interrupt signal to the data receiving and sending engine.
After receiving the interrupt signal, the data transceiver engine can send data to the universal asynchronous transceiver, and the data transceiver engine can send at least one byte of data to the asynchronous transceiver each time.
In an embodiment of the present disclosure, a data communication system includes firmware, a data transceiving engine, and a universal asynchronous receiver/transmitter, wherein: the firmware is used for writing target data into an internal cache of the data transceiving engine; the data transceiving engine is used for sending the data in the internal cache to the universal asynchronous receiver-transmitter; the universal asynchronous transceiver is used for transmitting received data to be transmitted to a receiving end according to a serial port communication protocol, and transmitting an interrupt signal to the data receiving and transmitting engine after transmitting the data to the receiving end, wherein the interrupt signal is used for indicating the data receiving and transmitting engine to transmit the data to the universal asynchronous transceiver. Therefore, after the target data is written into the internal cache of the data transceiving engine, the data transceiving engine can execute the work of sending the data and waiting for interruption, the firmware does not need to wait for the interruption of the Tx of the universal asynchronous receiver/transmitter (UART) any more, and the firmware is not delayed from executing other tasks, so that the operating efficiency of the firmware is improved.
In a possible implementation manner, the data transceiver engine is a digital logic circuit disposed on a chip, and the data transceiver engine and the universal asynchronous receiver/transmitter are disposed in the same chip.
In this implementation, the data transceiving engine and the UART are disposed in the same chip, that is, located in the same hardware, so that data transmission between the data transceiving engine and the UART is data transmission between hardware and hardware, interrupt processing of the UART is completely performed in hardware, and efficiency of data transmission and processing is higher than that of data transmission between software (firmware) and hardware (UART).
That is to say, in the hardware design of the chip, a unit may be opened up in the hardware, the data transceiver engine is used as a data transceiver engine, the data transceiver engine has a buffer, and the capacity of the buffer may be flexibly configured, for example, the capacity of the buffer may be configured to be 64bytes to 8kbytes, and the configuration interval comprehensively considers the data transmission capability of the UART and the size of the data amount that needs to be transmitted in the embedded software development process, so that the basic data transmission of the UART may be ensured, and the resource waste caused by occupying too large space may not be caused.
In one possible implementation, the universal asynchronous receiver/transmitter includes a transmit module, the transmit module including a buffer; the data transceiving engine is used for writing the data in the internal cache into a buffer area of a sending module of the universal asynchronous receiver-transmitter; and the sending module is used for transmitting the data of the buffer area of the sending module to the receiving end bit by bit according to the serial port communication protocol.
The UART comprises a transmitting module TX, the transmitting module TX comprises a buffer area, when a data transceiving engine transmits data in an internal buffer to the UART, the data transceiving engine writes the data into the buffer area of the transmitting module of the UART, and then the transmitting module transmits the data in the internal buffer area to a receiving end bit by bit according to a serial port communication protocol.
Please refer to fig. 3, which is a block diagram of another serial data communication system according to an embodiment of the present disclosure. The UART 103 may be located on an 8051 chip in this implementation manner, and the data transceiver engine 102 writes data into the transmit module buffer 104 in the UART 103, and the transmit module buffer 104 then transmits the data to the UART tool on the computer side bit by bit according to the serial communication protocol.
In one possible implementation, the data transceiving engine comprises: a first recording unit, a second recording unit, and a firmware write operation control unit: the first recording unit is used for recording a first data volume of target data written into an internal cache of the data transceiving engine by firmware; the second recording unit is used for recording a second data volume of the data sent to the universal asynchronous receiver/transmitter by the data receiving/transmitting engine; and the firmware write operation control unit is used for controlling the firmware to write data to the data transceiving engine according to the first data volume and the second data volume.
In this implementation, by recording a first data amount of the target data written by the firmware into the internal buffer of the data transceiving engine and a second data amount of the data transmitted by the data transceiving engine to the universal asynchronous receiver/transmitter, since the transmitted data is deleted after the data transceiving engine transmits the data to the universal asynchronous receiver/transmitter, the second data amount may be used to indicate the writable capacity after deleting the transmitted data, and the first data amount indicates the occupied capacity after writing the data. Then, based on the first data amount and the second data amount, it can be determined whether the data transceiving engine is full of data, so as to accurately and timely control the execution of the data writing operation of the firmware to the data transceiving engine.
Please refer to fig. 4, which is a block diagram of another serial data communication system according to an embodiment of the present disclosure. In this implementation, the data transceiving engine 102 can display the storage status of whether it is full to the firmware 101 in order to control whether the firmware 101 performs a write data operation to the data transceiving engine.
Illustratively, the capacity of the data transceiving engine is known, and when the difference between the first data volume and the second data volume is smaller than the capacity of the data transceiving engine, it indicates that the writable free capacity still exists in the data transceiving engine, i.e. the not-full state; when the difference between the first data amount and the second data amount is equal to the capacity of the data transceiving engine, it indicates that the data transceiving engine is full, i.e., a full state. Under the condition that the data transceiving engine is in a full-written state, the firmware writing operation control unit can suspend the writing operation of the firmware to the data transceiving engine; the firmware write operation control unit may allow a write operation of the firmware to the data transceiving engine in a case where the data transceiving engine is in the not-full state.
In another example, the specific implementation of the first amount of data may be a value of a write pointer and the specific implementation of the second amount of data may be a value of a read pointer. In this implementation, the first recording unit includes a write pointer, and the write pointer value is incremented by one when the firmware writes one byte of data into the internal cache of the data transceiving engine; the second recording unit is used for adding one to the value of the read pointer under the condition that the data transceiving engine sends one byte to the universal asynchronous receiver/transmitter every time; and the firmware writing operation control unit controls the firmware to write data to the data transceiving engine according to the reading pointer value and the writing pointer value.
In the implementation mode, the data volume stored in the internal cache of the data transceiving engine is recorded in the form of a write pointer, and the data volume read out of the internal cache of the data transceiving engine is recorded in the form of a read pointer, so that whether the internal cache of the data transceiving engine is full can be determined according to the write pointer value and the read pointer value, and whether the firmware can write data into the internal cache of the data transceiving engine can be accurately and timely controlled.
In a possible implementation manner, the firmware write operation control unit includes a status register, and when the write pointer makes one more turn than the read pointer and the read pointer value is equal to the write pointer value, the status in the status register is set to a first status, where the first status is used to indicate that the data transceiving engine is in a write-full status, and when the pointer redirects to the first storage unit in the internal cache, the status indicates that the pointer makes one turn, and the pointer includes the write pointer and the read pointer. The internal buffer of the data transceiving engine comprises a plurality of memory cells, the pointer points to the next memory cell to be read/written, and after the data in the internal buffer is read out, new data can be written in a circulating manner, so that when the pointer points to the first memory cell in the internal buffer again, the pointer goes through one circle. Then, when the write pointer makes one more turn than the read pointer, and when the read pointer value is equal to the write pointer value, that is, the storage location pointed by the write pointer and the storage location pointed by the read pointer are the same storage location, since the storage location pointed by the write pointer is the next location to be written with data and the storage location is the location to be read with data by the read pointer, obviously, the location is occupied and new characters cannot be written.
That is, when the write pointer makes one more turn than the read pointer, and the read pointer value is equal to the write pointer value, it indicates that the receipt transceiving engine is in a full write state in the internal buffer, so that the state in the status register may be set to the first state representing the full write state at this time, and specifically, the flag bit representing the first state may be assigned to 1, that is, the full write state is represented by the number 1.
In one possible implementation, the state in the status register is set to a second state in other cases, the second state indicating that the data transceiving engine is in a not full state.
Other cases here are in particular: in case the read pointer value is not equal to the write pointer value, or in case the write pointer and the read pointer are in the same revolution and the write pointer and the read pointer are the same. In these cases, an underfill status is indicated in the internal cache of the data transceiving engine. Specifically, when the write pointer and the read pointer are in the same circle, the condition that the write pointer value is the same as the read pointer value indicates that the internal cache of the data transceiving engine is empty; and under the condition that the read pointer value is not equal to the write pointer value, whether the write pointer and the read pointer are positioned in the same circle or not indicates that the data transceiving engine is in a non-full state. Thus, at this point the state in the status register may be set to a second state that characterizes the not-full state, and the specific value of the second state may be 0, i.e. the write-full state is represented by the number 0.
Therefore, whether the data transceiving engine is in a full writing state or a non-full writing state can be determined only according to the write pointer value and the read pointer value, the efficiency of determining the state of the data transceiving engine can be improved, and whether the firmware can write data into the data transceiving engine or not can be accurately and timely controlled.
In one possible implementation, the firmware is configured to: and acquiring the state in the state register, and suspending the writing of data into the data transceiving engine under the condition that the state in the state register is the first state. In one possible implementation, in the case that the state in the state register is the second state, data is written to the data transceiving engine.
The firmware write operation control unit indicates whether the data transceiving engine is full through the status register, and then the firmware determines whether the data transceiving engine is full through acquiring the status in the status register, and further determines whether to write data into the data transceiving engine.
Under the condition that the state in the state register is the first state, indicating that the data transceiving engine is in a full state, and suspending the writing of data into the data transceiving engine; and when the state in the state register is in the second state, indicating that the second buffer unit is in the non-full state, and writing data into the data transceiving engine.
In one possible implementation manner, in response to that the free capacity of the internal cache storage space in the data transceiving engine is greater than or equal to the data amount of the target data, the firmware writes the target data into the data transceiving engine at one time, wherein the data amount of the target data is greater than or equal to one byte.
In the case where the data amount of the target data is equal to one byte, the firmware writes the data byte by byte into the data transceiving engine. Since the firmware executes the instructions of the CPU, which is fast and the processing frequency is in the mega range, the firmware can write the target data into the data transceiving engine in a short time. However, the processing speed of the UART is slow, so that the time for the firmware to write the target data into the data transceiving engine can be ignored, and then the data transceiving engine and the UART can perform data transmission processing, and the firmware can perform other tasks.
In the case where the data amount of the target data is larger than one byte, the firmware can write data larger than one byte at a time, so that the number of times of performing the write operation can be reduced compared to character-by-character writing, and the speed of writing data can be further improved.
In a possible implementation manner, the data transceiving engine includes a free capacity statistical logic module, configured to perform real-time statistics on the free capacity of the storage space in the data transceiving engine.
In a possible implementation manner, in a case that the free capacity is smaller than the data amount of the target data, the partial data in the target data is written to the free capacity at one time.
The free capacity calculation unit may determine from the write pointer value and the read pointer value, and a specific determination process of the free capacity is as follows.
Free volume V in the case of write and read pointers in the same turn 1 Is determined by equation (1).
V 1 =V 0 -(P w -P r ) （1）
Wherein, V 0 For the total capacity of storage space in the data-transceiving engine, P w For writing pointer values, P r Is the read pointer value.
Free volume V in the case of a write pointer in the next turn of the read pointer 1 Is determined by equation (2).
V 1 =V 0 -(V 0 +P w -P r ) （2）
In a possible implementation manner, whether the write pointer has traveled one turn more than the read pointer may be marked by a flag bit, for convenience of description, the flag bit may be called a full-write flag bit, and when the write pointer writes to the maximum position, the full-write flag bit may be set, and at this time, the write pointer may enter the next turn, that is, the write pointer has traveled one turn more than the read pointer; when the read pointer reads the maximum position, the full-written flag bit can be cleared, and at the moment, the read pointer also enters the next circle, namely the write pointer and the read pointer are in the same circle. Then when the full flag is set, the free capacity can be determined by equation (2), and when the full flag is not set, the free capacity can be determined by equation (1).
The determined value of the free capacity can be written into a register, and the firmware can read the value of the free capacity in the register and then judge whether the value is larger than or equal to the data size of the target data, wherein the data size of the target data can be the length of data which is written into an internal cache of the data transceiving engine by default. When the free capacity is larger than or equal to the data amount of the target data, the target data can be written into the free capacity of the data transceiving engine at one time. When the free capacity is smaller than the data amount of the target data, part of the data in the target data is written into the free capacity at one time, preferably, the full free capacity can be written at one time.
In the embodiment of the disclosure, the free capacity of the storage space is counted in real time by adding logic in the data transceiving engine, so that the firmware can only need to query once before writing a plurality of bytes once, and if the free space is enough to write target data, the target data can be written once; and if the free capacity is smaller than the data quantity of the target data, writing partial data in the target data to the full free capacity at one time. Therefore, the firmware can determine the data writing amount into the data transceiving engine conveniently, and the data writing efficiency of the firmware into the data transceiving engine is improved.
It is understood that the above-mentioned system embodiments mentioned in the present disclosure can be combined with each other to form a combined embodiment without departing from the principle logic, which is limited by the space, and the detailed description of the present disclosure is omitted. Those skilled in the art will appreciate that in the above-described methods of the embodiments, the specific order of execution of the elements should be determined by their function and possibly their inherent logic.
In addition, the present disclosure also provides a data serial communication method and an electronic device, which can be used to operate any data serial communication system provided by the present disclosure, and the corresponding technical scheme and description refer to the corresponding record of the system part, which are not described again.
Fig. 5 shows a flowchart of a serial data communication method according to an embodiment of the present disclosure, where the method is applied to a serial data communication system, where the system includes firmware, a data transceiving engine, and a universal asynchronous receiver/transmitter, and as shown in fig. 5, the method includes: in step S51, the firmware writes target data into an internal cache of the data transceiving engine; in step S52, the data transceiving engine sends the data in the internal cache to the universal asynchronous receiver/transmitter; in step S53, the universal asynchronous receiver/transmitter transmits the received data to be transmitted to the receiving end according to the serial port communication protocol, and transmits an interrupt signal to the data receiving/transmitting engine after transmitting the data to the receiving end, where the interrupt signal is used to instruct the data receiving/transmitting engine to transmit the data to the universal asynchronous receiver/transmitter.
In one possible implementation, the data transceiving engine includes: a first recording unit, a second recording unit, and a firmware write operation control unit; the first recording unit is used for recording a first data volume of target data written into an internal cache of the data transceiving engine by the firmware; the second recording unit is used for recording a second data volume of the data sent to the universal asynchronous receiver-transmitter by the data receiving-transmitting engine; and the firmware writing operation control unit controls the firmware to write data to the data transceiving engine according to the first data volume and the second data volume.
In a possible implementation manner, the first recording unit includes a write pointer, and in a case where the firmware writes one byte of data into an internal buffer of the data transceiving engine, the write pointer value is incremented by one; the second recording unit comprises a read pointer, and the value of the read pointer is increased by one under the condition that the data transceiving engine sends one byte to the universal asynchronous receiver/transmitter; and the firmware writing operation control unit controls the firmware to write data to the data transceiving engine according to the reading pointer value and the writing pointer value.
In a possible implementation manner, the firmware write operation control unit includes a status register, and when the write pointer makes one more turn than the read pointer, and the read pointer value is equal to the write pointer value, the status in the status register is set to a first status, where the first status indicates that the data transceiving engine is in a write-full state, and when the pointer re-points to the first storage unit in the internal cache, the status indicates that the pointer makes one turn, and the pointer includes the write pointer and the read pointer.
In a possible implementation manner, the firmware acquires the state in the state register, and suspends the writing of the data into the data transceiving engine when the state in the state register is the first state.
In a possible implementation manner, the data transceiving engine includes a free capacity statistical logic module, and the free capacity statistical logic module performs real-time statistics on the free capacity of an internal cache in the data transceiving engine.
In one possible implementation, in response to a free capacity of an internal cache in a data transceiving engine being greater than or equal to a data amount of the target data, the firmware writes the target data to the data transceiving engine at one time, the data amount of the target data being greater than or equal to one byte.
In one possible implementation, in a case where the free capacity is smaller than the data amount of the target data, the firmware writes part of the data in the target data to the free capacity at a time.
The method has specific technical relevance with the internal structure of the computer system, and can solve the technical problems of how to improve the hardware operation efficiency or the execution effect (including reducing data storage capacity, reducing data transmission capacity, improving hardware processing speed and the like), thereby obtaining the technical effect of improving the internal performance of the computer system according with the natural law.
In some embodiments, specific implementations of the method provided in the embodiments of the present disclosure may refer to the description of the above system embodiment, and for brevity, are not described herein again.
Embodiments of the present disclosure also provide a computer-readable storage medium having stored thereon computer program instructions, which, when executed by a processor, operate the above-mentioned system. The computer readable storage medium may be a volatile or non-volatile computer readable storage medium.
An embodiment of the present disclosure further provides an electronic device, including: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to invoke the memory-stored instructions to operate the system described above.
The electronic device may be provided as a terminal, server, or other form of device.
Fig. 6 illustrates a block diagram of an electronic device 800 of an embodiment of the disclosure. For example, the electronic device 800 may be a User Equipment (UE), a mobile device, a User terminal, a cellular phone, a cordless phone, a Personal Digital Assistant (PDA), a handheld device, a computing device, a vehicle-mounted device, a wearable device, or other terminal device.
Referring to fig. 6, electronic device 800 may include one or more of the following components: a processing component 802, a memory 804, a power component 806, a multimedia component 808, an audio component 810, an input/output interface 812, a sensor component 814, and a communications component 816.
The processing component 802 generally controls overall operation of the electronic device 800, such as operations associated with display, telephone calls, data communications, camera operations, and recording operations. The processing components 802 may include one or more processors 820 to execute instructions to operate all or part of the system described above, such as to schedule or control at least one of firmware, a data transceiver engine, a universal asynchronous receiver/transmitter, or the like. Further, the processing component 802 can include one or more modules that facilitate interaction between the processing component 802 and other components. For example, the processing component 802 can include a multimedia module to facilitate interaction between the multimedia component 808 and the processing component 802.
The memory 804 is configured to store various types of data to support operations at the electronic device 800. Examples of such data include instructions for any application or method operating on the electronic device 800, contact data, phonebook data, messages, pictures, videos, and so forth. The memory 804 may be implemented by any type or combination of volatile or non-volatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disks.
The power supply component 806 provides power to the various components of the electronic device 800. The power components 806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 800.
The multimedia component 808 includes a screen that provides an output interface between the electronic device 800 and a user. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive an input signal from a user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundary of a touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 808 includes a front facing camera and/or a rear facing camera. The front camera and/or the rear camera may receive external multimedia data when the electronic device 800 is in an operation mode, such as a photographing mode or a video mode. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.
The audio component 810 is configured to output and/or input audio signals. For example, the audio component 810 includes a Microphone (MIC) configured to receive external audio signals when the electronic device 800 is in an operational mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signal may further be stored in the memory 804 or transmitted via the communication component 816. In some embodiments, audio component 810 also includes a speaker for outputting audio signals.
The input/output interface 812 provides an interface between the processing component 802 and peripheral interface modules, which may be keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to: a home button, a volume button, a start button, and a lock button.
The sensor assembly 814 includes one or more sensors for providing various aspects of state assessment for the electronic device 800. For example, the sensor assembly 814 may detect an open/closed state of the electronic device 800, the relative positioning of components, such as a display and keypad of the electronic device 800, the sensor assembly 814 may also detect a change in the position of the electronic device 800 or a component of the electronic device 800, the presence or absence of user contact with the electronic device 800, orientation or acceleration/deceleration of the electronic device 800, and a change in the temperature of the electronic device 800. Sensor assembly 814 may include a proximity sensor configured to detect the presence of a nearby object without any physical contact. The sensor assembly 814 may also include a light sensor, such as a Complementary Metal Oxide Semiconductor (CMOS) or Charge Coupled Device (CCD) image sensor, for use in imaging applications. In some embodiments, the sensor assembly 814 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.
The communication component 816 is configured to facilitate wired or wireless communication between the electronic device 800 and other devices. The electronic device 800 may access a wireless network based on a communication standard, such as a wireless network (Wi-Fi), a second generation mobile communication technology (2G), a third generation mobile communication technology (3G), a fourth generation mobile communication technology (4G), a long term evolution of universal mobile communication technology (LTE), a fifth generation mobile communication technology (5G), or a combination thereof. In an exemplary embodiment, the communication component 816 receives a broadcast signal or broadcast related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 816 further includes a Near Field Communication (NFC) module to facilitate short-range communications. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, ultra Wideband (UWB) technology, bluetooth (BT) technology, and other technologies.
In an exemplary embodiment, the electronic device 800 may be implemented by one or more Application Specific Integrated Circuits (ASICs), digital Signal Processors (DSPs), digital Signal Processing Devices (DSPDs), programmable Logic Devices (PLDs), field Programmable Gate Arrays (FPGAs), controllers, micro-controllers, microprocessors or other electronic components for performing the above-described methods.
In an exemplary embodiment, a non-transitory computer-readable storage medium, such as the memory 804, is also provided that includes computer program instructions executable by the processor 820 of the electronic device 800 to perform the above-described methods.
The disclosure relates to the field of augmented reality, and aims to detect or identify relevant features, states and attributes of a target object by means of various visual correlation algorithms by acquiring image information of the target object in a real environment, so as to obtain an AR effect combining virtual and reality matched with specific applications. For example, the target object may relate to a face, a limb, a gesture, an action, etc. associated with a human body, or an identifier, a marker, or a sand table, a display area, a display item, etc. associated with an object, or a venue. The vision-related algorithms may involve visual localization, SLAM, three-dimensional reconstruction, image registration, background segmentation, key point extraction and tracking of objects, pose or depth detection of objects, and the like. The specific application can not only relate to interactive scenes such as navigation, explanation, reconstruction, virtual effect superposition display and the like related to real scenes or articles, but also relate to special effect treatment related to people, such as interactive scenes such as makeup beautification, limb beautification, special effect display, virtual model display and the like. The detection or identification processing of relevant characteristics, states and attributes of the target object can be realized through the convolutional neural network. The convolutional neural network is a network model obtained by performing model training based on a deep learning framework.
Fig. 7 illustrates a block diagram of an electronic device 1900 of an embodiment of the disclosure. For example, the electronic device 1900 may be provided as a server or terminal device. Referring to fig. 7, electronic device 1900 includes a processing component 1922 further including one or more processors and memory resources, represented by memory 1932, for storing instructions, e.g., applications, executable by processing component 1922. The application programs stored in memory 1932 may include one or more modules that each correspond to a set of instructions. Further, the processing component 1922 is configured to execute instructions to run all or part of the system described above, such as scheduling or controlling at least one of firmware, a data transceiver engine, a universal asynchronous receiver/transmitter.
The electronic device 1900 may further include a power component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input/output interface 1958. The electronic device 1900 may operate based on an operating system, such as the Microsoft Server operating system (Windows Server), stored in the memory 1932 TM ) Apple Inc. of the present application based on the graphic user interface operating System (Mac OS X) TM ) Multi-user, multi-process computer operating system (Unix) TM ) Free and open sourcesUnix-like operating system of code (Linux) TM ) Open native code Unix-like operating System (FreeBSD) TM ) Or the like.
In an exemplary embodiment, a non-transitory computer readable storage medium, such as the memory 1932, is also provided that includes computer program instructions executable by the processing component 1922 of the electronic device 1900 to perform the above-described methods.
The present disclosure may be systems, methods, and/or computer program products. The computer program product may include a computer-readable storage medium having computer-readable program instructions embodied thereon for causing a processor to implement various aspects of the present disclosure.
The computer readable storage medium may be a tangible device that can hold and store the instructions for use by the instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic memory device, a magnetic memory device, an optical memory device, an electromagnetic memory device, a semiconductor memory device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a Static Random Access Memory (SRAM), a portable compact disc read-only memory (CD-ROM), a Digital Versatile Disc (DVD), a memory stick, a floppy disk, a mechanical coding device, such as punch cards or in-groove projection structures having instructions stored thereon, and any suitable combination of the foregoing. Computer-readable storage media as used herein is not to be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., optical pulses through a fiber optic cable), or electrical signals transmitted through electrical wires.
The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to a respective computing/processing device, or to an external computer or external storage device over a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. The network adapter card or network interface in each computing/processing device receives computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in the respective computing/processing device.
The computer program instructions for carrying out operations of the present disclosure may be assembler instructions, instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, the electronic circuitry that can execute the computer-readable program instructions implements aspects of the present disclosure by utilizing the state information of the computer-readable program instructions to personalize the electronic circuitry, such as a programmable logic circuit, a Field Programmable Gate Array (FPGA), or a Programmable Logic Array (PLA).
Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, systems, and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.
These computer-readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable medium storing the instructions comprises an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.
The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The computer program product may be embodied in hardware, software or a combination thereof. In an alternative embodiment, the computer program product is embodied in a computer storage medium, and in another alternative embodiment, the computer program product is embodied in a Software product, such as a Software Development Kit (SDK) or the like.
The foregoing description of the various embodiments is intended to highlight different aspects of the various embodiments that are the same or similar, which can be referenced with one another and therefore are not repeated herein for brevity.
It will be understood by those of skill in the art that in the above method of the present embodiment, the order of writing the steps does not imply a strict order of execution and does not impose any limitations on the implementation, as the order of execution of the steps should be determined by their function and possibly inherent logic.
If the technical scheme of the application relates to personal information, a product applying the technical scheme of the application clearly informs personal information processing rules before processing the personal information, and obtains personal independent consent. If the technical scheme of the application relates to sensitive personal information, a product applying the technical scheme of the application obtains individual consent before processing the sensitive personal information, and simultaneously meets the requirement of 'express consent'. For example, at a personal information collection device such as a camera, a clear and significant identifier is set to inform that the personal information collection range is entered, the personal information is collected, and if the person voluntarily enters the collection range, the person is considered as agreeing to collect the personal information; or on the device for processing the personal information, under the condition of informing the personal information processing rule by using obvious identification/information, obtaining personal authorization in the modes of pop-up window information or asking the person to upload personal information thereof and the like; the personal information processing rule may include information such as a personal information processor, a personal information processing purpose, a processing method, and a type of personal information to be processed.
Having described embodiments of the present disclosure, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or improvements to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (11)
1. A serial data port communication system, said system comprising: firmware, a data transceiving engine, and a universal asynchronous receiver transmitter, wherein:
the firmware is used for writing target data into an internal cache of the data transceiving engine;
the data transceiving engine is used for sending the data in the internal cache to the universal asynchronous receiver-transmitter;
the universal asynchronous receiver/transmitter is used for transmitting the received data to be transmitted to a receiving end according to a serial port communication protocol, and transmitting an interrupt signal to the data receiving/transmitting engine after transmitting the data to the receiving end, wherein the interrupt signal is used for indicating the data receiving/transmitting engine to transmit the data to the universal asynchronous receiver/transmitter.
2. The system of claim 1, wherein the data transceiver engine is a digital logic circuit disposed on a chip, and wherein the data transceiver engine and the UART are disposed in the same chip.
3. The system of claim 1, wherein the data transceiving engine comprises: a first recording unit, a second recording unit, and a firmware write operation control unit;
the first recording unit is used for recording a first data volume of target data written into an internal cache of the data transceiving engine by the firmware;
the second recording unit is used for recording a second data volume of the data sent to the universal asynchronous receiver-transmitter by the data receiving-transmitting engine;
and the firmware write operation control unit is used for controlling the firmware to write data to the data transceiving engine according to the first data volume and the second data volume.
4. The system of claim 3,
the first recording unit comprises a write pointer, and the value of the write pointer is increased by one under the condition that the firmware writes one byte of data into the internal cache of the data transceiving engine;
the second recording unit comprises a read pointer, and the value of the read pointer is increased by one under the condition that the data transceiving engine sends one byte to the universal asynchronous receiver/transmitter;
and the firmware writing operation control unit controls the firmware to write data to the data transceiving engine according to the reading pointer value and the writing pointer value.
5. The system of claim 4, wherein the firmware write control unit comprises a status register, and wherein if the write pointer has a value equal to the write pointer value when the write pointer has a number of turns greater than the read pointer, the status register is set to a first status indicating that the data transceiver engine is in a write-full status, and wherein if the pointer is redirected to the first storage location in the internal cache, the status register indicates that the pointer has made one turn, and wherein the pointer comprises a write pointer and a read pointer.
6. The system of claim 5, wherein the firmware is to:
and acquiring the state in the state register, and suspending the writing of data into the data transceiving engine under the condition that the state in the state register is the first state.
7. The system of claim 1, wherein the data transceiver engine comprises a free capacity statistics logic module configured to perform real-time statistics on the free capacity of the internal buffer of the data transceiver engine.
8. The system of claim 7, wherein the firmware writes target data to the data transceiver engine at one time in response to a free capacity of an internal cache in the data transceiver engine being greater than or equal to a data amount of the target data, the data amount of the target data being greater than or equal to one byte.
9. The system of claim 7, wherein the firmware writes a portion of the target data to the free capacity at a time if the free capacity is less than the amount of the target data.
10. A data serial port communication method is applied to a data serial port communication system, the system comprises firmware, a data transceiving engine and a universal asynchronous receiver/transmitter, and the method comprises the following steps:
the firmware writes target data into an internal cache of the data transceiving engine;
the data transceiving engine sends the data in the internal cache to a universal asynchronous receiver-transmitter;
the universal asynchronous transceiver transmits the received data to be transmitted to a receiving end according to a serial port communication protocol, and transmits an interrupt signal to the data receiving and transmitting engine after transmitting the data to the receiving end, wherein the interrupt signal is used for indicating the data receiving and transmitting engine to transmit the data to the universal asynchronous transceiver.
11. An electronic device, comprising:
a processor;
a memory for storing processor-executable instructions;
wherein the processor is configured to invoke the memory-stored instructions to execute the system of any one of claims 1-9.
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