CN115658446A - WDT simulation verification method, device, equipment and medium - Google Patents
WDT simulation verification method, device, equipment and medium Download PDFInfo
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Abstract
The application discloses a WDT simulation verification method, a WDT simulation verification device, WDT simulation verification equipment and WDT simulation verification media, which relate to the technical field of computers and comprise the following steps: after the simulation verification operation is started, triggering a random test event to control a test component to select a random test sequence and sending a corresponding transaction message to a driver so as to send the transaction message to the WDT through the driver; starting timing operation after the control module detects that the WDT starts to work, monitoring an output signal of the WDT after the preset timeout time is reached, and judging whether the output signal meets a first preset condition or not; if so, recording the current test coverage rate, and judging whether the current test coverage rate meets a second preset condition; and if not, sending a transaction completion mark to the test component to re-trigger the random test event to send the next transaction message until the current test coverage rate meets a second preset condition so as to complete the simulation verification operation. The simulation process can be controlled, the coverage rate can be quickly converged, and the verification efficiency is improved.
Description
Technical Field
The invention relates to the technical field of computers, in particular to a WDT simulation verification method, a WDT simulation verification device, WDT simulation verification equipment and WDT simulation verification media.
Background
The Watchdog Timer (WDT) is used to prevent program dead cycles. The watchdog is actually a counter, and typically gives the watchdog a number, called the feed dog, which starts counting after the program starts running. If the program runs normally, the CPU sends an instruction to set the watchdog to zero after a period of time, and counting is restarted. If the watchdog counter is incremented to the set value, the program is deemed to be not operating properly, and the system is forced to reset. Depending on the register configuration, the watchdog may generate an interrupt signal or a reset signal when a timeout or a pre-timeout occurs, and the polarity and pulse width of the reset signal may also vary according to the configuration. In addition, the time to generate the interrupt signal and the reset signal may vary due to the change in the watchdog count. Therefore, the difficulty in verifying the WDT is to ensure functional coverage under various configuration conditions and to accurately determine whether the output signal in each functional mode is correct.
In summary, how to verify the WDT to achieve fast convergence of coverage and improve verification efficiency is a problem to be solved at present.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a method, an apparatus, a device and a medium for verifying simulation of WDT, which can verify WDT to achieve fast convergence of coverage and improve verification efficiency. The specific scheme is as follows:
in a first aspect, the present application discloses a WDT simulation verification method, comprising:
after the simulation verification operation is started, triggering a random test event to control a test component to select a random test sequence, starting the random test sequence and sending a corresponding transaction message to a driver so as to send the transaction message to a WDT (wireless data transmission) through the driver;
starting timing operation after detecting that the WDT starts to work through a control module, monitoring an output signal of the WDT after reaching preset timeout time specified by the timing operation, and judging whether the output signal meets a first preset condition;
if the first preset condition is met, recording the current test coverage rate, and judging whether the current test coverage rate meets a second preset condition;
if the second preset condition is not met, sending a transaction completion mark to the test component through the control module to jump to the step of triggering the random test event to control the test component to select the random test sequence again so as to send the next transaction message until the current test coverage rate meets the second preset condition, and then completing the simulation verification operation.
Optionally, after the starting the random test sequence and sending the corresponding transaction message to the driver, the method further includes:
after detecting that the transaction message is sent completely, a pause event is triggered to control the test component to select a pause test sequence to stop sending the transaction message.
Optionally, the WDT simulation verification method further includes:
configuration functions corresponding to different bus protocols are predetermined, and test sequences corresponding to the configuration functions are saved in a test sequence library in the test component.
Optionally, after recording the current test coverage, the method further includes:
storing the current coverage test rate and corresponding transaction configuration data into a configuration database;
correspondingly, the sending, by the control module, the transaction completion flag to the test component to jump back to the step of triggering the random test event to control the test component to select the random test sequence, so as to send the next transaction message, until the current test coverage meets the second preset condition, further including:
if the current test coverage rate is monitored not to change within a preset unit time, traversing the configuration database through the control module to determine an uncovered target configuration function;
and controlling the test component to select a directional test sequence based on the target configuration function, and starting the directional test sequence to send the next transaction message.
Optionally, the sending, by the control module, the transaction completion flag to the test component to jump to the step of triggering the random test event to control the test component to select the random test sequence, so as to send the next transaction message, until the current test coverage meets the second preset condition, further includes:
if it is detected that all test sequences in the test sequence library have been sent, and the current test coverage does not meet the second preset condition, adding a new target oriented test sequence in the test sequence library based on the current coverage test coverage and the transaction configuration data stored in the configuration database;
and controlling the test component to select the target oriented test sequence and starting the target oriented test sequence to send the next transaction message.
Optionally, the sending, by the driver, the transaction message to the WDT further includes:
acquiring configuration data in a register through the control module, and determining a currently tested configuration function, and an input value of a WDT (power distribution unit) corresponding to the configuration function, and polarity and duration of an output signal according to the configuration data;
constructing the first preset condition based on an input value of the WDT, a polarity and a duration of the output signal.
Optionally, after determining whether the output signal meets a first preset condition, the method further includes:
if the first preset condition is not met, calling a preset ending function through the control module to end the simulation verification operation.
In a second aspect, the present application discloses a WDT emulation verification apparatus, comprising:
the random test module is used for triggering a random test event to control a test component to select a random test sequence after starting the simulation verification operation, starting the random test sequence and sending a corresponding transaction message to a driver so as to send the transaction message to a WDT (wireless data transmission) through the driver;
the output signal monitoring module is used for starting timing operation after detecting that the WDT starts to work through the control module, monitoring an output signal of the WDT after a preset timeout time specified by the timing operation is reached, and judging whether the output signal meets a first preset condition or not;
the coverage rate judging module is used for recording the current test coverage rate if the first preset condition is met, and judging whether the current test coverage rate meets a second preset condition or not;
and the repeated testing module is used for sending a transaction completion mark to the testing component through the control module to jump to the step of triggering the random testing event again to control the testing component to select the random testing sequence if the second preset condition is not met, so as to send the next transaction message until the current testing coverage rate meets the second preset condition, and then completing the simulation verification operation.
In a third aspect, the present application discloses an electronic device, comprising:
a memory for storing a computer program;
a processor for executing the computer program to implement the steps of the WDT emulation verification method disclosed in the foregoing.
In a fourth aspect, the present application discloses a computer readable storage medium for storing a computer program; wherein the computer program when executed by a processor implements the steps of the WDT simulation verification method disclosed above.
As can be seen, after the simulation verification operation is started, a random test event is triggered to control the test component to select a random test sequence, and the random test sequence is started to send a corresponding transaction message to the driver, so that the transaction message is sent to the WDT through the driver; starting timing operation after detecting that the WDT starts to work through a control module, monitoring an output signal of the WDT after reaching preset timeout time specified by the timing operation, and judging whether the output signal meets a first preset condition; if the first preset condition is met, recording the current test coverage rate, and judging whether the current test coverage rate meets a second preset condition; if the second preset condition is not met, sending a transaction completion mark to the test component through the control module to jump to the step of triggering the random test event to control the test component to select the random test sequence again so as to send a next transaction message until the current test coverage rate meets the second preset condition, and then completing the simulation verification operation. Therefore, the control module in the application comprises a timing function, and can acquire the output signal of the WDT after the preset timeout time specified by the timing operation is reached, and whether the output signal meets the first preset condition needs to be judged. Only when the output signal meets the first preset condition and the current coverage test rate does not meet the second preset condition, the control module controls the test assembly to realize the sending of the next transaction message, so that the simulation process can be dynamically controlled, the simulation time is saved, and the efficiency is improved. In addition, the current coverage test rate meeting the second preset condition is used as a simulation finishing condition to realize the rapid convergence of the coverage rate, so that the verification efficiency is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a flow chart of a WDT simulation verification method disclosed herein;
FIG. 2 is a schematic illustration of a particular verification platform disclosed herein;
FIG. 3 is a flow chart of a particular WDT simulation verification method disclosed herein;
FIG. 4 is a schematic diagram of an exemplary WDT simulation verification process disclosed herein;
FIG. 5 is a schematic diagram of a WDT emulation verification apparatus according to the present disclosure;
fig. 6 is a block diagram of an electronic device disclosed in the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Currently, according to different register configurations, the watchdog may generate an interrupt signal or a reset signal when a timeout occurs or a pre-timeout occurs, and the polarity and pulse width of the reset signal may also be different according to the configuration. In addition, the time to generate the interrupt signal and the reset signal may vary due to the change in the watchdog count. Therefore, the difficulty of verifying the WDT is to ensure the functional coverage under various configuration conditions and to accurately determine whether the output signal in each functional mode is correct. The embodiment of the application discloses a WDT simulation verification method, a WDT simulation verification device, WDT simulation verification equipment and WDT simulation verification media, which can verify WDT to achieve rapid convergence of coverage rate and improve verification efficiency.
Referring to fig. 1, an embodiment of the present application discloses a WDT simulation verification method, including:
step S11: after the simulation verification operation is started, a random test event is triggered to control a test component to select a random test sequence, the random test sequence is started to send a corresponding transaction message to a driver, and the transaction message is sent to the WDT through the driver.
In this embodiment, after the simulation verification operation starts, a random Test event (i.e., event) is triggered to control the Test component Test to select a random Test sequence, and the random Test sequence is started to send a complete transaction message (i.e., transaction) to the driver, so that the transaction message is sent to the WDT through the driver.
It should be noted that the verification platform used in this embodiment may be specifically as shown in fig. 2, the verification platform is provided with a config module on the basis of a conventional UVM component, and by selecting different bus configuration information, the selection of a driver driving timing sequence and an interface signal in an agent is realized, so that the efficiency of building a verification environment component is improved. The verification platform is additionally provided with a control module, the control module comprises a timing function and can automatically judge the time of generating the interrupt and reset signals according to the monitored function information so as to realize comparison of output signals. The Agent and the register control port of the WDT are connected by using an io interface, the io interface comprises all ports of an AMBA (Advanced Microcontroller Bus Architecture) Bus protocol, and the interface can be prevented from being frequently modified, wherein the AMBA Bus protocol is an on-chip connection standard designed for a high-performance embedded Microcontroller. In order to match the data types of different bus protocols, a plurality of groups of components are declared in the agent, corresponding to different bus protocols, and the instantiation of all the components is controlled by the config module. Taking WDT register port controlled by APB (Advanced Peripheral Bus) Bus as an example, in the config module, the is _ active variables of APB driver and APB monitor in agent are set to active mode by config _ db mode, and the related components of other Bus protocols are set to passive mode. In this way, the verification environment is simplified, and the influence of redundant components on the simulation speed is avoided.
Step S12: the method comprises the steps of starting timing operation after detecting that the WDT starts to work through a control module, monitoring an output signal of the WDT after reaching preset timeout time specified by the timing operation, and judging whether the output signal meets a first preset condition or not.
In this embodiment, the control module starts a timing operation after detecting that the WDT starts to operate, and monitors an output signal of the WDT after a preset timeout time specified by the timing operation is reached to determine whether the output signal meets a first preset condition, specifically, whether an interrupt signal and a reset signal are generated, whether the polarity is correct, and whether the pulse width meets a setting.
Step S13: if the first preset condition is met, recording the current test coverage rate, and judging whether the current test coverage rate meets a second preset condition.
In a specific embodiment, if the output signal meets a first preset condition, that is, the result of WDT output is correct, the control module records the current test coverage, and determines whether the current test coverage meets a second preset condition, where the second preset condition is specifically that the current test coverage needs to meet 100%, that is, whether the current test coverage reaches 100%.
In another specific embodiment, after the determining whether the output signal satisfies the first preset condition, the method further includes: if the first preset condition is not met, calling a preset ending function through the control module to end the simulation verification operation. That is, if the output signal does not satisfy the first preset condition, that is, the control module determines that the WDT output result is erroneous, the control module calls the finish function to end the simulation, and prints the current configuration function, so as to facilitate subsequent debugging.
Step S14: if the second preset condition is not met, sending a transaction completion mark to the test component through the control module to jump to the step of triggering the random test event to control the test component to select the random test sequence again so as to send a next transaction message until the current test coverage rate meets the second preset condition, and then completing the simulation verification operation.
In this embodiment, if the current test coverage does not satisfy the second preset condition, that is, does not reach 100%, the control module sends the transaction completion flag to the test component to jump to the step of triggering the random test event again to control the test component to select the random test sequence. That is, if the current test coverage rate does not reach 100%, a transaction completion flag is transmitted to the test component, after the test component receives the transaction completion flag, the random test event is continuously triggered, the random test sequence is controlled to send the next transaction message until the current test coverage rate after multiple cycles meets a second preset condition, and then the simulation verification operation is completed. That is, the control module will send out the simulation ending mark to the test component, and the test component will stop sending the transaction message, and the simulation is ended.
As can be seen, after the simulation verification operation is started, a random test event is triggered to control the test component to select a random test sequence, and the random test sequence is started to send a corresponding transaction message to the driver, so that the transaction message is sent to the WDT through the driver; starting timing operation after detecting that the WDT starts to work through a control module, monitoring an output signal of the WDT after reaching preset timeout time specified by the timing operation, and judging whether the output signal meets a first preset condition; if the first preset condition is met, recording the current test coverage rate, and judging whether the current test coverage rate meets a second preset condition; if the second preset condition is not met, sending a transaction completion mark to the test component through the control module to jump to the step of triggering the random test event to control the test component to select the random test sequence again so as to send a next transaction message until the current test coverage rate meets the second preset condition, and then completing the simulation verification operation. Therefore, the control module in the application comprises a timing function, and can acquire the output signal of the WDT after the preset timeout time specified by the timing operation is reached, and whether the output signal meets the first preset condition needs to be judged. Only when the output signal meets the first preset condition and the current coverage test rate does not meet the second preset condition, the control module controls the test assembly to realize the sending of the next transaction message, so that the simulation process can be dynamically controlled, the simulation time is saved, and the efficiency is improved. In addition, the condition that the current coverage test rate meets the second preset condition is used as the condition for ending the simulation, so that the coverage rate is quickly converged, and the verification efficiency is improved.
Referring to fig. 3 and 4, the embodiment of the present application discloses a specific WDT simulation verification method, and the technical solution is further described and optimized in this embodiment with respect to the previous embodiment. The method specifically comprises the following steps:
step S21: after the simulation verification operation is started, a random test event is triggered to control a test component to select a random test sequence, the random test sequence is started to send a corresponding transaction message to a driver, and the transaction message is sent to the WDT through the driver.
In this embodiment, in a specific implementation manner, it is necessary to determine configuration functions corresponding to different bus protocols in advance, and store a test sequence corresponding to each configuration function in a test sequence library in the test component. That is, the test sequence library of the test component stores test sequences corresponding to different configuration functions in advance.
In addition, the sending the transaction message to the WDT through the driver further includes: acquiring configuration data in a register through the control module, and determining a currently tested configuration function, an input value of a WDT (distributed computing) corresponding to the configuration function, and polarity and duration of an output signal according to the configuration data; constructing the first preset condition based on an input value of the WDT, a polarity and a duration of the output signal. It can be understood that, in the process of sending the transaction message to the WDT by the driver, the Monitor in the config module monitors the register configuration data and transmits the register configuration data to the control module, and the control module determines the configuration function implemented by the current transaction message according to the collected configuration data, that is, the input value of the WDT or the dog feeding time, the polarity of the output signal, the duration of the output signal, and the like, so as to construct the first preset condition based on the input value of the WDT, the polarity of the output signal, and the duration.
Step S22: after detecting that the transaction message is sent completely, a pause event is triggered to control the test component to select a pause test sequence to stop sending transaction messages.
In this embodiment, it should be noted that the test component includes all test sequences, and includes a suspend test sequence in addition to the random test sequence and the directional test sequence, and this sequence does not send any transaction message, but only pushes the simulation time in an infinite loop, thereby implementing the function of suspending the sending of the transaction message. Thus, upon detecting completion of the transmission of the transaction message, a suspend event may be triggered and the testing component may select a suspend test sequence to suspend transmission of the transaction message.
Step S23: the method comprises the steps of starting timing operation after detecting that the WDT starts to work through a control module, monitoring an output signal of the WDT after reaching preset timeout time specified by the timing operation, and judging whether the output signal meets a first preset condition or not.
Step S24: if the first preset condition is met, recording the current test coverage rate, storing the current coverage rate and corresponding transaction configuration data into a configuration database, and judging whether the current test coverage rate meets a second preset condition.
In this embodiment, if the output result of the WDT is correct, the control module may record the current coverage test rate, and store the current coverage test rate and the corresponding transaction configuration data in the internal configuration database.
Step S25: if the second preset condition is not met, sending a transaction completion mark to the test component through the control module to jump to the step of triggering the random test event to control the test component to select the random test sequence again so as to send a next transaction message until the current test coverage rate meets the second preset condition, and then completing the simulation verification operation.
In this embodiment, the sending, by the control module, the transaction completion flag to the test component to jump to the step of triggering the random test event again to control the test component to select the random test sequence so as to send the next transaction message until the current test coverage meets the second preset condition further includes: if the current test coverage rate is monitored not to change within a preset unit time, traversing the configuration database through the control module to determine an uncovered target configuration function; and controlling the test component to select a directional test sequence based on the target configuration function, and starting the directional test sequence to send the next transaction message. It can be understood that, after sending a plurality of transaction messages, the control module may monitor that the current test coverage rate has not been increased or changed within a preset unit time, at this time, the control module may traverse the internal configuration database to automatically calculate the uncovered target configuration function, when transmitting the transaction completion flag to the test component, the control module may trigger the directional test sequence event corresponding to the uncovered target configuration function in the test component, and then the test component controls the directional test sequence to send the next transaction message.
Further, in the foregoing process, the method may further include: if it is detected that all test sequences in the test sequence library have been sent, and the current test coverage does not meet the second preset condition, adding a new target oriented test sequence in the test sequence library based on the current coverage test coverage and the transaction configuration data stored in the configuration database; and controlling the test component to select the target oriented test sequence and starting the target oriented test sequence to send the next transaction message. It can be understood that, if it is detected that all test sequences in the test sequence library are completely sent, but the current test coverage rate still does not reach 100% and is not increased any more, the control module returns the coverage rate and the configuration database information, then adds a new target oriented test sequence in the test sequence library according to the information returned by the control module, and then selects the target oriented test sequence to continue the simulation verification after the test sequence library is updated until the coverage rate reaches 100%.
For more specific processing procedures of the steps S23, S24 and S25, reference may be made to corresponding contents disclosed in the foregoing embodiments, and details are not repeated here.
It can be seen that, in the embodiment of the present application, if the current test coverage does not reach 100%, a transaction completion flag is sent to the test component to re-trigger the random test event to control the test component to select the random test sequence, and then the next transaction message is sent. In the process, if the current test coverage rate is not changed within the preset unit time, the control module traverses an internal configuration database to automatically calculate the uncovered target configuration function, and then controls the test component to select the directional test sequence based on the target configuration function. In addition, if all the test sequences in the test sequence library are completely sent, but the current test coverage rate still does not reach 100%, a new target directional test sequence is added in the test sequence library according to the information returned by the control module, and then the next transaction message is sent. Therefore, the coverage rate is quickly converged, the full coverage of each configuration function test is realized, and the verification efficiency is improved.
Referring to fig. 5, an embodiment of the present application discloses a WDT emulation verification apparatus, including:
a random test module 11, configured to trigger a random test event to control a test component to select a random test sequence after a simulation verification operation is started, and start the random test sequence to send a corresponding transaction message to a driver, so as to send the transaction message to a WDT through the driver;
the output signal monitoring module 12 is configured to start a timing operation after detecting that the WDT starts working through the control module, monitor an output signal of the WDT after a preset timeout time specified by the timing operation is reached, and determine whether the output signal satisfies a first preset condition;
a coverage rate judging module 13, configured to record a current test coverage rate if the first preset condition is met, and judge whether the current test coverage rate meets a second preset condition;
and the repeated testing module 14 is configured to send, if the second preset condition is not met, a transaction completion flag to the testing component through the control module to jump to the step of triggering the random testing event again to control the testing component to select a random testing sequence, so as to send a next transaction message until the current testing coverage rate meets the second preset condition, and then complete the simulation verification operation.
As can be seen, after the simulation verification operation is started, a random test event is triggered to control the test component to select a random test sequence, and the random test sequence is started to send a corresponding transaction message to the driver, so that the transaction message is sent to the WDT through the driver; starting timing operation after detecting that the WDT starts to work through a control module, monitoring an output signal of the WDT after reaching preset timeout time specified by the timing operation, and judging whether the output signal meets a first preset condition; if the first preset condition is met, recording the current test coverage rate, and judging whether the current test coverage rate meets a second preset condition; if the second preset condition is not met, sending a transaction completion mark to the test component through the control module to jump to the step of triggering the random test event to control the test component to select the random test sequence again so as to send a next transaction message until the current test coverage rate meets the second preset condition, and then completing the simulation verification operation. Therefore, the control module in the application comprises a timing function, and can acquire the output signal of the WDT after the preset timeout time specified by the timing operation is reached, and whether the output signal meets the first preset condition needs to be judged. Only when the output signal meets the first preset condition and the current coverage test rate does not meet the second preset condition, the control module controls the test assembly to realize the sending of the next transaction message, so that the simulation process can be dynamically controlled, the simulation time is saved, and the efficiency is improved. In addition, the current coverage test rate meeting the second preset condition is used as a simulation finishing condition to realize the rapid convergence of the coverage rate, so that the verification efficiency is improved.
In some embodiments, after the random test module 11, the method may further include:
and the pause test sequence sending unit is used for triggering a pause event to control the test component to select a pause test sequence to stop sending the transaction message after detecting that the transaction message is sent completely.
In some embodiments, the WDT emulation verification apparatus may further include:
and the test sequence storage unit is used for determining the configuration functions corresponding to different bus protocols in advance and storing the test sequences corresponding to the configuration functions into a test sequence library in the test assembly.
In some specific embodiments, in the process of the coverage determining module 13, the method may further include:
the coverage rate storage unit is used for storing the current coverage test rate and corresponding transaction configuration data into a configuration database;
correspondingly, the process of repeatedly testing the module 14 may further include:
the traversing unit is used for traversing the configuration database through the control module to determine an uncovered target configuration function if the current test coverage rate is monitored not to change within a preset unit time;
and the directional test unit is used for controlling the test component to select a directional test sequence based on the target configuration function and starting the directional test sequence to send the next transaction message.
In some specific embodiments, the process of retesting the module 14 may further include:
a test sequence adding unit, configured to add a new target oriented test sequence in the test sequence library based on the current coverage test rate and the transaction configuration data stored in the configuration database if it is detected that all test sequences in the test sequence library have been sent and the current test coverage does not satisfy the second preset condition;
and the target orientation test unit is used for controlling the test component to select the target orientation test sequence and starting the target orientation test sequence to send the next transaction message.
In some specific embodiments, the process of the output signal monitoring module 12 may further include:
the configuration data acquisition unit is used for acquiring configuration data in the register through the control module and determining a currently tested configuration function, an input value of a WDT (distributed device) corresponding to the configuration function and the polarity and duration of an output signal according to the configuration data;
a first preset condition construction unit for constructing the first preset condition based on an input value of the WDT, a polarity and a duration of the output signal.
In some specific embodiments, after the output signal monitoring module 12, the method may further include:
and the simulation ending unit is used for calling a preset ending function through the control module to end the simulation verification operation if the first preset condition is not met.
Fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application. The method specifically comprises the following steps: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input output interface 25, and a communication bus 26. Wherein the memory 22 is used for storing a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps in the WDT emulation verification method executed by an electronic device disclosed in any of the foregoing embodiments.
In this embodiment, the power supply 23 is configured to provide a working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and an external device, and a communication protocol followed by the communication interface is any communication protocol applicable to the technical solution of the present application, and is not specifically limited herein; the input/output interface 25 is configured to obtain external input data or output data to the outside, and a specific interface type thereof may be selected according to specific application requirements, which is not specifically limited herein.
The processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, and the like. The processor 21 may be implemented in at least one hardware form of a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array), and a PLA (Programmable Logic Array). The processor 21 may also include a main processor and a coprocessor, where the main processor is a processor for Processing data in an awake state, and is also called a Central Processing Unit (CPU); a coprocessor is a low power processor for processing data in a standby state. In some embodiments, the processor 21 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content required to be displayed on the display screen. In some embodiments, the processor 21 may further include an AI (Artificial Intelligence) processor for processing a calculation operation related to machine learning.
In addition, the storage 22 is used as a carrier for storing resources, and may be a read-only memory, a random access memory, a magnetic disk or an optical disk, etc., the resources stored thereon include an operating system 221, a computer program 222, data 223, etc., and the storage may be a transient storage or a permanent storage.
The operating system 221 is used for managing and controlling each hardware device on the electronic device 20 and the computer program 222, so as to implement the operation and processing of the mass data 223 in the memory 22 by the processor 21, which may be Windows, unix, linux, or the like. The computer program 222 may further include a computer program that can be used to perform other specific tasks in addition to the computer program that can be used to perform the WDT simulation verification method performed by the electronic device 20 disclosed in any of the foregoing embodiments. The data 223 may include data received by the electronic device and transmitted from an external device, or may include data collected by the input/output interface 25 itself.
Further, an embodiment of the present application further discloses a computer-readable storage medium, where a computer program is stored in the storage medium, and when the computer program is loaded and executed by a processor, the method steps executed in the WDT simulation verification process disclosed in any of the foregoing embodiments are implemented.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.
The WDT simulation verification method, apparatus, device and storage medium provided by the present invention are described in detail above, and a specific example is applied in the present document to explain the principle and the implementation of the present invention, and the description of the above embodiment is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
1. A WDT simulation verification method is characterized by comprising the following steps:
after the simulation verification operation is started, triggering a random test event to control a test component to select a random test sequence, starting the random test sequence and sending a corresponding transaction message to a driver so as to send the transaction message to a WDT (wireless data transmission) through the driver;
starting timing operation after detecting that the WDT starts to work through a control module, monitoring an output signal of the WDT after reaching preset timeout time specified by the timing operation, and judging whether the output signal meets a first preset condition;
if the first preset condition is met, recording the current test coverage rate, and judging whether the current test coverage rate meets a second preset condition;
if the second preset condition is not met, sending a transaction completion mark to the test component through the control module to jump to the step of triggering the random test event to control the test component to select the random test sequence again so as to send a next transaction message until the current test coverage rate meets the second preset condition, and then completing the simulation verification operation.
2. The WDT emulation verification method of claim 1, wherein said initiating said random test sequence after sending a corresponding transaction message to a driver further comprises:
after detecting that the transaction message is sent completely, a pause event is triggered to control the test component to select a pause test sequence to stop sending the transaction message.
3. The WDT emulation verification method of claim 1, further comprising:
configuration functions corresponding to different bus protocols are predetermined, and test sequences corresponding to the configuration functions are stored in a test sequence library in the test component.
4. The WDT simulation verification method of claim 3, wherein said recording the current test coverage rate further comprises:
storing the current coverage test rate and corresponding transaction configuration data into a configuration database;
correspondingly, the sending, by the control module, the transaction completion flag to the test component to jump back to the step of triggering the random test event to control the test component to select the random test sequence, so as to send the next transaction message, until the current test coverage meets the second preset condition, further including:
if the current test coverage rate is not changed within the preset unit time, traversing the configuration database through the control module to determine the uncovered target configuration function;
and controlling the test component to select a directional test sequence based on the target configuration function, and starting the directional test sequence to send the next transaction message.
5. The WDT emulation verification method of claim 4, wherein said step of sending, by said control module, a transaction complete flag to said test component to re-jump to said step of triggering a random test event to control a test component to select a random test sequence to send a next transaction message until said current test coverage satisfies said second preset condition further comprises:
if it is detected that all the test sequences in the test sequence library have been sent completely and the current test coverage does not meet the second preset condition, adding a new target oriented test sequence in the test sequence library based on the current coverage test coverage and the transaction configuration data stored in the configuration database;
and controlling the test component to select the target oriented test sequence and starting the target oriented test sequence to send the next transaction message.
6. The WDT emulation verification method of claim 3, wherein said sending, by said driver, said transaction message to said WDT further comprises:
acquiring configuration data in a register through the control module, and determining a currently tested configuration function, an input value of a WDT (distributed computing) corresponding to the configuration function, and polarity and duration of an output signal according to the configuration data;
constructing the first preset condition based on an input value of the WDT, a polarity and a duration of the output signal.
7. The WDT emulation verification method of any of claims 1 to 6, wherein said determining whether said output signal satisfies a first predetermined condition further comprises:
if the first preset condition is not met, calling a preset ending function through the control module to end the simulation verification operation.
8. A WDT emulation verification apparatus, comprising:
the random test module is used for triggering a random test event to control a test component to select a random test sequence after starting the simulation verification operation, starting the random test sequence and sending a corresponding transaction message to a driver so as to send the transaction message to a WDT (wireless data transmission) through the driver;
the output signal monitoring module is used for starting timing operation after detecting that the WDT starts to work through the control module, monitoring an output signal of the WDT after a preset timeout time specified by the timing operation is reached, and judging whether the output signal meets a first preset condition or not;
the coverage rate judging module is used for recording the current test coverage rate if the first preset condition is met, and judging whether the current test coverage rate meets a second preset condition or not;
and the repeated testing module is used for sending a transaction completion mark to the testing component through the control module to jump to the step of triggering the random testing event again to control the testing component to select the random testing sequence if the second preset condition is not met, so as to send the next transaction message until the current testing coverage rate meets the second preset condition, and then completing the simulation verification operation.
9. An electronic device, comprising:
a memory for storing a computer program;
a processor for executing said computer program to implement the steps of the WDT simulation verification method of any of claims 1 to 7.
10. A computer-readable storage medium for storing a computer program; wherein the computer program when executed by a processor implements the steps of the WDT emulation verification method of any of claims 1 to 7.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116882334A (en) * | 2023-09-07 | 2023-10-13 | 深圳鲲云信息科技有限公司 | Method for judging end of simulation and computing equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116882334A (en) * | 2023-09-07 | 2023-10-13 | 深圳鲲云信息科技有限公司 | Method for judging end of simulation and computing equipment |
| CN116882334B (en) * | 2023-09-07 | 2023-12-15 | 深圳鲲云信息科技有限公司 | Method for judging end of simulation and computing equipment |
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