CN115642209A

CN115642209A - Micro-LED chip structure and preparation method thereof

Info

Publication number: CN115642209A
Application number: CN202211351660.5A
Authority: CN
Inventors: 李增林; 王国斌
Original assignee: Jiangsu Third Generation Semiconductor Research Institute Co Ltd
Current assignee: Jiangsu Third Generation Semiconductor Research Institute Co Ltd
Priority date: 2022-10-31
Filing date: 2022-10-31
Publication date: 2023-01-24

Abstract

The invention discloses a Micro-LED chip structure and a preparation method thereof, wherein the preparation method comprises the following steps: etching the epitaxial wafer by adopting a first-time etching process, removing part of the second nitride layer, part of the multiple quantum well luminescent layer and part of the first nitride layer on the epitaxial wafer to form an etched groove and a plurality of table boards, and exposing the first nitride layer at the etched groove; carrying out first repair treatment on the quantum well damage on the side wall of the etched groove by adopting a second etching process, and forming a slope on the side wall of the etched groove; and carrying out secondary repair treatment on the quantum well damage on part of the side wall of the etched groove by adopting a third etching process, so that the side wall of the etched groove comprises at least two inclined planes. The damaged quantum well is repaired twice, the adverse effect caused by the size effect of the Micro-LED is reduced, and the slope wall surface reflection of the upper layer and the lower layer can be additionally increased, so that the quantum efficiency of the Micro-LED is improved.

Description

Micro-LED chip structure and preparation method thereof

Technical Field

The invention relates to the technical field of semiconductors, in particular to a Micro-LED chip structure and a preparation method thereof.

Background

The Micro-LED display technology is a display technology which takes self-luminous micrometer-scale LEDs as light-emitting pixel units and assembles the light-emitting pixel units on a driving panel to form a high-density LED array. Due to the characteristics of small size, high integration level, self-luminescence and the like of the Micro-LED chip, compared with an LCD (liquid crystal display) and an OLED (organic light emitting diode), the Micro-LED chip has the advantages of higher brightness, resolution, contrast, energy consumption, service life, response speed, thermal stability and the like in the aspect of display.

However, the unit size of Micro-LEDs is smaller, and with the continuous reduction of the size of a single chip, the size effect is also increased, and the reduction of the chip size reduces the light absorption area and increases the ratio of the chip sidewall/chip surface area, thereby reducing the light absorption efficiency and increasing the dark current, and thus reducing the sidewall recombination. The quantum well at the edge of the sidewall is lost during the chip fabrication process and the size effect is further exacerbated. The research on how to reduce the invalid quantum well and increase the effective area of the chip has important significance for improving the quantum efficiency of the Micro-LED display device.

Disclosure of Invention

The invention aims to provide a Micro-LED chip structure and a preparation method thereof, wherein damaged quantum wells are repaired through two repair processes, adverse effects caused by the size effect of the Micro-LED chip structure are reduced, and slope wall surface reflection of an upper layer and a lower layer can be additionally increased, so that the internal quantum efficiency and the external quantum efficiency of the Micro-LED chip structure are improved.

The purpose of the invention is realized by adopting the following technical scheme:

a preparation method of a Micro-LED chip structure comprises the following steps:

etching an epitaxial wafer by adopting a first etching process, wherein the epitaxial wafer comprises a growth substrate, a first nitride layer, a multi-quantum well light-emitting layer and a second nitride layer which are stacked from bottom to top, removing part of the second nitride layer, part of the multi-quantum well light-emitting layer and part of the first nitride layer on the epitaxial wafer to form an etching groove and a plurality of table tops, and exposing the first nitride layer at the etching groove;

carrying out first repair treatment on the quantum well damage on the side wall of the etched groove by adopting a second etching process, wherein the side wall of the etched groove is in a slope shape;

and carrying out secondary repair treatment on the quantum well damage on part of the side wall of the etched groove by adopting a third etching process, so that the side wall of the etched groove comprises at least two inclined planes.

Preferably, after the second repairing treatment, the side wall of the etched groove is in a V shape, and the tip of the V shape of the etched groove is located on the multiple quantum well light-emitting layer.

Preferably, the first etching process is a dry etching process;

the second etching process is a dry etching process or a wet etching process, and when the second etching process is a dry etching process, the etching power of the second etching process is less than that of the first etching process;

the third etching process is a wet etching process.

Preferably, in the first etching process, the etching gas is BCl ₃ And Cl ₂ ，BCl ₃ The gas flow is 280-520sccm and Cl ₂ The gas flow is 12-28sccm, and the etching power is 200-300W;

when the second etching process is a dry etching process, the etching gas is BCl ₃ And Cl ₂ ，BCl ₃ The gas flow is 70-130sccm, cl ₂ The gas flow is 3-7sccm, and the etching power is 17-23W;

when the second etching process is a wet etching process, the etching solution is a mixed solution of phosphoric acid and sulfuric acid, the etching temperature is 180-220 ℃, and the etching time is 10-20min;

in the third etching process, the etching solution is a mixed solution of phosphoric acid and sulfuric acid, the etching temperature is 180-220 ℃, and the etching time is 10-20min.

Preferably, after the first repairing treatment, the etched groove has a trapezoid groove structure with a narrow top and a wide bottom or a trapezoid groove structure with a wide top and a narrow bottom;

when the second etching process adopts a dry etching process to carry out first repair treatment so that the etched groove is in a trapezoid groove structure with a narrow upper part and a wide lower part, the second etching process comprises the following steps: forming a thermal expansion layer on the upper surface of the table board, forming a patterned second mask layer on the thermal expansion layer and at the bottom of the etching groove, heating the epitaxial wafer to enable the second mask layer on the table board close to the edge of the etching groove to tilt upwards, repairing the damage of the quantum well on the side wall of the etching groove by adopting a dry etching process, and then removing the thermal expansion layer and the second mask layer;

when the second etching process adopts a wet etching process to carry out first repair treatment to enable the etched groove to be in a trapezoid groove structure with a narrow upper part and a wide lower part, the second etching process comprises the following steps: forming a patterned second mask layer on the upper surface of the table top and the bottom of the etching groove, covering the upper surface of the table top by the second mask layer and extending to the edge of the table top, repairing the damage of the quantum well on the side wall of the etching groove by adopting a wet etching process, forming a trapezoidal groove structure with a narrow top and a wide bottom on the side wall of the etching groove, and then removing the second mask layer;

when the second etching process adopts a wet etching process to carry out the first repair treatment so that the etched groove has a trapezoid groove structure with a wide upper part and a narrow lower part, the second etching process comprises the following steps: firstly, forming a patterned second mask layer on the upper surface of the table top and the bottom of the etching groove, covering the upper surface of the table top by the second mask layer and not extending to the edge of the table top, repairing the quantum well damage on the side wall of the etching groove by adopting a wet etching process, forming an inclined structure on the side wall of the etching groove, and then removing the second mask layer.

Preferably, when the etching groove is in a trapezoidal groove structure with a narrow top and a wide bottom, the third etching process includes: forming a third patterned mask layer on the upper surface of the table top, the bottom of the etching groove and the lower half part of the side wall of the etching groove, covering the upper surface of the table top and not extending to the edge of the table top, repairing the damage of the quantum well on the side wall of the etching groove by adopting a wet etching process to ensure that the side wall of the etching groove comprises at least two inclined planes, and then removing the third mask layer;

when the etching groove is a trapezoid groove structure with a wide upper part and a narrow lower part, the third etching process comprises the following steps: firstly, forming a third patterned mask layer on the upper surface of the table top, the bottom of the etching groove and the upper half part of the side wall of the etching groove, covering the upper surface of the table top and extending to the edge of the table top, repairing the quantum well damage on the side wall of the etching groove by adopting a wet etching process to enable the side wall of the etching groove to comprise at least two inclined planes, and then removing the third mask layer.

Preferably, when the etching groove has a trapezoid groove structure with a narrow top and a wide bottom, the first etching process includes: removing part of the second nitride layer, part of the multiple quantum well light-emitting layer and part of the first nitride layer on the epitaxial wafer to form an etching groove and a plurality of table tops, wherein the growth substrate is exposed at the etching groove; the third etching process comprises the following steps: forming a first bonding metal layer on the table top, providing a transfer substrate, arranging a second bonding metal layer on the transfer substrate, bonding the transfer substrate to the epitaxial wafer after being inverted, fusing the first bonding metal layer and the second bonding metal layer into a third bonding metal layer, removing the growth substrate, forming a patterned third mask layer on the upper surface of the table top, the bottom of the etching groove and the upper half part of the side wall of the etching groove, covering the upper surface of the table top and extending to the edge of the table top, repairing the quantum well damage on the side wall of the etching groove by adopting a wet etching process to enable the side wall of the etching groove to comprise at least two inclined planes, and then removing the third mask layer;

when the etching groove is in a trapezoid groove structure with a wide upper part and a narrow lower part, the first etching process comprises the following steps: removing part of the second nitride layer, part of the multiple quantum well light-emitting layer and part of the first nitride layer on the epitaxial wafer to form an etching groove and a plurality of table tops, wherein the growth substrate is exposed at the etching groove; the third etching process comprises the following steps: forming a first bonding metal layer on the table board, providing a transfer substrate, arranging a second bonding metal layer on the transfer substrate, bonding the transfer substrate on the epitaxial wafer after the transfer substrate is inverted, fusing the first bonding metal layer and the second bonding metal layer into a third bonding metal layer, removing the growth substrate, forming a patterned third mask layer on the upper surface of the table board, the bottom of the etching groove and the lower half part of the side wall of the etching groove, covering the upper surface of the table board and not extending to the edge of the table board, repairing the quantum well damage on the side wall of the etching groove by adopting a wet etching process, enabling the side wall of the etching groove to comprise at least two inclined planes, and then removing the third mask layer.

Preferably, the thermal expansion layer is a Ni layer, and the temperature for heating the epitaxial wafer of the layer is 352-362 ℃.

Preferably, the manufacturing method further comprises: forming a second electrode electrically connected with the second nitride layer on the table-board, and forming a first electrode electrically connected with the first nitride layer at the bottom of the etching groove; after the second electrode and the first electrode are formed, a passivation layer is formed, and the passivation layer covers the upper surface of the mesa which is not covered by the second electrode, part of the surface of the second electrode, the side wall of the etching groove, the first nitride layer of which the bottom of the etching groove is not covered by the first electrode, and part of the surface of the first electrode.

Preferably, a roughened layer is formed on the passivation layer, and the root mean square roughness of the roughened layer is 15-20nm.

Preferably, the epitaxial wafer further comprises: a buffer layer and a current spreading layer, the buffer layer being located between the growth substrate and the first nitride layer, the current spreading layer being located on the second nitride layer;

when the first nitride layer is an N-type nitride layer, the second nitride layer is a P-type nitride layer; when the first nitride layer is a P-type nitride layer, the second nitride layer is an N-type nitride layer.

A Micro-LED chip structure is obtained by the manufacturing method.

Compared with the prior art, the invention has the beneficial effects that at least:

the damaged quantum well on the side wall of the etched groove is repaired through two repairing processes, the damaged quantum well is removed, the side wall of the etched groove forms at least two inclined plane fonts and protrudes towards the etched groove, a passivation layer is favorably formed, slope wall surface reflection of an upper layer and a lower layer can be additionally increased, light-emitting efficiency of a vertical surface of a Micro-LED chip structure is enhanced, adverse effects caused by size effects of the Micro-LED chip structure are further reduced, and internal quantum efficiency and external quantum efficiency of the Micro-LED chip structure are improved.

Drawings

Fig. 1 is a flowchart of a method for manufacturing a Micro-LED chip structure according to an embodiment of the present invention.

Fig. 2a to 2g are schematic cross-sectional structure diagrams of the Micro-LED chip structure of embodiment 1 of the present invention in steps.

Fig. 3 is a schematic partial cross-sectional view of an epitaxial wafer after being heated in step S102 according to embodiment 3 of the present invention.

Fig. 4 is a schematic diagram of Ga and N in a multiple quantum well layer breaking to form dangling bonds in an embodiment of the present invention.

FIG. 5 is a graphical representation of the linear expansion coefficient of nickel of an embodiment of the present invention.

Fig. 6 is a schematic cross-sectional structure of a Micro-LED chip structure in steps according to embodiment 2 of the present invention.

Fig. 7a to 7c are schematic cross-sectional structure diagrams of Micro-LED chip structures in steps according to embodiment 3 of the present invention.

Fig. 8a to 8h are schematic cross-sectional structures of Micro-LED chip structures in steps according to embodiment 4 of the present invention.

In the figure: 100. an epitaxial wafer; 101a, a growth substrate; 101b, a transfer substrate; 102. a buffer layer; 103. a first nitride layer; 104. a multiple quantum well light-emitting layer; 105. a second nitride layer; 106. etching a groove; 107. a current spreading layer; 108. a first electrode; 109. a second electrode; 110. a thermal expansion layer; 111. a passivation layer; 112. an insulating layer; 113. a protective layer; 114. a coarsening layer; 115. a first bonding metal layer; 116. a second bonding metal layer; 117. a third bonding metal layer; 118. a second mask layer; 119. and a third mask layer.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus, a repetitive description thereof will be omitted.

The words indicating positions and directions in the present invention are illustrated by way of example in the accompanying drawings, but may be changed as required and are within the scope of the present invention.

Example 1:

referring to fig. 1 and 2a-2g, the method for manufacturing a Micro-LED chip structure provided by the present invention includes steps S101-S103.

Step S101: and etching the epitaxial wafer by adopting a first etching process to form an etching groove 106 and a plurality of table tops.

Specifically, referring to fig. 2a, the epitaxial wafer 100 includes a growth substrate 101a, a first nitride layer 103, a multiple quantum well light emitting layer 104, and a second nitride layer 105, which are sequentially stacked from bottom to top. When the first nitride layer 103 is an N-type layer, the second nitride layer 105 is a P-type layer; when the first nitride layer 103 is a P-type layer, the second nitride layer 105 is an N-type layer. The N-type layer is an N-type nitride layer, preferably an N-type gallium nitride layer, and the P-type layer is a P-type nitride layer, preferably a P-type gallium nitride layer.

As a specific example, the growth substrate 101a may be made of sapphire, silicon, gallium nitride, or silicon carbide, and in this embodiment, the growth substrate 101a is preferably made of sapphire. A first nitride layer 103 is located on the growth substrate 101a, a multiple quantum well light emitting layer 104 is located on the first nitride layer 103, a second nitride layer 105 is located on the multiple quantum well light emitting layer 104, the multiple quantum well light emitting layer 104 is preferably a material of a gallium nitride system, and the multiple quantum well light emitting layer 104 is used for carrier recombination light emission.

As shown in fig. 2b, step S101 may specifically include: forming a photoresist layer on the surface of the epitaxial wafer 100, exposing and developing the photoresist layer and forming a patterned first mask layer (not shown), wherein the photoresist is a positive photoresist or a negative photoresist; and etching the epitaxial wafer 100 by adopting a first etching process, removing part of the second nitride layer 105, part of the multiple quantum well light-emitting layer 104 and part of the first nitride layer 103 on the epitaxial wafer 100 to form an etched groove 106 and a plurality of mesas, and exposing the first nitride layer 103 at the etched groove 106, wherein the thickness of the first nitride layer 103 can be approximately half etched. The first etching process is a dry etching process, a high-power dry etching process can be adopted to improve the etching rate, and as an optimal mode, the etching gas in the dry etching process is BCl ₃ And Cl ₂ ，BCl ₃ The gas flow is 280-520sccm and Cl ₂ The gas flow is 12-28sccm, the etching power is 200-300W, and BCl is taken as an example ₃ The gas flow rate was 300sccm, cl ₂ The gas flow is 15sccm, and the etching power is 200W; then, the residual first mask layer is removed by adopting a developing solution, and the residual glue is formed by O ₂ And removing plasma, and ultrasonically cleaning by using ethanol solution to obtain a plurality of table tops. Each mesa comprises a first nitride layer 103, a multiple quantum well light emitting layer 104 and a second nitride layer 105 which are stacked from bottom to top, each mesa can correspond to one Micro-LED chip structure unit, the number of mesas can be set according to actual requirements, and the size of each mesa and the distance between adjacent mesas can also be set according to actual requirements.

Step S102: and performing first repair treatment on the quantum well damage on part of the side wall of the etched groove 106 by adopting a second etching process, wherein the side wall of the etched groove 106 is in a slope shape.

Specifically, as shown in FIG. 4, the damaged quantum well is, for exampleDuring the process of forming the etched groove 106, ga and N in the multiple quantum well light emitting layer 104 on the sidewall of the etched groove 106 are broken to form bonding damage, resulting in the occurrence of dangling bonds. Firstly, forming a thermal expansion layer 110 on the upper surface of the table top after the first mask layer is removed, wherein the thermal expansion layer 110 can be formed in a deposition mode, the thickness of the thermal expansion layer 110 is 30-80nm, and the thermal expansion layer 110 can expand when being heated; then forming a second mask layer 118 on the thermal expansion layer 110 and at the bottom of the etching groove 106, wherein the second mask layer 118 covers the thermal expansion layer 110 and the bottom of the etching groove 106; as shown in fig. 3, then heating the layer epitaxial wafer 100 to make a portion of the second mask layer 118 on the mesa near the edge of the etching recess 106 tilt upward, after tilting, the tilt height of a portion of the second mask layer 118 may gradually decrease from the edge of the etching recess 106 toward the center line of the mesa, the thermal expansion layer 110 is made of a material that is more easily expanded than the second mask layer 118 and other layers after being heated, and the temperature of the layer epitaxial wafer 100 is related to the material of the thermal expansion layer 110; after a portion of the second mask layer 118 is lifted up, a second etching process is then used to repair the quantum well damage on the sidewall of the etched groove 106, as shown in fig. 2c, a portion of the second nitride layer 105, a portion of the multiple quantum well light emitting layer 104, and the first nitride layer 103 on the epitaxial layer 100 are removed, and the damaged quantum well is removed. Because the etching power of the second etching process is smaller than that of the first etching process, the quantum well damage generated by the first etching process can be effectively removed, and the secondary quantum well damage cannot be generated on the side wall of the etching groove 106. Preferably, in the second etching process, the etching gas is BCl ₃ And Cl ₂ ，BCl ₃ The gas flow is 70-130sccm, cl ₂ The gas flow is 3-7sccm, the etching power is 17-23W, BCl is taken as an example ₃ The gas flow is 100sccm, cl ₂ The gas flow rate was 5sccm and the etching power was 20W.

As shown in fig. 3, since the portion of the second mask layer 118 near the edge of the etched recess 106 is tilted upward, the plasma of the second etching process can be obliquely etched along the arrow direction, so that the etched recess 106 forms a trapezoid-shaped groove structure with a narrow top and a wide bottom, and the sidewall of the etched recess 106 forms a slope. The side wall of the etching groove 106 is in a slope shape, so that the light emitting efficiency of the side wall light which is reflected to enter the vertical plane can be enhanced, and the quantum efficiency of the Micro-LED chip structure is effectively improved.

Preferably, the thermal expansion layer 110 is a nickel layer (Ni layer), the temperature of the epitaxial heating layer 100 is 352-362 ℃, nickel is a ferromagnetic metal, as shown in fig. 5, the linear expansion coefficient curve of nickel, when the temperature rises to approach the curie point (Tc), ferromagnetic paramagnetic transition occurs, and then the thermal expansion coefficient is obviously abnormal, that is, a λ -shaped expansion peak appears with the vertex at Tc, the experimental value of the curie point Tc of nickel is in the range of 352-362 ℃, by using a pure nickel layer as the thermal expansion layer 110, the temperature of the epitaxial heating layer 100 is set to 352-362 ℃, so that the thermal expansion layer 110 can be rapidly heated and expanded at the lower temperature, and further, the portion of the second mask layer 118 on the mesa near the edge of the etching groove 106 is tilted upward, and the heating temperature is lower, which will not affect the Micro-LED chip.

Then, the thermal expansion layer 110 is dissolved by wet etching or the thermal expansion layer 110 is etched by dry etching, the residual second mask layer 118 is removed by developing solution, and the residual glue is O ₂ plasma was removed and washed ultrasonically with ethanol solution.

Step S103: and performing secondary repair treatment on the quantum well damage on part of the side wall of the etched groove 106 by adopting a third etching process, so that the side wall of the etched groove 106 comprises at least two inclined planes.

Step S103 may specifically include: as shown in fig. 2d, a photoresist layer is formed on the surface of the epitaxial wafer 100, the photoresist layer is exposed and developed, and a patterned third mask layer 119 is formed, where the third mask layer 119 covers a portion of the upper surface of the mesa, the bottom of the etching groove 106, and the lower half of the sidewall of the etching groove 106, and the third mask layer 119 covers the upper surface of the mesa and does not extend to the edge of the mesa, that is, the third mask layer 119 does not completely cover the mesa, and the third mask layer 119 is not covered at the periphery of the mesa. A third etching process is used to repair the quantum well damage on the sidewall of the etched groove 106, the third etching process is a wet etching process, as shown in fig. 2e, the wet etching process is used to remove part of the second nitride layer 105 and part of the multiple quantum well light-emitting layer 104 on the epitaxial wafer 100, and the quantum well damage on the sidewall of the etched groove 106 is removed, and the sidewall of the etched groove 106 may include at least two slopes, for example, the sidewall of the etched groove 106 forms a V-shape and protrudes toward the etched groove 106, the V-shape is a V-shape along the longitudinal cross section of the sidewall of the etched groove 106 in the thickness direction of the Micro-LED chip structure, and the tip of the V-shape is preferably located on the multiple quantum well light-emitting layer 104, thereby facilitating improvement of light-emitting uniformity.

The side wall of the microchip is repaired by adopting a two-time repairing process method, the invalid quantum well can be eliminated better by adopting the two-time repairing process, and the slope wall surface reflection of the upper layer and the lower layer can be additionally increased, so that the light-emitting efficiency of the vertical surface of the microchip is enhanced. The two-time repairing process can more perfectly repair the damage of the side wall of the Micro core particle, and the light efficiency extraction efficiency of the Micro-LED chip structure is improved to a new height. Preferably, in the wet etching process, the etching solution is a mixed solution of phosphoric acid and sulfuric acid, the etching temperature is 180-220 ℃, the etching time is 10-20min, and as an example, the etching temperature is 200 ℃, and the etching time is 15min.

Then, the residual third mask layer 119 is removed by using a developing solution, and the residual glue is formed by O ₂ The plasma is removed and washed ultrasonically with ethanol solution.

Preferably, a second electrode 109 electrically connected to the second nitride layer 105 is formed on the mesa, and a first electrode 108 electrically connected to the first nitride layer 103 is formed at the bottom of the etched groove 106.

Specifically, as shown in fig. 2f, the second electrode 109 is formed on the second nitride layer 105 by electron beam evaporation, plasma sputtering, or thermal evaporation, the first electrode 108 is formed on the first nitride layer 103 at the bottom of the etched groove 106, and the second electrode 109 and the first electrode 108 are used for die bonding wire. Preferably, the second electrode 109 and the first electrode 108 include an ohmic contact layer, a light reflecting layer, an adhesion transition layer and a welding layer which are sequentially stacked, the ohmic contact layer is a Cr layer with a thickness of 50-100nm, the Cr layer plays a role in improving ohmic contact between the electrode and the N-type GaN layer or the P-type GaN layer, the light reflecting layer is an Al layer with a thickness of 50-100nm, the adhesion transition layer is a Ti layer, a Ni layer and a Pt layer which are sequentially arranged from bottom to top, the thicknesses of the Ti layer, the Ni layer and the Pt layer are respectively 10-50nm, the adhesion transition layer ensures that the whole electrode structure has a better adhesion effect, the second electrode 109 and the first electrode 108 are prevented from falling off the epitaxial wafer 100, the thickness of the Au layer is 1500-2500nm, and the Au layer is used for welding. The first electrode 108 and the second electrode 109 may be formed before step S102, or may be formed after step S102, and the first electrode 108 and the second electrode 109 may be formed before step S103, or may be formed after step S103.

Preferably, after the second electrode 109 and the first electrode 108 are formed, a passivation layer 111 is formed on the epitaxial wafer 100, and the passivation layer 111 covers the upper surface of the mesa not covered by the second electrode 109, a part of the surface of the second electrode 109, the sidewall of the etched groove 106, the first nitride layer 103 of the bottom of the etched groove 106 not covered by the first electrode 108, and a part of the surface of the first electrode 108.

Specifically, the passivation layer 111 is formed on the epitaxial wafer 100, and the passivation layer 111 may be deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD), low Pressure Chemical Vapor Deposition (LPCVD), or Atomic Layer Deposition (ALD), and in this embodiment, the Atomic Layer Deposition (ALD) is preferably used. The passivation layer 111 includes an insulating layer 112 and a protective layer 113 which are sequentially stacked, the protective layer 113 covers a portion of the insulating layer 112, the insulating layer 112 is a silicon nitride layer or a silicon oxide layer, and the protective layer 113 includes a Cr layer, an Al layer, and an Au layer which are sequentially stacked. The insulating layer 112 separates the protective layer 113 from the second electrode 109 and the first electrode 108, and may prevent the protective layer 113 from connecting the second electrode 109 and the first electrode 108 to short-circuit, and the insulating layer 112 may further separate the protective layer 113 from the second nitride layer 105 and the first nitride layer 103. The Cr layer of the protective layer 113 can enable the adhesiveness between the Al layer and the insulating layer 112 to be better, the insulating layer 112 is prevented from being peeled off from the protective layer 113, the Al layer can reflect light reflected by the Micro-LED chip out again, the light emitting efficiency of the Micro-LED chip structure is improved, the Au layer has better cladding performance and oxidation resistance, the Micro-LED chip structure can be better protected, and the use reliability and the heat stability of the Micro-LED chip structure tube are improved.

Preferably, the roughened layer 114 is formed on the passivation layer 111 by laser irradiation, and the surface roughened by laser irradiation has a root mean square roughness of 15-20nm. Since the refractive index of Au is usually 1.35 and the refractive index of air is 1.0, au is an optically dense medium and air is an optically sparse medium in the pair of media. According to Snel1 law, a part of light rays with incident angles smaller than the critical angle theta can be emitted into the air, but when the light rays with incident angles larger than theta are incident on the interface, the phenomenon of total internal reflection can occur. This causes a lot of large-angle light rays to exist in the light emitted from the micro-leds, and the light rays cannot be emitted into the air due to the total internal reflection phenomenon, which results in a decrease in the light emitting efficiency of the micro-leds. The coarsening of the surface can greatly reduce the occurrence of the total reflection phenomenon, thereby improving the luminous efficiency.

Preferably, as shown in fig. 2g, the epitaxial wafer 100 in step S101 further includes a buffer layer 102 and a current spreading layer 107, the buffer layer 102 is located between the growth substrate 101a and the first nitride layer 103, and by providing the buffer layer 102, the lattice matching and the crystal quality of the first nitride layer 103 and the growth substrate 101a are improved, and the buffer layer 102 may be an aluminum nitride layer. The current spreading layer 107 is located on the second nitride layer 105, and the current spreading layer 107 may be formed on the second nitride layer 105 by using electron beam evaporation, plasma sputtering, or thermal evaporation. The current spreading layer 107 may be a single-layer metal layer, a multi-layer metal layer, an ITO layer, or the like, and the current spreading layer 107 is preferably any of a nickel/gold alloy, a metal mainly containing aluminum, and ITO. Preferably, the current spreading layer 107 is an ITO layer, which has good conductivity and light transmittance and is beneficial to the photoelectric performance of the chip. When the current spreading layer 107 is provided, the second electrode 109 is formed on the current spreading layer 107.

Finally, laser or mechanical cutting is used for cutting the epitaxial wafer 100, testing and sorting are carried out to obtain the Micro-LED chip structure unit, and the cutting can adopt a known method, which is not described herein

Example 2:

referring to FIGS. 2a to 2g and FIG. 6, the method for manufacturing a Micro-LED chip structure provided by the present invention includes steps S201 to S203.

Embodiment 2 differs from embodiment 1 in that step S202 of embodiment 2 differs from step S102 of embodiment 1.

The difference between S202 and step S102 of embodiment 1 is that a photoresist layer is formed on the surface of the epitaxial wafer 100, the photoresist layer is exposed and developed, and a patterned second mask layer 118 is formed, as shown in fig. 6, the second mask layer 118 covers the upper surface of the mesa and the bottom of the etched groove 106, and the second mask layer 118 covers the upper surface of the mesa and extends to the edge of the mesa. And then, repairing the quantum well damage on the side wall of the etched groove 106 by adopting a second etching process, wherein the second etching process is a wet etching process, part of the second nitride layer 105 and part of the multiple quantum well light-emitting layer 104 on the epitaxial wafer 100 are removed, and the quantum well damaged on the side wall of the etched groove 106 is removed. Moreover, as shown in fig. 2c, since the second mask layer 118 covers the upper surface of the mesa and extends to the edge of the mesa, the wet etching process enables the etching groove 106 to form a trapezoidal groove structure with a narrow top and a wide bottom, the side wall of the etching groove 106 is in a slope shape, the light emitting efficiency of the side wall light that is reflected to enter a vertical plane is enhanced, and the quantum efficiency of the Micro-LED chip structure is effectively improved. Preferably, in the wet etching process, the etching solution is a mixed solution of phosphoric acid and sulfuric acid, the etching temperature is 180-220 ℃, the etching time is 10-20min, and as an example, the etching temperature is 200 ℃, and the etching time is 15min.

Example 3:

referring to FIGS. 2a-2g and FIGS. 7a-7c, the method for manufacturing a Micro-LED chip structure according to the present invention includes steps S301-S303.

Embodiment 3 differs from embodiment 1 in that step S302 of embodiment 3 differs from step S102 of embodiment 1, and step S303 of embodiment 3 differs from step S103 of embodiment 1.

The difference between step S302 of embodiment 3 and step S102 of embodiment 1 is that a photoresist layer is formed on the surface of the epitaxial wafer 100, the photoresist layer is exposed and developed, and a patterned second mask layer 118 is formed, as shown in fig. 7a, the second mask layer 118 covers a portion of the upper surface of the mesa and the bottom of the etched groove 106, the second mask layer 118 covers the upper surface of the mesa and does not extend to the edge of the mesa, that is, the second mask layer 118 does not completely cover the mesa, and the second mask layer 118 is not covered at the periphery of the mesa. And then, repairing the quantum well damage on the side wall of the etched groove 106 by adopting second etching, wherein the second etching process is a wet etching process, part of the second nitride layer 105 and part of the multiple quantum well light-emitting layer 104 on the epitaxial wafer 100 are removed, and the quantum well damage on the side wall of the etched groove 106 is removed. Moreover, as shown in fig. 7b, since the second mask layer 118 covers the upper surface of the mesa and does not extend to the edge of the mesa, the wet etching process enables the etching groove 106 to form a trapezoid groove structure with a wide top and a narrow bottom, the side wall of the etching groove 106 is in a slope shape, the light emitting efficiency of the side wall light that is reflected to enter a vertical plane is enhanced, and the quantum efficiency of the Micro-LED chip structure is effectively improved. Preferably, in the wet etching process, the etching solution is a mixed solution of phosphoric acid and sulfuric acid, the etching temperature is 180-220 ℃, the etching time is 10-20min, and as an example, the etching temperature is 200 ℃, and the etching time is 15min.

Step S303 of embodiment 3 is different from step S103 of embodiment 1 in that, as shown in fig. 7c, a photoresist layer is formed on the surface of the epitaxial wafer 100, the photoresist layer is exposed and developed, and a patterned third mask layer 119 is formed, the third mask layer 119 covers the upper surface of the mesa, the bottom of the etching groove 106, and the upper half of the sidewall of the etching groove 106, and the third mask layer 119 covers the upper surface of the mesa and extends to the edge of the mesa. And repairing the quantum well damage on the side wall of the etched groove 106 by adopting a third etching process, wherein the third etching process is a wet etching process, as shown in fig. 2f, the wet etching process is adopted to remove part of the second nitride layer 105 and part of the multiple quantum well light-emitting layer 104 on the epitaxial wafer 100, the quantum well damaged on the side wall of the etched groove 106 is removed, the side wall of the etched groove 106 comprises at least two inclined planes, for example, the side wall of the etched groove 106 forms a V-shape and protrudes towards the etched groove 106, and the V-shape is that the shape of the longitudinal section of the side wall of the etched groove 106 along the thickness direction of the Micro-LED chip structure is a V-shape.

Example 4:

referring to FIGS. 2a-2g and FIGS. 8a-8h, the method for manufacturing a Micro-LED chip structure provided by the present invention includes steps S401-S403.

Step S401: and etching the epitaxial wafer by adopting a first etching process to form an etching groove 106 and a plurality of table tops.

Step S401 differs from step S101 in embodiment 1 in that, as shown in fig. 8a, the first etching process includes: part of the second nitride layer 105, part of the multiple quantum well light emitting layer 104, and part of the first nitride layer 103 on the epitaxial wafer 100 are removed, and an etched groove 106 and a plurality of mesas are formed, where the growth substrate 101a is exposed at the etched groove 106.

Step S402: and performing first repair treatment on the quantum well damage on part of the side wall of the etched groove 106 by adopting a second etching process, wherein the side wall of the etched groove 106 is in a slope shape.

The second etching process in step S402 may be a dry etching process or a wet etching process. Step S402 may be the same as or similar to step S102 in embodiment 1, may also be the same as or similar to step S202 in embodiment 2, and may also be the same as or similar to step S302 in embodiment 3, which are not repeated herein.

Step S403: and performing secondary repair treatment on the quantum well damage on part of the side wall of the etched groove 106 by adopting a third etching process, so that the side wall of the etched groove 106 comprises at least two inclined planes.

When step S402 is the same as or similar to step S102 in embodiment 1, or the same as or similar to step S202 in embodiment 2, step S403 is different from step S103 in embodiment 1 in that, as shown in fig. 8b to 8e, a first bonding metal layer 115 is formed on the mesa, a transfer substrate 101b is provided, a second bonding metal layer 116 is provided on the transfer substrate 101b, the transfer substrate 101b is bonded to the epitaxial wafer 100 after being inverted, the first bonding metal layer 115 and the second bonding metal layer 116 are fused into a third bonding metal layer 117, the growth substrate 101a is removed, a patterned third mask layer 119 is then formed on the upper surface of the mesa, the bottom of the etching groove 106, and the upper half portion of the sidewall of the etching groove 106, the third mask layer 119 covers the upper surface of the mesa and extends to the edge of the mesa, a quantum well damage on the sidewall of the etching groove 106 is repaired using a third etching process, so that the sidewall of the etching groove 106 includes at least two slopes, and then the third mask layer 119 is removed.

Specifically, the first bonding metal layer 115 is formed on the second nitride layer 105 by an evaporation method. The first bonding metal layer 115 may be one or more of Au, ti, sn, ni, mn, and is preferably a titanium gold alloy. A transfer substrate 101b is provided, the transfer substrate 101b is made of a material with good light transmittance, the transfer substrate 101b may be made of sapphire, silicon, gallium nitride or the like, and the transfer substrate 101b in this embodiment is preferably made of sapphire. And depositing a second bonding metal layer 116 on the transfer substrate 101b by using electron beam evaporation, plasma sputtering or thermal evaporation, wherein the second bonding metal layer 116 may be one or more of Au, ti, sn, mn and Ni, preferably a titanium-gold alloy, and the second bonding metal layer 116 and the first bonding metal layer 115 are preferably made of the same material. The transfer substrate 101b is bonded to the epitaxial wafer 100 after being turned upside down, the first bonding metal layer 115 and the second bonding metal layer 116 are fused into a third bonding metal layer 117, and the substrate 101a is removed. Specifically, as shown in fig. 8c, the transfer substrate 101b deposited with the second bonding metal layer 116 is bonded to the epitaxial wafer 100 deposited with the first bonding metal layer 115 by flipping using a bonding apparatus with alignment function, the first bonding metal layer 115 and the second bonding metal layer 116 are coated with BCB bonding glue, as shown in fig. 8d, the first bonding metal layer 115 and the second bonding metal layer 116 are fused into a third bonding metal layer 117 under high temperature and high pressure, and the micro-LED chip structure removes the substrate 101a using a laser lift-off apparatus.

A photoresist layer is formed on the surface of the bonded epitaxial wafer 100, the photoresist layer is exposed and developed, and a patterned third mask layer 119 is formed, the third mask layer 119 covers the upper surface of the mesa, the bottom of the etching groove 106, and the upper half of the sidewall of the etching groove 106, the third mask layer 119 covers the upper surface of the mesa and extends to the edge of the mesa, and the specific structure is similar to that in fig. 7 c. A third etching process is used to repair the damage of the quantum well on the sidewall of the etched groove 106, the third etching process is a wet etching process, as shown in fig. 8e, the wet etching process is used to remove part of the second nitride layer 105 and part of the multiple quantum well light-emitting layer 104 on the epitaxial wafer 100, and the damaged quantum well on the sidewall of the etched groove 106 is removed, and the sidewall of the etched groove 106 includes at least two slopes, for example, the sidewall of the etched groove 106 forms a V shape and protrudes toward the etched groove 106, the V shape is a V shape along the longitudinal cross section of the sidewall of the etched groove 106 in the thickness direction of the Micro-LED chip structure.

When step S402 is the same as or similar to step S302 in embodiment 3, step S403 is different from step S303 in embodiment 3 in that a first bonding metal layer 115 is formed on the mesa as shown in fig. 8b and 8g, a transfer substrate 101b is provided, a second bonding metal layer 116 is provided on the transfer substrate 101b, the transfer substrate 101b is bonded to the epitaxial wafer 100 after being turned upside down, the first bonding metal layer 115 and the second bonding metal layer 116 are fused into a third bonding metal layer 117, the growth substrate 101a is removed, then a patterned third mask layer 119 is formed on the upper surface of the mesa, the bottom of the etching groove 106, and the lower half of the sidewall of the etching groove 106, the third mask layer 119 covers the upper surface of the mesa and does not extend to the edge of the mesa, a quantum well damage on the sidewall of the etching groove 106 is repaired using a third etching process, the sidewall of the etching groove 106 includes at least two slopes, and then the third mask layer 119 is removed.

Specifically, first bonding metal layer 115 is formed on second nitride layer 105 using an evaporation method. First bonding metal layer 115 may be one or more of Au, ti, sn, ni, mn, and is preferably a titanium gold alloy. A transfer substrate 101b is provided, the transfer substrate 101b is made of a material with good light transmittance, the transfer substrate 101b can be made of sapphire, silicon, gallium nitride or the like, and the transfer substrate 101b in this embodiment is preferably made of sapphire. A second bonding metal layer 116 is deposited on the transfer substrate 101b by electron beam evaporation, plasma sputtering, or thermal evaporation, the second bonding metal layer 116 may be one or more of Au, ti, sn, mn, and Ni, preferably a titanium-gold alloy, and the material of the second bonding metal layer 116 and the first bonding metal layer 115 is preferably the same. The transfer substrate 101b is bonded to the epitaxial wafer 100 after being turned upside down, the first bonding metal layer 115 and the second bonding metal layer 116 are fused into a third bonding metal layer 117, and the substrate 101a is removed. Specifically, as shown in fig. 8g, the transfer substrate 101b deposited with the second bonding metal layer 116 is bonded to the epitaxial wafer 100 deposited with the first bonding metal layer 115 by using a bonding apparatus with an alignment function, the first bonding metal layer 115 and the second bonding metal layer 116 are coated with BCB bonding glue, as shown in fig. 8h, under an environment of high temperature and high pressure, the first bonding metal layer 115 and the second bonding metal layer 116 are fused into a third bonding metal layer 117, and the micro-LED chip structure removes the substrate 101a by using a laser lift-off apparatus.

A photoresist layer is formed on the surface of the bonded epitaxial wafer 100, the photoresist layer is exposed and developed, and a patterned third mask layer 119 is formed, the third mask layer 119 covers the upper surface of the mesa, the bottom of the etching groove 106, and the lower half of the sidewall of the etching groove 106, the third mask layer 119 covers the upper surface of the mesa and does not extend to the edge of the mesa, and the specific structure is similar to that shown in fig. 2 d. A third etching process is used to repair the damage of the quantum well on the sidewall of the etched groove 106, the third etching process is a wet etching process, as shown in fig. 8e, the wet etching process is used to remove part of the second nitride layer 105 and part of the multiple quantum well light-emitting layer 104 on the epitaxial wafer 100, and the damaged quantum well on the sidewall of the etched groove 106 is removed, and the sidewall of the etched groove 106 includes at least two slopes, for example, the sidewall of the etched groove 106 forms a V-shape or an arch shape and protrudes toward the etched groove 106, the V-shape is a V-shape along the longitudinal cross section of the sidewall of the etched groove 106 in the thickness direction of the Micro-LED chip structure.

Specifically, as shown in fig. 8f, a first electrode 108 is formed on the first nitride layer 103 by electron beam evaporation, plasma sputtering, or thermal evaporation, a second electrode 109 is formed on the second bonding metal layer 116 at the bottom of the etched groove 106, and the second electrode 109 and the first electrode 108 are used for die bonding wire. Preferably, the second electrode 109 and the first electrode 108 include an ohmic contact layer, a light reflecting layer, an adhesion transition layer and a welding layer which are sequentially stacked, the ohmic contact layer is a Cr layer with a thickness of 50-100nm, the Cr layer plays a role in improving ohmic contact between the electrode and the N-type GaN layer or the P-type GaN layer, the light reflecting layer is an Al layer with a thickness of 50-100nm, the adhesion transition layer is a Ti layer, a Ni layer and a Pt layer which are sequentially arranged from bottom to top, the thicknesses of the Ti layer, the Ni layer and the Pt layer are respectively 10-50nm, the adhesion transition layer ensures that the whole electrode structure has a better adhesion effect, the second electrode 109 and the first electrode 108 are prevented from falling off the epitaxial wafer 100, the thickness of the Au layer is 1500-2500nm, and the Au layer is used for welding. The first electrode 108 and the second electrode 109 may be formed before step S403, or may be formed after step S403.

Although embodiments of the present invention have been shown and described, it will be understood that the above embodiments are exemplary and not to be construed as limiting the present invention, and that those skilled in the art may make changes, modifications, substitutions and alterations to the above embodiments without departing from the spirit and scope of the present invention, all such changes being within the scope of the appended claims.

Claims

1. A preparation method of a Micro-LED chip structure is characterized by comprising the following steps:

etching an epitaxial wafer by adopting a first-time etching process, wherein the epitaxial wafer comprises a growth substrate, a first nitride layer, a multiple quantum well light-emitting layer and a second nitride layer which are stacked from bottom to top, part of the second nitride layer, part of the multiple quantum well light-emitting layer and part of the first nitride layer on the epitaxial wafer are removed, etching grooves and multiple table tops are formed, and the first nitride layer is exposed at the etching grooves;

2. The method for preparing a Micro-LED chip structure according to claim 1, wherein after the second repairing process, the side wall of the etched groove is V-shaped, and the V-shaped tip of the etched groove is located on the multiple quantum well light-emitting layer.

3. A method of fabricating a Micro-LED chip structure according to claim 1,

the first etching process is a dry etching process;

the second etching process is a dry etching process or a wet etching process, and when the second etching process is the dry etching process, the etching power of the second etching process is smaller than that of the first etching process;

the third etching process is a wet etching process.

4. A method of fabricating a Micro-LED chip structure according to claim 3,

in the first etching process, the etching gas is BCl ₃ And Cl ₂ ，BCl ₃ The gas flow is 280-520sccm and Cl ₂ The gas flow is 12-28sccm, and the etching power is 200-300W;

the second etching processWhen the etching process is a dry etching process, the etching gas is BCl ₃ And Cl ₂ ，BCl ₃ The gas flow is 70-130sccm, cl ₂ The gas flow is 3-7sccm, and the etching power is 17-23W;

5. The method for preparing a Micro-LED chip structure according to claim 3, wherein after the first repairing treatment, the etched groove is in a trapezoid groove structure with a narrow top and a wide bottom or in a trapezoid groove structure with a wide top and a narrow bottom;

when the second etching process adopts a dry etching process to carry out the first repair treatment so that the etched groove has a trapezoid groove structure with a narrow top and a wide bottom, the second etching process comprises the following steps: forming a thermal expansion layer on the upper surface of the table board, forming a patterned second mask layer on the thermal expansion layer and at the bottom of the etching groove, heating the epitaxial wafer to enable the second mask layer on the table board close to the edge of the etching groove to tilt upwards, repairing the damage of the quantum well on the side wall of the etching groove by adopting a dry etching process, and then removing the thermal expansion layer and the second mask layer;

6. A method of fabricating a Micro-LED chip structure according to claim 5,

when the etching groove is in a trapezoid groove structure with a narrow upper part and a wide lower part, the third etching process comprises the following steps: forming a third patterned mask layer on the upper surface of the table top, the bottom of the etching groove and the lower half part of the side wall of the etching groove, wherein the third patterned mask layer covers the upper surface of the table top and does not extend to the edge of the table top;

when the etching groove is in a trapezoid groove structure with a wide upper part and a narrow lower part, the third etching process comprises the following steps: firstly, forming a third patterned mask layer on the upper surface of the table top, the bottom of the etching groove and the upper half part of the side wall of the etching groove, covering the upper surface of the table top and extending to the edge of the table top, repairing the quantum well damage on the side wall of the etching groove by adopting a wet etching process to enable the side wall of the etching groove to comprise at least two inclined planes, and then removing the third mask layer.

7. A method of fabricating a Micro-LED chip structure according to claim 5,

when the etching groove is in a trapezoid groove structure with a narrow upper part and a wide lower part, the first etching process comprises the following steps: removing part of the second nitride layer, part of the multiple quantum well light-emitting layer and part of the first nitride layer on the epitaxial wafer to form an etching groove and a plurality of table tops, wherein the growth substrate is exposed at the etching groove; the third etching process comprises the following steps: forming a first bonding metal layer on the table top, providing a transfer substrate, arranging a second bonding metal layer on the transfer substrate, inverting the transfer substrate and bonding the transfer substrate onto the epitaxial wafer, so that the first bonding metal layer and the second bonding metal layer are fused into a third bonding metal layer, removing the growth substrate, then forming a patterned third mask layer on the upper surface of the table top, the bottom of the etching groove and the upper half part of the side wall of the etching groove, covering the upper surface of the table top and extending to the edge of the table top, repairing the quantum well damage on the side wall of the etching groove by adopting a wet etching process, so that the side wall of the etching groove comprises at least two inclined planes, and then removing the third mask layer;

8. A method of fabricating a Micro-LED chip structure as recited in claim 5, wherein said thermal expansion layer is a Ni layer and the temperature to which said epitaxial layer is heated is 352-362 ℃.

9. The method of fabricating a Micro-LED chip structure according to claim 1, wherein the fabricating method further comprises: forming a second electrode electrically connected with the second nitride layer on the table-board, and forming a first electrode electrically connected with the first nitride layer at the bottom of the etching groove; after the second electrode and the first electrode are formed, a passivation layer is formed, and the passivation layer covers the upper surface of the table top, which is not covered by the second electrode, part of the surface of the second electrode, the side wall of the etching groove, the first nitride layer of which the bottom of the etching groove is not covered by the first electrode, and part of the surface of the first electrode.

10. A method of fabricating a Micro-LED chip structure according to claim 9, wherein a roughened layer is formed on the passivation layer, the roughened layer having a root mean square roughness of 15-20nm.

11. A method of fabricating a Micro-LED chip structure according to claim 1, wherein the epitaxial wafer further comprises: a buffer layer and a current spreading layer, the buffer layer being located between the growth substrate and the first nitride layer, the current spreading layer being located on the second nitride layer;

12. A Micro-LED chip structure, characterized in that it is obtained by the manufacturing method according to any one of claims 1 to 11.