CN115622556A - Multistage down-conversion frequency synthesis device and method - Google Patents

Multistage down-conversion frequency synthesis device and method Download PDF

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Publication number
CN115622556A
CN115622556A CN202211315298.6A CN202211315298A CN115622556A CN 115622556 A CN115622556 A CN 115622556A CN 202211315298 A CN202211315298 A CN 202211315298A CN 115622556 A CN115622556 A CN 115622556A
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frequency
yto
vco
output
mixer
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王伟
杨东营
李宁
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CLP Kesiyi Technology Co Ltd
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CLP Kesiyi Technology Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/12—Indirect frequency synthesis using a mixer in the phase-locked loop

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Abstract

The invention discloses a device and a method for synthesizing multistage down-conversion frequency, and belongs to the field of frequency synthesis. The invention simplifies the circuit by a multi-stage down-conversion method, reduces the debugging difficulty and is easy to debug; the VCO phase-locked loop also generates a fixed tuning local oscillation frequency point by a multi-stage down-conversion method; according to different frequency bands of the YTO, a proper VCO fixed tuning local oscillation point can be flexibly selected, so that various intermodulation spurs are effectively avoided; through mixing of the YTO and the VCO, a near-end phase noise curve of the YTO loop is close to a phase noise curve of the VCO loop to reach a low phase noise level, and the YTO loop and the VCO loop both reach the low phase noise level through a multi-stage down-conversion method, so that intermodulation stray can be flexibly inhibited.

Description

Multistage down-conversion frequency synthesis device and method
Technical Field
The invention belongs to the technical field of frequency synthesis, and particularly relates to a multistage down-conversion frequency synthesis device and method.
Background
The frequency synthesis technique simply refers to generating a target frequency by one or more reference signal sources through a linear operation in a frequency domain. The circuit that implements frequency synthesis is called a frequency synthesizer, which is an important component of modern electronic systems. Frequency synthesizers typically employ the following techniques: 1. direct digital frequency technology, i.e., DDS technology; 2. phase-locked loop technology, i.e., PLL technology; 3. DDS + PLL technique. The spurious indications of DDS in frequency synthesized signals are generally poor and are not generally used directly. The basic theory of phase-locked loops was proposed in the 30's of the 20 th century, and the development to date has become well-established for applications in the field of electronic systems.
The prior art scheme of the frequency synthesis method for the broadband YTO is also based on the PLL technology and frequency synthesis based on the broadband YTO with 4-10 GHz, and the prior art scheme is as follows: introducing a VCO phase-locked loop to perform down-mixing processing on YTO, performing primary down-mixing to obtain phase discrimination frequency, selecting a VCO (1 GHz-2.5 GHz), performing two-stage frequency doubling processing on the VCO, performing band-pass filtering on 2 GHz-5 GHz obtained after primary frequency doubling through a switch frequency dividing section, performing band-pass filtering processing on 4 GHz-10 GHz obtained after secondary frequency doubling through the switch frequency dividing section, and obtaining the phase discrimination reference of the YTO loop through a small number frequency divider. The phase discrimination reference of the VCO loop is obtained by dividing an external high-purity reference signal by an integer, two-stage frequency doubling output of the VCO is subjected to frequency mixing with the external high-purity reference signal of 4.8GHz or a frequency doubling signal of 9.6GHz, and then 100MHz sampling is carried out on the one-stage frequency mixing output, namely, a harmonic frequency mixing method is adopted, so that the phase discrimination input signal of the VCO loop is obtained. The technical method is complex, the corresponding circuit structure is also complex, and the debugging difficulty is high. The phase noise of the VCO loop is also not optimal due to the harmonic mixing method adopted by the VCO loop.
Aiming at the locking scheme of a broadband YIG Tuned Oscillator (YTO), the existing frequency synthesis methods mainly comprise two methods, one method is to carry out frequency division processing on the YTO to obtain phase discrimination frequency and carry out phase discrimination integration with reference frequency, so that the YTO is locked; the other method is to adopt a wide-band VCO to carry out frequency mixing with the YTO to obtain a phase discrimination frequency, and then carry out phase discrimination integration with a reference frequency to lock the YTO. The phase noise of the first method mainly depends on a broadband YTO, and the phase noise index is generally poor and cannot reach a low phase noise level; the second method is generally difficult to find a broadband VCO corresponding to the broadband YTO, and in the prior art, a more appropriate broadband VCO is subjected to multiple frequency multiplication and then is subjected to frequency mixing with the broadband YTO to obtain a phase demodulation frequency.
The existing broadband YTO frequency synthesis technology generally adopts a first-level down-conversion scheme, frequency mixing is carried out through multiple frequency multiplication of a VCO phase-locked loop to obtain phase demodulation frequency, a large amount of filtering and shielding processing are required to be carried out on a path in the VCO multiple frequency multiplication path, the occupied space of a printed circuit board is large, the circuit is complex, the debugging difficulty is large, and the cost is high.
Disclosure of Invention
Aiming at the technical problems in the prior art, the invention provides a multistage down-conversion frequency synthesis device and method, which are reasonable in design, overcome the defects of the prior art and have good effects.
In order to achieve the purpose, the invention adopts the following technical scheme:
a multi-stage down-conversion frequency synthesizer comprises a YTO ring;
the YTO ring comprises a 4.8GHz reference signal, a first power divider, a fractional frequency divider, a first mixer, a first single-pole double-throw switch, a first phase discriminator, a first integrating circuit, a voltage-current conversion circuit, a VCO ring, an YTO driving circuit, an YTO, a second mixer and a second single-pole double-throw switch;
the 4.8GHz reference signal, one end of the first power distributor, the fractional frequency divider, the first phase discriminator, the first integrating circuit, the voltage-current conversion circuit, the YTO, the second frequency mixer and the second single-pole double-throw switch are sequentially connected through a line; the other end of the first power divider, the frequency divider, the first mixer, the first single-pole double-throw switch and the first phase discriminator are sequentially connected through a line; the YTO driving circuit is connected with the YTO through a line; the VCO loop is connected with the second mixer through a line; the second single-pole double-throw switch is respectively connected with the first single-pole double-throw switch and the first frequency mixer through lines;
a 4.8GHz reference signal, at a frequency of 4.8GHz, from outside the module, configured for output to the first power divider;
the first power divider is configured to implement balanced distribution of 4.8GHz signal power, one path serves as the input of the fractional frequency divider, and the other path serves as the input of the two-way frequency divider;
a fractional divider configured as a phase detector for generating YTO rings of 25MHz to 75MHzReference signal f of PDREF ；
A frequency halver configured to generate 2.4GHz as a fixed local oscillator for the two-stage down-mixing;
a first mixer configured for second-stage mixing of YTO ring, outputting a phase discrimination frequency f of YTO ring PD ；
A first single-pole double-throw switch configured to select a path according to a frequency band of the YTO ring; if f is YTO Selecting a second single-pole double-throw switch channel when the frequency is less than or equal to 7.6 GHz; otherwise, selecting a first mixer path;
the first phase discriminator is used for carrying out frequency discrimination and phase discrimination on a reference signal and an input signal and outputting the reference signal and the input signal to the integrating circuit;
the first integrating circuit is configured to integrate the output signal of the first phase detector to obtain an error voltage, has a low-pass filtering effect, and filters high-frequency and noise components in the error signal;
a voltage-to-current conversion circuit configured to convert the error voltage signal to a current signal to drive YTO;
the VCO loop is configured to output a fixed down-conversion local oscillator at 4-8 GHz;
a YTO drive circuit configured to drive YTO operation;
YTO, a YIG (Yttrium Iron Garnet) tuned oscillator;
a second mixer configured to mix the YTO output signal with the VCO loop output signal to obtain a first-level mixing output | f YTO -f VCO ∣；
A second single-pole double-throw switch configured to select a path according to a frequency band of the YTO ring; if f is YTO Selecting a first single-pole double-throw switch channel when the frequency is less than or equal to 7.6 GHz; otherwise the first mixer path is selected.
Preferably, the VCO loop comprises a 100MHz reference signal, a 4.8GHz reference signal, a second power divider, a third mixer, a second phase detector, a second integrating circuit, a filter, a frequency doubler, a VCO driving circuit, a VCO, a fourth mixer, and a broadband prescaler;
the 100MHz reference signal is connected with the second phase discriminator through a line; the 4.8GHz reference signal, one end of the second power divider and the third mixer are sequentially connected through a line; the third mixer, the second phase discriminator, the second integrating circuit, the VCO, the fourth mixer and the filter form a loop which is connected through a line; the VCO driving circuit is connected with the VCO through a line; the other end of the second power divider, the frequency doubler, the broadband prescaler and the fourth frequency mixer are connected through lines;
a 100MHz reference signal, having a frequency of 100MHz, external to the module, configured for output to the second phase detector;
a 4.8GHz reference signal, at a frequency of 4.8GHz, from outside the module, configured for output to the second power divider;
the second power divider is configured to be used for realizing balanced distribution of 4.8GHz signal power, wherein one path is used as the input of the third mixer, and the other path is used as the input of the frequency doubler;
the third mixer is configured to perform secondary mixing of the VCO ring to obtain the phase discrimination frequency of the VCO ring and output the phase discrimination frequency to the second phase discriminator;
the second phase detector is configured to perform phase frequency detection on the reference signal and the input signal and output the signals to the second integrating circuit;
the second integration circuit is configured for integrating the output of the second phase discriminator to obtain an error voltage, has a low-pass filtering effect and filters high-frequency and noise components in an error signal;
a filter configured to low-pass filter a first-order mixing output of the VCO loop to filter out a noise component;
and the frequency doubler is configured to double the frequency of the 4.8GHz signal to obtain 9.6GHz, and output the frequency doubler to the broadband prescaler.
A VCO driving circuit configured to drive a VCO operation;
VCO, voltage controlled oscillator;
the fourth mixer is used for carrying out primary mixing on the signal output by the VCO and the signal output by the broadband prescaler to obtain 4.7GHz or 4.9GHz;
a wideband prescaler configured to output a first stage fixed down-converted local oscillator of the VCO loop.
In addition, the invention also provides a multistage down-conversion frequency synthesis method, which adopts the multistage down-conversion frequency synthesis device, and specifically comprises the following steps:
step 1: setting an external high-purity frequency source, and providing frequencies of 4.8GHz and 100MHz;
and 2, step: if f is YTO When the frequency of the YTO and the VCO ring after frequency mixing by the second mixer is less than or equal to 7.6GHz, the phase discrimination frequency is obtained through the second single-pole double-throw switch and the first single-pole double-throw switch and is output to the first phase discriminator; if f is YTO If the frequency is more than 7.6GHz, the frequency obtained by mixing the YTO and the VCO ring through the second mixer, the 4.8GHz reference signal through the second single-pole double-throw switch and the output 2.4GHz of the first power divider and the frequency divider is mixed through the second single-pole double-throw switch, and the phase-discriminated frequency is obtained through the first single-pole double-throw switch and is output to the first phase discriminator;
and step 3: the YTO ring phase discrimination reference frequency is generated by a 4.8GHz reference signal after passing through a first power divider and then passing through a fractional frequency divider;
and 4, step 4: the YTO ring is output through the YTO driving circuit and the first phase detector, and then is output to the voltage-current conversion circuit through the first integrating circuit to jointly control the locking of the YTO ring;
and 5: selecting a VCO ring fixed tuning local oscillation point according to the YTO frequency;
step 6: the 4.8GHz reference signal generates the first-stage mixing output frequency of the VCO ring through a second power divider, a frequency doubler and a broadband prescaler;
and 7: the VCO and the first-stage mixing output frequency are mixed through a fourth mixer, the output is mixed with a 4.8GHz reference signal through a filter, the output of the second power divider is mixed through a third mixer to obtain a 100MHz phase discrimination frequency, and then the 100MHz phase discrimination frequency and the reference 100MHz phase discrimination integral are obtained;
and step 8: the VCO driving circuit and the second phase detection integration control the locking of the VCO loop through the output of the second integration circuit together.
Preferably, the frequency range of YTO is 4-10GHz and the frequency range of VCO is 4-8 GHz.
Preferably, the frequency band of the YTO output frequency is: f. of YTO Less than or equal to 7.6GHz or f YTO ＞7.6GHz。
The invention has the following beneficial technical effects:
the invention simplifies the circuit by a multi-stage down-conversion method, reduces the debugging difficulty and is easy to debug; the VCO phase-locked loop also generates a fixed tuning local oscillation frequency point by a multi-stage down-conversion method; according to different frequency bands of YTO, a proper VCO fixed tuning local oscillation point can be flexibly selected, and various intermodulation stray can be effectively avoided.
Drawings
FIG. 1 is a schematic diagram of YTO ring of the present invention;
FIG. 2 is a schematic diagram of a VCO loop of the present invention;
wherein, the reference signal is 1-4.8 GHz; 2-a first power divider; 3-fractional divider; 4-a frequency divider; 5-a first mixer; 6-a first single pole double throw switch; 7-a first phase detector; 8-a first integrating circuit; 9-a voltage current conversion circuit; 10-VCO loop; 11-YTO drive circuit; 12-YTO; 13-a second mixer; 14-a second single pole double throw switch; 15-100MHz reference signal; 16-a second power divider; 17-a third mixer; 18-a second phase detector; 19-a second integrating circuit; 20-a filter; 21-a frequency doubler; 22-VCO driving circuit; 23-a VCO; 24-a fourth mixer; 25-broadband prescaler.
Detailed Description
The invention is described in further detail below with reference to the following figures and detailed description:
the invention mainly provides a low-phase noise frequency synthesis method based on multi-stage down conversion aiming at a broadband YTO, the near-end phase noise curve of an YTO loop is close to the phase noise curve of a VCO ring through mixing of the YTO and the VCO to reach a low-phase noise level, and both the YTO loop and the VCO ring reach the low-phase noise level through the multi-stage down conversion method, so that intermodulation stray can be flexibly inhibited.
Example 1:
a multi-stage down-conversion frequency synthesizer comprises a YTO ring; the principle is as shown in figure 1 of the drawings,
the YTO ring comprises a 4.8GHz reference signal 1, a first power divider 2, a fractional frequency divider 3, a frequency divider 4, a first mixer 5, a first single-pole double-throw switch 6, a first phase detector 7, a first integrating circuit 8, a voltage-current conversion circuit 9, a VCO ring 10, an YTO driving circuit 11, an YTO12, a second mixer 13 and a second single-pole double-throw switch 14;
the 4.8GHz reference signal 1, one end of the first power divider 2, the fractional frequency divider 3, the first phase discriminator 7, the first integrating circuit 8, the voltage-current conversion circuit 9, the YTO12, the second mixer 13 and the second single-pole double-throw switch 14 are sequentially connected through a line; the other end of the first power divider 2, the frequency divider 4, the first mixer 5, the first single-pole double-throw switch 6 and the first phase detector 7 are connected in sequence through a line; the YTO driving circuit 11 is connected with the YTO12 through a line; the VCO loop 10 is connected to the second mixer 13 by a line; the second single-pole double-throw switch 14 is respectively connected with the first single-pole double-throw switch 6 and the first mixer 5 through lines;
a 4.8GHz reference signal 1, frequency 4.8GHz, from outside the module, configured for output to a first power divider 2;
a first power divider 2 configured to implement balanced division of 4.8GHz signal power, one path being an input of a fractional divider 3, and the other path being an input of a divide-by-two divider 4;
a fractional divider 3 configured as a reference signal f for a phase detector generating YTO-rings of 25MHz to 75MHz PDREF ；
A frequency halver 4 configured to generate 2.4GHz as a fixed local oscillator for the two-stage down-mixing;
a first mixer 5 configured for second stage mixing of YTO ring, outputting a phase detection frequency f of YTO ring PD ；
A first single-pole double-throw switch 6 configured to select a path according to a frequency band of the YTO ring; if f is YTO Selecting a second single-pole double-throw switch channel when the frequency is less than or equal to 7.6 GHz; otherwise, selecting a first mixer path;
a first phase detector 7 configured to perform frequency and phase discrimination on the reference signal and the input signal, and output the signals to the integrating circuit;
the first integrating circuit 8 is configured to integrate the output signal of the first phase detector 7 to obtain an error voltage, has a low-pass filtering effect, and filters high-frequency and noise components in the error signal;
a voltage-to-current conversion circuit 9 configured to convert the error voltage signal into a current signal to drive the YTO;
a VCO loop 10 configured to output a fixed down-conversion local oscillator of 4 to 8 GHz;
an YTO drive circuit 11 configured to drive YTO operation;
YTO12, a YIG (Yttrium Iron Garnet) tuned oscillator;
a second mixer 13 configured for mixing the signal output by YTO12 with the signal output by the VCO loop 10 to obtain a first-level mixing output | f YTO -f VCO ∣；
A second single-pole double-throw switch 14 configured to select a path according to a frequency band of the YTO ring; if f is YTO Selecting a first single-pole double-throw switch path if the frequency is less than or equal to 7.6 GHz; otherwise the first mixer path is selected.
Example 2:
the VCO loop principle in the YTO loop is shown in fig. 2, and the VCO loop includes a 100MHz reference signal 15, a 4.8GHz reference signal 1, a second power divider 16, a third mixer 17, a second phase detector 18, a second integrating circuit 19, a filter 20, a frequency doubler 21, a VCO driving circuit 22, a VCO23, a fourth mixer 24, and a broadband prescaler 25;
the 100MHz reference signal 15 is connected with the second phase discriminator 18 through a line; the 4.8GHz reference signal 1, one end of the second power divider 16 and the third mixer 17 are connected in sequence through lines; the third mixer 17, the second phase detector 18, the second integrating circuit 19, the VCO23, the fourth mixer 24 and the filter 20 form a loop, and are connected by a line; the VCO driving circuit 22 is connected to the VCO23 by a line; the other end of the second power divider 16, the frequency doubler 21, the broadband prescaler 25 and the fourth mixer 24 are connected through lines;
a 100MHz reference signal 15, at 100MHz, from outside the module, configured for output to the second phase detector;
a 4.8GHz reference signal 1, frequency 4.8GHz, from outside the module, configured for output to the second power splitter;
a second power divider 16 configured to implement balanced division of 4.8GHz signal power, one path being an input of the third mixer 17, and the other path being an input of the frequency doubler 21;
the third mixer 17 is configured to perform secondary mixing of the VCO loop to obtain a phase detection frequency of the VCO loop, and output the phase detection frequency to the second phase detector 18;
a second phase detector 18 configured to perform phase frequency detection on the reference signal and the input signal, and output the phase frequency detected signal to a second integrating circuit 19;
a second integrating circuit 19, configured to integrate the output of the second phase detector 18 to obtain an error voltage, having a low-pass filtering function, and filtering out high-frequency and noise components in the error signal;
a filter 20 configured to low-pass filter the first-order mixing output of the VCO loop to filter out a noise component;
and the frequency doubler 21 is configured to double the frequency of the 4.8GHz signal to obtain 9.6GHz, and output the signal to the broadband prescaler.
A VCO driving circuit 22 configured to drive the VCO operation;
VCO23, voltage controlled oscillator;
the fourth mixer 24 performs first-stage mixing on the signal output by the VCO23 and the signal output by the broadband prescaler 25 to obtain 4.7GHz or 4.9GHz;
a wideband prescaler 25 configured to output a first stage fixed down-converted local oscillator of the VCO loop.
Example 3:
on the basis of the above embodiments, the present invention also provides a multi-stage down-conversion frequency synthesis method, wherein,
the frequency synthesis equation is:
f YTO ＝f VCO +/-4.8 GHz/N.F, (YTO output frequency f YTO ≤7.6GHz)；
f YTO ＝2.4GHz+f VCO +/-4.8 GHz/N.F, (YTO output frequency f) YTO ＞7.6GHz)；
f VCO ＝4.8GHz±f PRE ±100MHz；
In the above formula, f YTO Is YTO output signal, and can be any frequency in 4-10 GHz; f. of VCO For the VCO output signal according to f YTO The frequency can be selected from limited fixed frequencies in the range of 4-8 GHz; N.F is the frequency dividing ratio of the fractional frequency divider; f. of PRE For a wide frequency band prescaler output signal, according to f VCO The frequency may be selected to be a frequency in a finite fixed frequency range of 75MHz to 3000 MHz.
The method specifically comprises the following steps:
step 1: setting an external high-purity frequency source, and providing frequencies of 4.8GHz and 100MHz;
step 2: if f is YTO When the frequency of the YTO and the VCO ring after frequency mixing by the second mixer is less than or equal to 7.6GHz, the phase discrimination frequency is obtained through the second single-pole double-throw switch and the first single-pole double-throw switch and is output to the first phase discriminator; if f is YTO If the frequency is more than 7.6GHz, the frequency obtained by mixing the YTO and the VCO ring through the second mixer, the 4.8GHz reference signal through the second single-pole double-throw switch and the output 2.4GHz of the first power divider and the frequency divider is mixed through the second single-pole double-throw switch, and the phase-discriminated frequency is obtained through the first single-pole double-throw switch and is output to the first phase discriminator;
and step 3: the YTO ring phase demodulation reference frequency is generated by a 4.8GHz reference signal through a first power divider and then through a fractional frequency divider;
and 4, step 4: the YTO ring is output through the YTO driving circuit and the first phase detector, and then is output to the voltage-current conversion circuit through the first integrating circuit to jointly control the locking of the YTO ring;
and 5: selecting a VCO ring fixed tuning local oscillation point according to the YTO frequency;
step 6: the 4.8GHz reference signal generates the first-stage mixing output frequency of the VCO ring through a second power divider, a frequency doubler and a broadband prescaler;
and 7: the VCO and the first-stage mixing output frequency are mixed through a fourth mixer, the output of the VCO and the first-stage mixing output frequency is mixed through a filter and a 4.8GHz reference signal through the output of a second power divider and then through a third mixer to obtain a 100MHz phase discrimination frequency, and then the 100MHz phase discrimination integral is obtained;
and step 8: the VCO driving circuit and the second phase detection integration control the locking of the VCO loop through the output of the second integration circuit.
The frequency range of YTO is 4-10GHz and the frequency range of VCO is 4-8 GHz.
The frequency band of YTO output frequency is: f. of YTO Less than or equal to 7.6GHz or f YTO ＞7.6GHz。
Suppose that a frequency synthesis signal f is required YTO For 4050MHz signal, f may be set VCO 4100MHz, N.F 96.0 PRE Is 600MHz.
It is to be understood that the above description is not intended to limit the present invention, and the present invention is not limited to the above examples, and those skilled in the art may make modifications, alterations, additions or substitutions within the spirit and scope of the present invention.

Claims (4)

1. A multi-stage down-conversion frequency synthesizer, comprising: including YTO rings;
the YTO ring comprises a 4.8GHz reference signal, a first power divider, a fractional frequency divider, a first mixer, a first single-pole double-throw switch, a first phase discriminator, a first integrating circuit, a voltage-current conversion circuit, a VCO ring, an YTO driving circuit, an YTO, a second mixer and a second single-pole double-throw switch;
the 4.8GHz reference signal, one end of the first power distributor, the fractional frequency divider, the first phase discriminator, the first integrating circuit, the voltage-current conversion circuit, the YTO, the second frequency mixer and the second single-pole double-throw switch are sequentially connected through a line; the other end of the first power divider, the frequency divider, the first mixer, the first single-pole double-throw switch and the first phase detector are sequentially connected through a line; the YTO driving circuit is connected with the YTO through a line; the VCO loop is connected with the second mixer through a line; the second single-pole double-throw switch is respectively connected with the first single-pole double-throw switch and the first frequency mixer through lines;
a 4.8GHz reference signal, at a frequency of 4.8GHz, from outside the module, configured for output to the first power divider;
the first power divider is configured to implement balanced distribution of 4.8GHz signal power, one path serves as the input of the fractional frequency divider, and the other path serves as the input of the two-way frequency divider;
a fractional divider configured as a reference signal f for a phase detector generating YTO-rings of 25MHz to 75MHz PDREF ；
A frequency halver configured to generate a 2.4GHz frequency as a fixed local oscillator for the two-stage down-mixing;
a first mixer configured for second stage mixing of YTO ring, outputting a phase detection frequency f of YTO ring PD ；
A first single-pole double-throw switch configured to select a path according to a frequency band of the YTO ring; if f is YTO Selecting a second single-pole double-throw switch channel when the frequency is less than or equal to 7.6 GHz; otherwise, selecting a first mixer path;
the first phase discriminator is used for carrying out frequency discrimination and phase discrimination on a reference signal and an input signal and outputting the reference signal and the input signal to the integrating circuit;
the first integrating circuit is configured to integrate the output signal of the first phase detector to obtain an error voltage, has a low-pass filtering effect, and filters high-frequency and noise components in the error signal;
a voltage-to-current conversion circuit configured to convert the error voltage signal to a current signal to drive YTO;
the VCO loop is configured to output a fixed down-conversion local oscillator at 4-8 GHz;
a YTO drive circuit configured to drive YTO operation;
YTO, YIG tuned oscillator;
a second mixer configured to mix the YTO output signal with the VCO loop output signal to obtain a first-level mixing output |f YTO -f VCO ∣；
A second single-pole double-throw switch configured to select a path according to a frequency band of the YTO ring; if f is YTO Selecting a first single-pole double-throw switch channel when the frequency is less than or equal to 7.6 GHz; otherwise the first mixer path is selected.
2. The multi-stage down-conversion frequency synthesizing apparatus according to claim 1, wherein: the VCO ring comprises a 100MHz reference signal, a 4.8GHz reference signal, a second power divider, a third mixer, a second phase discriminator, a second integrating circuit, a filter, a frequency doubler, a VCO driving circuit, a VCO, a fourth mixer and a broadband prescaler;
the 100MHz reference signal is connected with the second phase discriminator through a line; the 4.8GHz reference signal, one end of the second power divider and the third mixer are sequentially connected through a line; the third mixer, the second phase discriminator, the second integrating circuit, the VCO, the fourth mixer and the filter form a loop which is connected through a line; the VCO driving circuit is connected with the VCO through a line; the other end of the second power divider, the frequency doubler, the broadband prescaler and the fourth frequency mixer are connected through lines;
a 100MHz reference signal, having a frequency of 100MHz, external to the module, configured for output to the second phase detector;
a 4.8GHz reference signal, at a frequency of 4.8GHz, from outside the module, configured for output to the second power divider;
the second power divider is configured to be used for realizing balanced distribution of 4.8GHz signal power, wherein one path is used as the input of the third mixer, and the other path is used as the input of the frequency doubler;
the third mixer is configured to perform secondary mixing of the VCO ring to obtain the phase discrimination frequency of the VCO ring and output the phase discrimination frequency to the second phase discriminator;
the second phase detector is configured to perform frequency and phase discrimination on the reference signal and the input signal and output the reference signal and the input signal to the second integrating circuit;
the second integration circuit is configured to integrate the output of the second phase discriminator to obtain an error voltage, has a low-pass filtering effect, and filters high-frequency and noise components in the error signal;
a filter configured to low-pass filter a first-order mixing output of the VCO loop to filter out a noise component;
and the frequency doubler is configured to double the frequency of the 4.8GHz signal to obtain 9.6GHz, and output the frequency doubler to the broadband prescaler.
A VCO driving circuit configured to drive a VCO operation;
a VCO, a voltage controlled oscillator;
the fourth mixer is used for carrying out primary mixing on the signal output by the VCO and the signal output by the broadband prescaler to obtain 4.7GHz or 4.9GHz;
a wideband prescaler configured to output a first stage fixed down-converted local oscillator of the VCO loop.
3. A multi-stage down-conversion frequency synthesis method is characterized in that: the multi-stage down-conversion frequency synthesis apparatus according to claim 2, comprising:
step 1: setting an external high-purity frequency source, and providing frequencies of 4.8GHz and 100MHz;
step 2: judging whether to mix with 2.4GHz generated by the two frequency dividers to obtain a phase discrimination frequency according to the frequency band of the YTO output frequency; the method comprises the following specific steps:
if f is YTO If the frequency is less than or equal to 7.6GHz, the signal output by the YTO and the signal output by the VCO ring are subjected to frequency mixing through a second frequency mixer, and the frequency after frequency mixing is subjected to phase discrimination through a second single-pole double-throw switch and a first single-pole double-throw switch and is output to a first phase discriminator;
if f is YTO If the frequency is more than 7.6GHz, the signal output by the YTO and the signal output by the VCO ring are mixed by the second mixer, the frequency after mixing is mixed by the second single-pole double-throw switch and the output frequency 2.4GHz of the 4.8GHz reference signal after passing through the first power divider and the two frequency dividers by the first mixer, and the frequency after mixing is subjected to phase discrimination frequency obtained by the first single-pole double-throw switch and is output to the first phase discriminator;
and step 3: acquiring a YTO ring phase demodulation reference frequency;
4.8GHz reference signals pass through a first power divider and a decimal frequency divider to obtain phase discrimination reference frequency of a YTO ring;
and 4, step 4: selecting a fixed tuning local oscillation point of the VCO ring according to the YTO frequency;
and 5: the 4.8GHz reference signal passes through a second power divider, a frequency doubler and a broadband prescaler to obtain the first-stage mixing output frequency of the VCO ring;
and 6: the VCO and the first-stage mixing output frequency are mixed through a fourth mixer, the mixed frequency passes through a filter, enters a third mixer with a 4.8GHz reference signal through a signal output by a second power divider to be mixed, the mixed frequency is mixed to obtain a 100MHz phase discrimination frequency, and enters a second phase discriminator with the 100MHz reference signal; the second phase discriminator is used for carrying out phase frequency discrimination on the 100MHz reference signal and the 100MHz phase discrimination frequency and outputting the phase frequency discrimination to the second integrating circuit;
and 7: the VCO driving circuit and the second phase detection integration control the locking of the VCO loop through the output of the second integration circuit.
4. The method of multi-stage down-conversion frequency synthesis of claim 3, wherein: the frequency range of YTO is 4-10GHz and the frequency range of VCO is 4-8 GHz.
CN202211315298.6A 2022-10-26 2022-10-26 Multistage down-conversion frequency synthesis device and method Pending CN115622556A (en)

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