CN115621124A

CN115621124A - Preparation method of insulated gate bipolar transistor

Info

Publication number: CN115621124A
Application number: CN202211197169.1A
Authority: CN
Inventors: 孙向东
Original assignee: GTA Semiconductor Co Ltd
Current assignee: GTA Semiconductor Co Ltd
Priority date: 2022-09-29
Filing date: 2022-09-29
Publication date: 2023-01-17

Abstract

The application relates to a preparation method of an insulated gate bipolar transistor, which comprises the following steps: providing a first substrate and a second substrate, wherein the first substrate comprises a first surface; injecting the first substrate from the first surface of the first substrate to form a back structure of the insulated gate bipolar transistor; forming a sacrificial layer on the second substrate; bonding a second substrate to the side of the first substrate on which the back structure is formed through the sacrificial layer; forming a front structure of the insulated gate bipolar transistor on one side of the first substrate far away from the second substrate; and removing the sacrificial layer to separate the second substrate from the first substrate. The manufacturing process of the back structure is simpler, and the equipment cost for manufacturing the back structure of the insulated gate bipolar transistor is reduced.

Description

Preparation method of insulated gate bipolar transistor

Technical Field

The application relates to the technical field of semiconductors, in particular to a preparation method of an insulated gate bipolar transistor.

Background

With the development of semiconductor technology, the conventional reverse conducting type insulated gate bipolar transistor structure has the characteristic of extremely thin thickness.

However, the conventional reverse conducting type insulated gate bipolar transistor structure has the problems that the difficulty of the back surface process (including high-energy injection and high-temperature annealing) is too high, and the processing equipment of the back surface structure is expensive.

Disclosure of Invention

Therefore, it is necessary to provide a method for manufacturing an insulated gate bipolar transistor, which aims at the problems in the conventional technology that the difficulty of the back surface process is too high and the processing equipment of the back surface structure is expensive.

In order to achieve the above object, the present application provides a method for manufacturing an insulated gate bipolar transistor, which includes providing a first substrate and a second substrate, where the first substrate includes a first surface;

injecting the first substrate from the first surface of the first substrate to form a back structure of the insulated gate bipolar transistor;

forming a sacrificial layer on the second substrate;

bonding the second substrate to the side of the first substrate on which the back structure is formed through the sacrificial layer;

forming a front structure of the insulated gate bipolar transistor on one side of the first substrate far away from the second substrate;

and removing the sacrificial layer to separate the second substrate from the first substrate.

According to the preparation method of the insulated gate bipolar transistor, the back structure of the insulated gate bipolar transistor is completed on the first surface of the first substrate before the front structure of the insulated gate bipolar transistor is completed on the first substrate, so that the manufacturing process of the back structure is simpler, and the equipment cost for manufacturing the back structure of the insulated gate bipolar transistor is reduced.

The sacrificial layer may facilitate bonding and separation of the first substrate from the second substrate. Meanwhile, the sacrificial layer separates the second substrate from the back structure formed on the first substrate, so that the back structure formed on the first substrate can be effectively prevented from being accidentally damaged in the process of removing the second substrate.

In one embodiment, the sacrificial layer includes a first oxide layer, and the forming of the sacrificial layer on the second substrate includes the following steps:

and carrying out thermal oxidation treatment on the second substrate to form the first oxide layer on the surface of the second substrate.

In one embodiment, removing the sacrificial layer to separate the second substrate from the first substrate comprises:

thinning one side of the second substrate far away from the first substrate;

removing the remaining portion of the second substrate by a first etching solution;

and removing the sacrificial layer by using a second corrosive liquid.

In one embodiment, the thinning the side of the second substrate away from the first substrate includes:

and mechanically thinning one side of the second substrate far away from the first substrate.

In one embodiment, the first substrate is implanted from the first surface thereof to form a back structure of the igbt, including the following steps:

performing ion implantation on the first substrate from the first surface of the first substrate to form a buffer layer;

forming an injection blocking layer on the surface of the buffer layer, wherein an opening is formed in the injection blocking layer, and the buffer layer is exposed out of the opening;

performing ion implantation on the buffer layer based on the implantation barrier layer to form an N-type short-circuit region at the bottom of the buffer layer;

and removing the injection blocking layer, and carrying out ion injection on the buffer layer and the N-type short circuit region to form a P-type doped region at the bottom of the buffer layer. In one embodiment, forming an implantation blocking layer on the surface of the buffer layer includes the following steps:

forming an injection blocking material layer on the buffer layer;

forming a patterned photoresist on the injection barrier material layer;

and etching the injection barrier material layer based on the patterned photoresist, and forming the injection barrier layer on the surface of the buffer layer.

In one embodiment, the injection blocking material layer includes a second oxide layer, and the injection blocking material layer is formed on the buffer layer, including the following steps:

and carrying out thermal oxidation treatment on the buffer layer to form the second oxide layer on the surface of the buffer layer.

In one embodiment, the injection blocking material layer further includes a third oxide layer, and before forming the buffer layer on the first surface of the first substrate, the method further includes the following steps:

performing thermal oxidation treatment on the first substrate to form the third oxide layer on the first surface of the first substrate;

the thickness of the third oxidation layer is smaller than that of the second oxidation layer, and after the buffer layer is subjected to thermal oxidation treatment, the second oxidation layer is located between the third oxidation layer and the buffer layer.

In one embodiment, before forming the front structure of the igbt on the side of the first substrate away from the first surface, the method includes the following steps:

and thinning one side of the first substrate, which is far away from the second substrate.

In one embodiment, thinning the side of the first substrate away from the second substrate includes:

mechanically thinning one side of the first substrate, which is far away from the second substrate;

and carrying out chemical mechanical polishing on the first substrate after the mechanical thinning.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a flowchart of a method for manufacturing an insulated gate bipolar transistor provided in an embodiment;

fig. 2 to 12 are schematic cross-sectional structures of structures obtained by the method for manufacturing an igbt according to an embodiment;

description of the reference numerals: 10-a first substrate, 20-a back structure, 21-a buffer layer, 22-an N-type short-circuit region, 23-a P-type doped region, 31-an injection blocking material layer, 311-a second oxide layer, 312-a third oxide layer, 30-an injection blocking layer, 40-a patterned photoresist, 50-a collector layer, 60-a front structure, 70-a second substrate and 80-a sacrificial layer.

Detailed Description

To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Embodiments of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relational terms, such as "under," "below," "under," "over," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. In addition, the device may comprise additional orientations (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.

As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising," "includes" or "including," etc., specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and/or" includes any and all combinations of the associated listed items.

In one embodiment, referring to fig. 1, a method for manufacturing an insulated gate bipolar transistor is provided, which includes the following steps:

step S10, providing a first substrate 10 and a second substrate 70, wherein the first substrate 10 comprises a first surface;

step S20, injecting the first substrate 10 from the first surface thereof to form a back structure 20 of the igbt; step S30, forming a sacrificial layer 80 on the second substrate 70;

step S40, bonding the second substrate 70 to the side of the first substrate 10 on which the back structure 20 is formed, through the sacrificial layer 80;

step S60, forming a front structure 60 of the igbt on a side of the first substrate 10 away from the second substrate 70;

in step S70, the sacrificial layer 80 is removed, and the second substrate 70 is separated from the first substrate 10.

In step S10, the first substrate 10 and/or the second substrate 70 may include, but are not limited to, a silicon wafer.

The first substrate 10 is used for carrying and forming a device structure of an insulated gate bipolar transistor, and the front surface of the first substrate 10 may be a smooth surface, and the smooth surface may serve as a first surface. The second substrate 70 is used to support the first substrate 10 and the back side structure 20 of the igbt formed on the first substrate 10, so as to facilitate further processing to form the front side structure 60 of the igbt.

As an example, the first substrate 10 may be an N-type zone-melting single crystal wafer, which may have a surface area of eight inches, a thickness of 700 μm, and a resistivity of 100 Ω cm. The thickness of the second substrate 70 may be 700 μm.

In step S20, referring to fig. 7, the back side structure 20 of the igbt includes a buffer layer 21, an N-type short circuit region 22, and a P-type doped region 23.

Specifically, when implanting the first substrate 10, phosphorus ion implantation may be first performed from the first surface of the first substrate 10 to form the buffer layer 21. Then, arsenic ion implantation is performed on the buffer layer 21 to form the N-type short-circuiting region 22. Finally, boron ion implantation is performed on the buffer layer 21 and the N-type short-circuit region 22 to form a P-type doped region 23.

In step S30, referring to fig. 8, the material of the sacrificial layer 80 may include silicon dioxide, silicon nitride, or silicon oxynitride. The sacrificial layer 80 may be formed by thermal oxidation or deposition. The Deposition process may include, but is not limited to, one or more of a Chemical Vapor Deposition (CVD) process, an Atomic Layer Deposition (ALD) process, a High Density Plasma (HDP) process, a Plasma enhanced Deposition (pecvd) process, and a Spin-on Dielectric (SOD) process.

In step S40, referring to fig. 8, the second substrate 70 is bonded to the first substrate 10. Specifically, the sacrificial layer 80 formed on the surface of the second substrate 70 and the backside structure 20 formed on the first substrate 10 are bonded to each other.

In step S60, referring to fig. 9, the front structure 60 of the igbt is formed on a side of the first substrate 10 away from the second substrate 70. The method for forming the front structure 60 is the same as that of the conventional art, and is not described herein again.

In step S70, referring to fig. 9 to 11, the second substrate 70 is required to be separated from the first substrate 10 in this step as a supporting substrate. Specifically, the first substrate 10 may be separated from the second substrate 70 by removing the sacrificial layer 80 by wet and/or dry etching or the like.

Referring to fig. 12, step S70 may further include:

step S80, the collector layer 50 is formed.

Specifically, the collector layer 50 may be formed by sputtering a metal, which may be one or more of aluminum, titanium, nickel, and silver.

In the embodiment, the back structure 20 of the igbt is completed on the first surface of the first substrate 10 before the back structure 60 of the igbt is completed on the first substrate 10, so that the manufacturing process of the back structure 20 is simpler, and the equipment cost for manufacturing the back structure 20 of the igbt is reduced.

The sacrificial layer 80 may facilitate bonding and separation of the first substrate 10 and the second substrate 70. Meanwhile, the sacrificial layer 80 separates the second substrate 70 from the back structure 20 formed on the first substrate 10, so that the back structure 20 formed on the first substrate 10 can be effectively prevented from being accidentally damaged in the process of removing the second substrate 70.

In one embodiment, the sacrificial layer 80 comprises a first oxide layer, and the step S30 comprises the steps of:

step S31, a thermal oxidation process is performed on the second substrate 70 to form a first oxide layer on the surface of the second substrate 70.

As an example, the first oxide layer may have a thickness of

To is that

For example, can be

Specifically, by performing the thermal oxidation process on the second substrate 70, the first oxide layer may be formed on both the front surface and the back surface of the second substrate 70. One of the faces (front or back) can then be selected to bond to the first substrate 10 through the first oxide layer of that face.

Of course, the forming method of the sacrificial layer 80 is not limited thereto, and in other cases, the sacrificial layer 80 may also be formed by deposition or the like, which is not limited herein.

In one embodiment, referring to fig. 9 to 11, step S70 includes the following steps:

step S71, thinning the side of the second substrate 70 far away from the first substrate 10;

in step S72, the remaining portion of the second substrate 70 is removed by the first etching solution.

In step S73, the sacrificial layer 80 is removed by the second etching solution.

In step S71, referring to fig. 9, as an example, when thinning the side of the second substrate 70 away from the first substrate 10, mechanical thinning may be performed. Of course, other ways (such as chemical mechanical polishing) can be used to thin the side of the second substrate 70 away from the first substrate 10, which is not limited herein.

In step S72, referring to fig. 10, the remaining portion of the second substrate 70 may be wet-etched and removed by using a first etching solution, where the first etching solution is a chemical solution having an etching effect on the second substrate 70.

In step S73, referring to fig. 11, the sacrificial layer 80 is wet etched and removed by a second etching solution, and at this time, the second etching solution is a chemical solution having an etching effect on the sacrificial layer 80. The first etching solution and the second etching solution are different solutions.

For example, when the sacrificial layer 80 is a silicon dioxide layer, hydrofluoric acid (HF) may be selected as the second etching solution.

In this embodiment, the second substrate 70 is first thinned, so that the thickness of the second substrate 70 can be rapidly reduced. Furthermore, after the second substrate 70 is thinned, the remaining part of the second substrate 70 is removed by using the first etching solution, so that mechanical damage to the back structure 20 on the first substrate 10 due to excessive thinning can be avoided.

Meanwhile, the second substrate 70 has a sacrificial layer 80 between the first substrate 10. The sacrificial layer 80 is removed by the second etching solution, so that the first etching solution can be effectively prevented from etching the remaining part of the second substrate 70 and simultaneously causing an etching effect on the back structure 20 of the first substrate 10, thereby better protecting the back structure 20 of the first substrate 10.

In one embodiment, referring to fig. 3 to 7, the step S20 includes the following steps:

step S21, referring to fig. 3, performing ion implantation on the first surface of the first substrate 10 to form a buffer layer 21;

step S22, referring to fig. 6, forming an injection blocking layer 30 on the surface of the buffer layer 21, where the injection blocking layer 30 has an opening therein, and the opening exposes the buffer layer 21;

step S23, referring to fig. 6 and 7, performing ion implantation on the buffer layer 21 based on the implantation blocking layer 30 to form an N-type short-circuit region 22 at the bottom of the buffer layer 21;

in step S24, referring to fig. 7, the implantation blocking layer 30 is removed, and ion implantation is performed on the buffer layer 21 and the N-type short-circuit region 22 to form a P-type doped region 23 at the bottom of the buffer layer 21.

In step S21, the first substrate 10 may be implanted with a phosphorus element from the first surface thereof, and specifically, the implantation dose may be 5E12 to 3E13/cm ² The implantation energy may be 80 to 120KeV. Then, the first substrate 10 may be sent to a high temperature furnace tube for thermal process propulsion to form the buffer layer 21.

In step S22, a patterned photoresist 40 is formed on the buffer layer 21, and an implantation barrier layer 30 is formed based on the patterned photoresist etching, wherein the implantation barrier layer 30 has an opening exposing the buffer layer 21 and defining the size and the position of the N-type short-circuit region 22.

In step S23, the buffer layer 21 may be implanted with arsenic ions based on the implantation barrier layer 30, and the implantation dose may be 1E 15-3E 15/cm ² The implantation energy may be 100 to 150KeV, thereby forming the N-type short circuit region 22 at the bottom of the buffer layer 21.

In step S24, the implantation barrier layer 30 may be removed by etching. Then, the buffer layer 21 and the N-type short circuit region 22 may be subjected to boron ion implantation over the entire surface at an implantation dose of 1E 13-5E 13/cm ² The implantation energy may be 30 to 50KeV, thereby forming the P-type doped region 23 at the bottom of the buffer layer 21.

In the present embodiment, forming the implantation blocking layer 30 having the implantation opening on the surface of the buffer layer 21 may facilitate the formation of the N-type short-circuiting region 22.

In one embodiment, referring to fig. 4 to 6, step S22 includes the following steps:

step S221, referring to fig. 4, forming an injection blocking material layer 31 on the buffer layer 21;

step S222, referring to fig. 5, forming a patterned photoresist 40 on the implantation barrier material layer 31;

in step S223, referring to fig. 6, the implantation barrier material layer 30 is etched based on the patterned photoresist 40, and the implantation barrier layer 30 is formed on the surface of the buffer layer 21.

In step S221, referring to fig. 4, the thickness of the second oxide layer 311 may be greater than 1 μm. For example, the thickness of the second oxide layer 311 may be 1 μm to 1.5 μm.

As an example, the injection blocking material layer 30 may include a second oxide layer 311. At this time, the step may include: the buffer layer 21 is subjected to thermal oxidation treatment, and a second oxide layer 311 is formed on the surface of the buffer layer 21.

Specifically, at this time, after the ion implantation is performed from the first surface of the first substrate 10, the first substrate 10 may be first sent into a high-temperature furnace tube to be thermally pushed and trapped, so as to form the buffer layer 21, and then the buffer layer 21 after being pushed and trapped may be thermally oxidized in the high-temperature furnace tube, so as to form the second oxide layer 311.

Of course, the implantation barrier material layer 30 may be formed by other methods, such as deposition, but is not limited thereto.

In step S222, referring to fig. 5, a photoresist is first coated on the implantation blocking layer 30, and then the photoresist is exposed and developed to form a patterned photoresist 40.

In step S223, referring to fig. 6, the implantation barrier material layer 30 may be dry etched based on the patterned photoresist 40, so as to form the implantation barrier layer 30 with a controllable opening shape.

In the present embodiment, the implantation stopper layer 30 having the implantation opening is formed simply and efficiently by the processes such as photolithography and etching.

In one embodiment, referring to fig. 2 to 3, the implanted blocking material layer 31 further includes a third oxide layer 312, and the step S21 further includes the following steps:

referring to fig. 2, a thermal oxidation process is performed on the first substrate 10 to form a third oxide layer 312 on the first substrate 10.

After the first substrate 10 is processed, the third oxide layer 312 may be formed on both the front surface and the back surface.

Referring to fig. 3, the thickness of the third oxide layer 312 is smaller than that of the second oxide layer 311. Specifically, the thickness of the third oxide layer 312 may be

To

For example, can be

The thickness of the second oxide layer 311 may be greater than 1 μm, for example.

At this time, due to the existence of the third oxide layer 312, a tunneling effect can be effectively prevented in the ion implantation process in step S21, so that the thickness of the buffer layer 21 formed by implantation is more uniform. Meanwhile, the third oxide layer 312 can effectively prevent the first substrate 10 from being damaged during the implantation process.

Meanwhile, since the third oxide layer 312 has a small thickness, oxidation may enter the buffer layer 21 through the third oxide layer 312. Therefore, after the third oxide layer 312 and the buffer layer 21 are formed, the subsequent steps may continue to form the second oxide layer 311 on the surface of the buffer layer 21 by thermal oxidation.

After the buffer layer 21 is subjected to the thermal oxidation process, the second oxide layer 311 is located between the third oxide layer 312 and the buffer layer 21.

In one embodiment, step S60 is preceded by the steps of:

in step S50, a side of the first substrate 10 away from the second substrate 70 is thinned, please refer to fig. 7 and fig. 8.

In this embodiment, the first substrate 10 is thinned, so that the overall thickness of the chip can be reduced to some extent, and a reverse conducting insulated gate bipolar transistor structure with a smaller thickness can be formed.

In one embodiment, step S50 includes the steps of:

step S51, mechanically thinning the side of the first substrate 10 far away from the second substrate 70;

step S52, performing chemical mechanical polishing on the mechanically thinned first substrate 10.

In step S51, the first substrate 10 is mechanically thinned, so that the thinning cost can be reduced.

In step S52, the surface of the first substrate 10 is planarized using a chemical mechanical polishing process, so that the operation performance and reliability of the device can be optimized.

In this embodiment, thinning the first substrate 10 can effectively reduce the thickness of the chip. In addition, the first substrate 10 after mechanical thinning can be polished chemically and mechanically to form a smooth and flat surface, on which the front structure 60 of the igbt can be formed better.

It should be understood that, although the steps in the flowchart of fig. 1 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a part of the steps in fig. 1 may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or stages is not necessarily performed in sequence, but may be performed alternately or alternately with other steps or at least a part of the steps or stages in other steps.

In the description herein, references to the description of "some embodiments," "other embodiments," "desired embodiments," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, a schematic description of the above terminology may not necessarily refer to the same embodiment or example.

All the possible combinations of the technical features of the embodiments described above may not be described for the sake of brevity, but should be considered as being within the scope of the present disclosure as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A preparation method of an insulated gate bipolar transistor is characterized by comprising the following steps:

providing a first substrate and a second substrate, wherein the first substrate comprises a first surface;

forming a sacrificial layer on the second substrate;

bonding the second substrate to the first substrate through the sacrificial layer at a side where the backside structure is formed;

2. The method of claim 1, wherein the sacrificial layer comprises a first oxide layer, and wherein the forming the sacrificial layer on the second substrate comprises:

3. The method of manufacturing an insulated gate bipolar transistor according to claim 1, wherein removing the sacrificial layer to separate the second substrate from the first substrate comprises:

thinning one side of the second substrate, which is far away from the first substrate;

and removing the sacrificial layer by using a second corrosive liquid.

4. The method for manufacturing the insulated gate bipolar transistor according to claim 3, wherein the thinning the second substrate on the side away from the first substrate comprises:

5. The method according to claim 1, wherein the step of implanting the first substrate from the first surface thereof to form the back side structure of the igbt comprises the steps of:

forming an injection blocking layer on the surface of the buffer layer, wherein the injection blocking layer is internally provided with an opening, and the opening exposes the buffer layer;

and removing the injection blocking layer, and carrying out ion injection on the buffer layer and the N-type short circuit region to form a P-type doped region at the bottom of the buffer layer.

6. The method for manufacturing the insulated gate bipolar transistor according to claim 5, wherein an injection blocking layer is formed on the surface of the buffer layer, and the method comprises the following steps:

forming an injection blocking material layer on the buffer layer;

forming a patterned photoresist on the injection barrier material layer;

7. The method of claim 6, wherein the implanted blocking material layer comprises a second oxide layer, and the step of forming the implanted blocking material layer on the buffer layer comprises the steps of:

8. The method of claim 7, wherein the implanted blocking material layer further comprises a third oxide layer, and further comprising the following steps before forming the buffer layer on the first surface of the first substrate:

9. The method according to claim 1, wherein before the front structure of the igbt is formed on the side of the first substrate away from the first surface, the method includes the following steps:

10. The method for manufacturing the insulated gate bipolar transistor according to claim 9, wherein the thinning of the side of the first substrate away from the second substrate comprises the following steps: