CN115617115B - Reference voltage generating circuit, chip and electronic equipment - Google Patents

Reference voltage generating circuit, chip and electronic equipment Download PDF

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Publication number
CN115617115B
CN115617115B CN202211344115.3A CN202211344115A CN115617115B CN 115617115 B CN115617115 B CN 115617115B CN 202211344115 A CN202211344115 A CN 202211344115A CN 115617115 B CN115617115 B CN 115617115B
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transistor
circuit
current
reference voltage
voltage
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CN115617115A (en
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赵东艳
李明节
王于波
李振国
原义栋
胡毅
赵天挺
侯佳力
王亚彬
苏萌
刘宇
常乃超
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State Grid Corp of China SGCC
Beijing Smartchip Microelectronics Technology Co Ltd
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State Grid Corp of China SGCC
Beijing Smartchip Microelectronics Technology Co Ltd
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Priority to PCT/CN2023/122790 priority patent/WO2024093602A1/en
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)

Abstract

The disclosure relates to the technical field of integrated circuits, in particular to a reference voltage generating circuit, a chip and electronic equipment, wherein the reference voltage generating circuit comprises: a reference voltage generation circuit for generating a first reference voltage; the voltage stabilizing circuit comprises a voltage converting circuit, a pulling current voltage stabilizing branch circuit and a filling current voltage stabilizing branch circuit, wherein: the voltage conversion circuit is used for converting the first reference voltage into the reference voltage, converting the reference voltage into a first control voltage when the reference voltage generation circuit receives external pulling current, and converting the reference voltage into a second control voltage when the reference voltage generation circuit receives external pouring current; the current-drawing voltage stabilizing branch circuit receives the first control voltage, and the current-filling voltage stabilizing branch circuit receives the second control voltage so as to stabilize the reference voltage, thereby improving the reliability of the circuit.

Description

Reference voltage generating circuit, chip and electronic equipment
Technical Field
The disclosure relates to the technical field of integrated circuits, and in particular relates to a reference voltage generating circuit, a reference voltage generating chip and an electronic device.
Background
Reference voltage generating circuits such as bandgap reference sources are widely used in integrated circuits to provide a process, voltage and temperature independent voltage that can be used in modules and chips such as data converters, reference voltage sources, large scale analog to digital (SoC) chips.
In a high-precision data acquisition system in the industrial field, the sampling precision of a chip and the variation of the sampling precision along with the load are seriously dependent on a high-precision reference source on the chip, so that in order to ensure that the amplitude of the absolute sampling precision along with the load variation is reduced when the chip works in a wide load range, a reference voltage generation circuit with both pull current and current filling is required to be developed, and the problem that the sampling precision is reduced due to the reference voltage variation caused by the load variation of the high-precision sampling system is solved.
Disclosure of Invention
In order to solve the problems in the related art, embodiments of the present disclosure provide a reference voltage generating circuit, a chip, and an electronic device.
In a first aspect, embodiments of the present disclosure provide a reference voltage generating circuit, a chip, and an electronic device.
Specifically, the reference voltage generation circuit includes:
a reference voltage generation circuit for generating a first reference voltage that does not vary with process and temperature;
The voltage stabilizing circuit comprises a voltage converting circuit, a pulling current voltage stabilizing branch circuit and a filling current voltage stabilizing branch circuit, wherein:
the voltage conversion circuit is used for converting the first reference voltage into the reference voltage, converting the reference voltage into a first control voltage when the reference voltage generation circuit receives external pulling current, and converting the reference voltage into a second control voltage when the reference voltage generation circuit receives external pouring current, wherein the voltage conversion circuit comprises a first transistor MP5 and a second transistor MP6, the first transistor MP5 and the second transistor MP6 are connected through a common grid, the source electrode of the first transistor MP5 is connected with the first reference voltage, the drain electrode of the first transistor MP5 is grounded through a third current source, and the third current source is a current source formed by mirroring the first current; the source electrode of the second transistor MP6 is connected with the reference voltage, and the drain electrode is connected with the input ends of the pull current voltage stabilizing branch circuit and the current filling voltage stabilizing branch circuit;
the pull-current voltage stabilizing branch circuit comprises a third transistor MN6 and a fourth transistor MP8, wherein the source electrode of the third transistor MN6 is connected with the first control voltage, and the drain electrode of the fourth transistor MP8 is connected with the reference voltage so as to stabilize the reference voltage to a rated value when the reference voltage generating circuit receives external pull-current and causes the reference voltage to decrease;
The current-filling voltage stabilizing branch circuit comprises a fifth transistor MN7, wherein the grid electrode of the fifth transistor MN7 is connected with the second control voltage, the drain electrode of the fifth transistor MN is connected with the reference voltage, and when the reference voltage generating circuit receives external current filling, the reference voltage is stabilized to a rated value when the reference voltage is increased.
In an embodiment of the disclosure, the reference voltage generating circuit is further configured to generate a first current.
In an embodiment of the disclosure, the reference voltage generating circuit includes a first bipolar transistor Q1, a second bipolar transistor Q2, a third bipolar transistor Q3, a first resistor R1, a second resistor R2, and a first current mirror circuit; wherein,,
the first bipolar transistor Q1, the second bipolar transistor Q2, the third bipolar transistor Q3, the first resistor R1, and the second resistor R2 are used to generate the first reference voltage, and the first current mirror circuit is used to generate the first current.
In the embodiment of the disclosure, the base and collector of the first bipolar transistor Q1 and the second bipolar transistor Q2 are both grounded, the emitter of the first bipolar transistor Q1 is connected to the first input terminal of the first current mirror circuit, and the emitter of the second bipolar transistor Q2 is connected to the second input terminal of the first current mirror circuit via the first resistor R1;
The reference voltage generating circuit further comprises a second current source, the base electrode and the collector electrode of the third bipolar transistor Q3 are grounded, the emitter electrode is connected to the second current source and the source electrode of the first transistor MN5 through the second resistor, the second current source is a current source formed by twice mirror images of the first current, and the other end of the second current source is connected to the power supply voltage.
In the disclosed embodiment, the first transistor MP5 and the second transistor MP6 have the same feature size.
In the embodiment of the disclosure, the drain electrode of the second transistor MP6 is further connected to a fourth current source, where the fourth current source is a current source formed by mirroring twice the first current, and the other end of the fourth current source is grounded.
In the embodiment of the disclosure, the gate of the third transistor MN6 is connected to the first bias voltage, the drain is connected to the gate of the fourth transistor MP8, and the source of the fourth transistor MP8 is connected to the power supply voltage;
the source of the fifth transistor MN7 is grounded.
In the embodiment of the disclosure, the drain electrode of the third transistor MN6 is further connected to a fifth current source, where the fifth current source is a current source formed by mirroring the first current twice, and the other end of the fifth current source is connected to a power supply voltage.
In the disclosed embodiment, the first bias voltage is generated by a bias branch including a sixth current source, a sixth transistor MN8, and a seventh transistor MN9;
the sixth current source is a current source formed by mirroring the first current, one end of the sixth current source is connected to a power supply voltage, and the other end of the sixth current source is connected to the first bias voltage and the drain electrode of the sixth transistor MN 8;
the gate and drain of the sixth transistor MN8 are shorted, and the source is connected to the drain of the seventh transistor MN9;
the gate and drain of the seventh transistor MN9 are shorted, and the source is grounded.
In this embodiment of the disclosure, the first current mirror circuit includes an eighth transistor MN1, a ninth transistor MN2, a tenth transistor MP1, and an eleventh transistor MP2, where a source of the eighth transistor MN1 is a first input terminal of the first current mirror, a source of the ninth transistor MN2 is a second input terminal of the first current mirror, a gate drain of the eighth transistor MN1 is shorted and connected to a gate of the ninth transistor MN2 and a drain of the tenth transistor MP1, a gate drain of the eleventh transistor MP2 is shorted and connected to a gate of the tenth transistor MP1 and a drain of the ninth transistor MN2, and sources of the tenth transistor MP1 and the eleventh transistor MP2 are both connected to a power supply voltage.
In the embodiment of the disclosure, the second current source includes a twelfth transistor MP3, where a gate of the twelfth transistor MP3 is connected to a gate of the eleventh transistor MP2, a drain is connected to the second resistor R2, and a source is connected to a power supply voltage.
In an embodiment of the disclosure, the third current source includes a thirteenth transistor MP4, a fourteenth transistor MN3, and a fifteenth transistor MN4, wherein a gate of the thirteenth transistor MP4 is connected to a gate of the twelfth transistor MP3, a drain is connected to a drain of the fourteenth transistor MN3, and a source is connected to a power supply voltage; the gate and drain of the fourteenth transistor MN3 are shorted and connected to the gate of the fifteenth transistor MN4, the sources of the fourteenth transistor MN3 and the fifteenth transistor MN4 are grounded, and the drain of the fifteenth transistor MN4 is connected to the drain of the first transistor MP5 as one end of the third current source.
In the embodiment of the disclosure, the fourth current source includes a sixteenth transistor MN5, the gate of the sixteenth transistor MN5 is connected to the gate of the fifteenth transistor MN4, the drain serving as one end of the fourth current source is connected to the drain of the second transistor MP6, and the source is grounded.
In the embodiment of the disclosure, the fifth current source includes a seventeenth transistor MP7, the gate of the seventeenth transistor MP7 is connected to the gate of the twelfth transistor MP2, the drain serving as the fifth current source is connected to the drain of the third transistor MN6, and the source is connected to the power supply voltage.
In the embodiment of the disclosure, the sixth current source includes an eighteenth transistor MP9, the gate of the eighteenth transistor MP9 is connected to the gate of the twelfth transistor MP2, the drain serving as the sixth current source is connected to the drain of the sixth transistor MN8, and the source is connected to the power supply voltage.
In the embodiment of the disclosure, the transistors MP1, MP2, MP4, MP7, and MP9 have the same feature size, the transistor MP3 has twice the feature size of the transistor MP1, the transistors MN3 and MN4 have the same feature size, and the transistor MN5 has twice the feature size of the transistor MN 3.
In a second aspect, embodiments of the present disclosure provide a chip comprising a reference voltage generating circuit as claimed in any one of the first aspects.
In a third aspect, embodiments of the present disclosure provide an electronic device comprising a chip as described in the second aspect.
According to the technical scheme provided by the embodiment of the disclosure, the voltage stabilizing circuit comprising the current pulling voltage stabilizing branch circuit and the current filling voltage stabilizing branch circuit is additionally arranged in the reference voltage generating circuit, so that the reference voltage can be quickly stabilized to the rated value when the reference voltage generating circuit receives external current pulling to reduce the reference voltage and when the reference voltage is increased due to external current filling, and the reliability of the circuit is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
Other features, objects and advantages of the present disclosure will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings. In the drawings.
Fig. 1 shows a block diagram of a reference voltage generating circuit in the prior art.
Fig. 2 shows a block diagram of a reference voltage generation circuit according to an embodiment of the present disclosure.
Fig. 3 illustrates a block diagram of a reference voltage generating circuit according to an embodiment of the present disclosure.
Fig. 4 shows a block diagram of an electronic device according to an embodiment of the disclosure.
Fig. 5 shows a block diagram of a chip according to an embodiment of the disclosure.
Detailed Description
Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement them. In addition, for the sake of clarity, portions irrelevant to description of the exemplary embodiments are omitted in the drawings.
In this disclosure, it should be understood that terms such as "comprises" or "comprising," etc., are intended to indicate the presence of features, numbers, steps, acts, components, portions, or combinations thereof disclosed in this specification, and are not intended to exclude the possibility that one or more other features, numbers, steps, acts, components, portions, or combinations thereof are present or added.
In addition, it should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
In the above-mentioned high-precision data acquisition system in the industrial field, the sampling precision of the chip and the variation of the sampling precision along with the load are seriously dependent on the high-precision reference source on the chip, so as to ensure that the amplitude of the absolute sampling precision along with the load variation is reduced when the chip works in a wide load range, it is highly required to develop a reference voltage generation circuit with both pull current and fill current, so as to solve the problem that the sampling precision is reduced due to the reference voltage variation caused by the load variation faced by the high-precision sampling system.
Fig. 1 shows a block diagram of a reference voltage generating circuit in the prior art. As shown in fig. 1, the circuit composed of bipolar transistor, resistor and error amplifier can provide a bandgap reference voltage which does not change with process and temperature, and has a certain forward driving capability due to the existence of metal oxide field effect MOS transistor. Under the condition that the reference voltage generating circuit receives external pulling current, the MOS tube can play a role in stabilizing voltage and quickly recover the reference voltage; however, under the condition that the reference voltage generating circuit receives external current, the reference voltage can be repaired and stabilized only by means of a resistor, the recovery time is long, the voltage overshoot duration caused by the current is long at the moment, adverse effects are easily caused on devices in the circuit, the service life of the devices is shortened, even the devices are damaged, and the reliability of the circuit is low.
In view of this, the embodiment of the present disclosure provides a reference voltage generating circuit including: a reference voltage generation circuit for generating a first reference voltage that does not vary with process and temperature; the voltage stabilizing circuit comprises a voltage converting circuit, a pulling current voltage stabilizing branch circuit and a filling current voltage stabilizing branch circuit, wherein: the voltage conversion circuit is used for converting the first reference voltage into the reference voltage, converting the reference voltage into a first control voltage when the reference voltage generation circuit receives external pulling current, and converting the reference voltage into a second control voltage when the reference voltage generation circuit receives external pouring current; the current-drawing voltage stabilizing branch circuit receives the first control voltage, so that when the reference voltage generating circuit receives external drawing current and the reference voltage is reduced, the reference voltage is stabilized to a rated value; the current-sinking and voltage-stabilizing branch circuit receives the second control voltage, so that when the reference voltage generating circuit receives external current sinking and leads to the rise of the reference voltage, the reference voltage is stabilized to a rated value. The voltage stabilizing circuit comprising the current pulling voltage stabilizing branch circuit and the current filling voltage stabilizing branch circuit is additionally arranged in the reference voltage generating circuit, so that the reference voltage can be quickly stabilized to a rated value when the reference voltage is reduced due to the fact that the reference voltage generating circuit receives external current pulling and is increased due to the fact that the reference voltage generating circuit receives external current filling, and the reliability of the circuit is improved. Wherein the first control voltage is the same as the second control voltage.
Fig. 2 shows a block diagram of a reference voltage generation circuit according to an embodiment of the present disclosure.
As shown in fig. 2, the reference voltage generating circuit includes:
a reference voltage generation circuit for generating a first reference voltage that does not vary with process and temperature;
the voltage stabilizing circuit comprises a voltage converting circuit, a pulling current voltage stabilizing branch circuit and a filling current voltage stabilizing branch circuit, wherein:
the voltage conversion circuit is used for converting the first reference voltage into the reference voltage, converting the reference voltage into a first control voltage when the reference voltage generation circuit receives external pulling current, and converting the reference voltage into a second control voltage when the reference voltage generation circuit receives external pouring current, wherein the voltage conversion circuit comprises a first transistor MP5 and a second transistor MP6, the first transistor MP5 and the second transistor MP6 are connected through a common grid, the source electrode of the first transistor MP5 is connected with the first reference voltage, the drain electrode of the first transistor MP5 is grounded through a third current source, and the third current source is a current source formed by mirroring the first current; the source electrode of the second transistor MP6 is connected with the reference voltage, and the drain electrode is connected with the input ends of the pull current voltage stabilizing branch circuit and the current filling voltage stabilizing branch circuit;
The pull-current voltage stabilizing branch circuit comprises a third transistor MN6 and a fourth transistor MP8, wherein the source electrode of the third transistor MN6 is connected with the first control voltage, and the drain electrode of the fourth transistor MP8 is connected with the reference voltage so as to stabilize the reference voltage to a rated value when the reference voltage generating circuit receives external pull-current and causes the reference voltage to decrease;
the current-filling voltage stabilizing branch circuit comprises a fifth transistor MN7, wherein the grid electrode of the fifth transistor MN7 is connected with the second control voltage, the drain electrode of the fifth transistor MN is connected with the reference voltage, and when the reference voltage generating circuit receives external current filling, the reference voltage is stabilized to a rated value when the reference voltage is increased.
In the embodiments of the present disclosure, the reference voltage generating circuit may be a bandgap reference voltage generating circuit, where the reference voltage generating circuit generates a bandgap reference first reference voltage, and the first reference voltage does not vary with process and temperature. The reference voltage generating circuit may be a classical circuit composed of two bipolar transistors, a differential amplifier and a plurality of resistors as shown in fig. 1, or may be an improved circuit of the classical circuit. The improved circuit will be described in detail later with reference to fig. 3.
If the first reference voltage generated by the reference voltage generating circuit is directly output as the reference voltage, when the output node receives the external pull circuit or the current filling, the output voltage of the output node is correspondingly reduced or increased, so that the output reference voltage deviates from the rated value of the output node, and the stable reference voltage cannot be provided.
In view of this, in the embodiment of the present disclosure, a voltage stabilizing circuit including a voltage converting circuit, a pull-current voltage stabilizing branch, and a sink-current voltage stabilizing branch is further provided in the reference voltage generating circuit. The voltage conversion circuit is used for converting the first reference voltage into the reference voltage, converting the reference voltage into a first control voltage when the reference voltage generation circuit receives external pull current, and converting the reference voltage into a second control voltage when the reference voltage generation circuit receives external sink current. The current-drawing voltage stabilizing branch circuit receives the first control voltage, so that when the reference voltage generating circuit receives external drawing current and the reference voltage is reduced, the reference voltage is stabilized to a rated value; the current-sinking and voltage-stabilizing branch circuit receives the second control voltage, so that when the reference voltage generating circuit receives external current sinking and leads to the rise of the reference voltage, the reference voltage is stabilized to a rated value.
In the embodiment of the present disclosure, the rated value of the reference voltage refers to a value of the reference voltage required to be provided by the reference voltage generating circuit, and may be, for example, 3.3V, 1.8V, etc., which is not limited herein.
In the embodiment of the disclosure, the current-drawing voltage-stabilizing branch and the current-filling voltage-stabilizing branch both comprise active devices so as to improve the response capability of the branches, and can stabilize the reference voltage which is reduced by current drawing to a rated value and stabilize the reference voltage which is increased by current filling to the rated voltage.
According to the technical scheme of the embodiment of the disclosure, the voltage stabilizing circuit comprising the current pulling voltage stabilizing branch circuit and the current filling voltage stabilizing branch circuit is additionally arranged in the reference voltage generating circuit, so that the reference voltage can be quickly stabilized to the rated value when the reference voltage generating circuit receives external current pulling to reduce the reference voltage and when the reference voltage is increased due to external current filling, and the reliability of the circuit is improved.
In this embodiment of the present disclosure, the reference voltage generating circuit may be further configured to generate a first current, so that each branch in the voltage stabilizing circuit may set its own current source by mirroring the first current, thereby reducing current deviation of each branch, and further improving reliability of the circuit.
Fig. 3 illustrates a block diagram of a reference voltage generating circuit according to an embodiment of the present disclosure.
As shown in fig. 3, the reference voltage generating circuit may include a first bipolar transistor Q1, a second bipolar transistor Q2, a third bipolar transistor Q3, a first resistor R1, a second resistor R2, and a first current mirror circuit; the first bipolar transistor Q1, the second bipolar transistor Q2, the third bipolar transistor Q3, the first resistor R1, and the second resistor R2 are used for generating the first reference voltage, and the first current mirror circuit is used for generating the first current.
Specifically, the bases and collectors of the first bipolar transistor Q1 and the second bipolar transistor Q2 are both grounded, the emitter of the first bipolar transistor Q1 is connected to the first input terminal of the first current mirror circuit, and the emitter of the second bipolar transistor Q2 is connected to the second input terminal of the first current mirror circuit via the first resistor R1. The first current mirror includes an eighth transistor MN1, a ninth transistor MN2, a tenth transistor MP1, and an eleventh transistor MP2, wherein a source electrode of the eighth transistor MN1 is a first input terminal of the first current mirror, a source electrode of the ninth transistor MN2 is a second input terminal of the first current mirror, a gate drain of the eighth transistor MN1 is shorted and connected to a gate electrode of the ninth transistor MN2 and a drain electrode of the tenth transistor MP1, a gate drain of the eleventh transistor MP2 is shorted and connected to a gate electrode of the tenth transistor MP1 and a drain electrode of the ninth transistor MN2, and sources of the tenth transistor MP1 and the eleventh transistor MP2 are both connected to a power supply voltage.
In this embodiment of the disclosure, the reference voltage generating circuit may further include a second current source, where a base and a collector of the third bipolar transistor Q3 are both grounded, an emitter is connected to the second current source and a source of the first transistor MN5 through the second resistor R2, the second current source is a current source formed by mirroring the first current twice, and another end of the second current source is connected to a power supply voltage. In one embodiment of the present disclosure, the second current source may include a twelfth transistor MP3, a gate of the twelfth transistor MP3 is connected to a gate of the eleventh transistor MP2, a drain is connected to the second resistor R2, and a source is connected to a power supply voltage. By reasonably setting the characteristic dimensions of the first bipolar transistor Q1, the second bipolar transistor Q2 and the third bipolar transistor Q3, the emitter-base voltage difference (Veb 1-Veb 2) of the first bipolar transistor Q1 and the second bipolar transistor Q2 with positive temperature coefficient and the emitter-base voltage Veb3 of the third bipolar transistor Q3 with negative temperature coefficient can obtain a first reference voltage Vref1 which does not change with temperature and process.
Specifically, it is assumed that mismatch in the circuit including inter-resistance mismatch, inter-transistor mismatch, and the like, is ignored, the transistor MN1,MN2, MP1 and MP2 constitute a self-bias loop, and the source voltages of MN1 and MN2 are thought of. Since for bipolar transistors the collector current is related to the saturation current as: i C ＝I S *e Veb/Vt Wherein I C Is a collector circuit of a bipolar transistor, I S In the saturated circuit of the bipolar transistor, veb is the emitter-base voltage of the bipolar transistor, vt is the thermal voltage, vt=kt/q, k is the boltzmann constant, T is the absolute temperature, and q is the electron charge.
The bases and collectors of the bipolar transistors Q1, Q2, and Q3 in fig. 3 are all grounded, so the currents of the bipolar transistors Q1, Q2, and Q3 are all: i Q ＝I E ＝I B +I C ＝(1+1/β F )Is*e Veb/Vt Wherein I Q I for the current flowing through the bipolar transistor E Is the emitter current of the bipolar transistor, I B Is the base current of the bipolar transistor. It can further be derived that veb=vt×ln (I Q /(Is*(1+1/β F )))。
The eighth transistor MN1 and the ninth transistor MN2 in fig. 3 are equal in size, and the tenth transistor MP1 and the eleventh transistor MP2 are equal in size, so that the current I flowing through the bipolar transistors Q1 and Q2 Q1 And I Q2 Equal, the emitter-base voltage difference of the two is: Δveb=veb1-veb2=vt×ln ((I) Q1 *I S2 )/(I S1 *I Q2 ) V=vt×lnn, where N is the emitter area ratio of the second bipolar transistor Q2 and the first bipolar transistor Q1, and the ratio of the saturation currents of the first bipolar transistor Q1 and the second bipolar transistor Q2 is: i S1 ：I S2 ＝1：N。
As can be seen from fig. 3, the current in bipolar transistors Q1 and Q2 is equal to the current in first resistor R1, and therefore: i Q1 ＝I Q2 ＝ΔVeb/R1＝Vt*ln(N/R1)。
The sizes of the devices are reasonably set, so that the current generated by the second current source is evenly distributed to the second resistor R2, the third bipolar transistor Q3 branch and the first reference voltage Vref1 output branch, and the current in the second resistor R2 is equal to the current in the first resistor R1, so that the first reference voltage Vref1 for realizing first-order temperature compensation can be obtained: vref1 = veb3+ ((Veb 1-Veb 2)/R1) R2.
In the embodiment of the present disclosure, the first transistor MP5 and the second transistor MP6 may be configured to have the same feature size, so that the currents flowing through the first transistor MP5 and the second transistor MP6 are also equal, and thus the gate-source voltages of the first transistor MP5 and the second transistor MP6 are also equal. In this way, the first reference voltage Vref1 can be copied from the source of the first transistor MP5 to the source of the second transistor MP6 for output without damage, and after the first reference voltage Vref1 is buffered and isolated by the first transistor MP5, the second transistor MP6 is used as a level conversion circuit to generate the first control voltage output to the pull-current voltage stabilizing branch and the second control voltage output to the current-sinking voltage stabilizing branch, thereby improving the reliability of the circuit. The bandgap reference voltage VREF1 with pull current and sink current is obtained by the transistors MP8, MN6 and MN7 as VREF 1=vref 1 1 -V SGMP5 +V SGMP6 Wherein V is SGMP5 For the source gate voltage, V, of the first transistor MP5 SGMP6 Is the source gate voltage of the second transistor MP 6.
In an embodiment of the disclosure, the third current source may include a thirteenth transistor MP4, a fourteenth transistor MN3, and a fifteenth transistor MN4, wherein a gate of the thirteenth transistor MP4 is connected to a gate of the twelfth transistor MP3, a drain is connected to a drain of the fourteenth transistor MN3, and a source is connected to a power supply voltage; the gate and drain of the fourteenth transistor MN3 are shorted and connected to the gate of the fifteenth transistor MN4, the sources of the fourteenth transistor MN3 and the fifteenth transistor MN4 are grounded, and the drain of the fifteenth transistor MN4 is connected to the drain of the first transistor MP5 as one end of the third current source.
In the embodiment of the disclosure, the drain electrode of the second transistor MP6 is further connected to a fourth current source, where the fourth current source is a current source formed by mirroring twice the first current, and the other end of the fourth current source is grounded. Specifically, the fourth current source may include a sixteenth transistor MN5, where a gate of the sixteenth transistor MN5 is connected to a gate of the fifteenth transistor MN4, a drain of the sixteenth transistor is connected to a drain of the second transistor MP6 as one end of the fourth current source, and a source of the fourth current source is grounded.
In the embodiment of the disclosure, the pull-current voltage stabilizing branch includes a third transistor MN6 and a fourth transistor MP8, where a source of the third transistor MN6 is an input terminal of the pull-current voltage stabilizing branch, a gate is connected to the first bias voltage, a drain is connected to the gate of the fourth transistor MP8, a source of the fourth transistor MP8 is connected to the power supply voltage, and a drain is connected to the reference voltage.
In the embodiment of the disclosure, the drain of the third transistor MN6 may be further connected to a fifth current source, where the fifth current source is a current source formed by mirroring the first current twice, and the other end of the fifth current source is connected to a power supply voltage. Specifically, the fifth current source may include a seventeenth transistor MP7, the gate of the seventeenth transistor MP7 is connected to the gate of the twelfth transistor MP2, the drain is connected to the drain of the third transistor MN6 as one end of the fifth current source, and the source is connected to the power supply voltage.
When the reference voltage generating circuit receives an external pull current, the output reference voltage Vref of the reference voltage generating circuit is pulled down, and at this time, the source voltage of the second transistor MP6 is reduced, resulting in an increase in the gate-source voltage of the second transistor MP6, and further, an increase in the leakage current of the second transistor MP 6. Since the current supplied by the fourth current source remains constant, the current flowing through the third transistor MN6 decreases, which in turn causes the drain voltage of the third transistor MN6 to decrease, that is, the gate voltage of the fourth transistor MP8 decreases, so that the fourth transistor MP8 is turned on, and the reference voltage is quickly stabilized to the rated value.
In this embodiment of the disclosure, the current-sinking and voltage-stabilizing branch includes a fifth transistor MN7, where a gate of the fifth transistor MN7 is an input end of the current-sinking and voltage-stabilizing branch, a source is grounded, and a drain is connected to the reference voltage.
When the reference voltage generating circuit receives an external current, the output reference voltage Vref of the reference voltage generating circuit increases, and at this time, the source voltage of the second transistor MP6 increases, which results in the drain voltage of the second transistor MP6 increasing, that is, the gate voltage of the fifth transistor MN7 increases, so that the fifth transistor MN7 is turned on, and the reference voltage is quickly stabilized to the rated value.
According to the technical scheme of the embodiment of the disclosure, the active devices MN6, MP8 and MN7 are adopted to form the current-drawing voltage stabilizing circuit and the current-filling voltage stabilizing circuit, so that the output reference voltage can be stabilized under the current-drawing condition and the current-filling condition, and the response speed is high.
In the disclosed embodiment, the first bias voltage is generated by a bias branch including a sixth current source, a sixth transistor MN8, and a seventh transistor MN9. The sixth current source is a current source formed by mirroring the first current, one end of the sixth current source is connected to a power supply voltage, and the other end of the sixth current source is connected to the first bias voltage and the drain electrode of the sixth transistor MN 8; the gate and drain of the sixth transistor MN8 are shorted, and the source is connected to the drain of the seventh transistor MN 9; the gate and drain of the seventh transistor MN9 are shorted, and the source is grounded. Further, the sixth current source may include an eighteenth transistor MP9, where a gate of the eighteenth transistor MP9 is connected to a gate of the twelfth transistor MP2, a drain of the eighteenth transistor MP9 is connected to a drain of the sixth transistor MN8 as one end of the sixth current source, and a source of the sixth current source is connected to a power supply voltage.
According to the technical scheme of the embodiment of the disclosure, the bias branch is formed by the current source formed by mirroring the first current and the two transistors connected in a diode connection mode in series, so that the first bias voltage is provided for the current-pulling voltage-stabilizing branch, and the structure is simple and the performance is stable.
In the embodiment of the disclosure, the transistors MN1-MN9 may be N-type metal oxide field effect transistors NMOS, and the transistors MP1-MP9 may be P-type metal oxide field effect transistors NMOS. Wherein transistors MP5 and MP6 have the same feature size, transistors MP1, MP2, MP4, MP7 and MP9 have the same feature size, transistor MP3 has twice the feature size of transistor MP1, transistors MN3 and MN4 have the same feature size, and transistor MN5 has twice the feature size of transistor MN 3.
In another embodiment of the present disclosure, the reference voltage generating circuit in the reference voltage generating circuit may be replaced by another reference voltage generating circuit, that is, another reference voltage generating circuit may be combined with the voltage stabilizing circuit in the reference voltage generating circuit to implement the reference voltage generating circuit having both the current drawing and current sinking functions. Those skilled in the art may select different reference voltage generating circuits to be combined with the voltage stabilizing circuit according to the needs of practical applications, and this disclosure will not be described in detail herein.
Fig. 4 shows a block diagram of an electronic device according to an embodiment of the disclosure.
As shown in fig. 4, the electronic device includes a reference voltage generating circuit provided by an embodiment of the present disclosure.
Specifically, the reference voltage generation circuit includes:
a reference voltage generation circuit for generating a first reference voltage that does not vary with process and temperature;
the voltage stabilizing circuit comprises a voltage converting circuit, a pulling current voltage stabilizing branch circuit and a filling current voltage stabilizing branch circuit, wherein:
the voltage conversion circuit is used for converting the first reference voltage into the reference voltage, converting the reference voltage into a first control voltage when the reference voltage generation circuit receives external pulling current, and converting the reference voltage into a second control voltage when the reference voltage generation circuit receives external pouring current;
the pull-current voltage stabilizing branch circuit comprises a third transistor MN6 and a fourth transistor MP8, wherein the source electrode of the third transistor MN6 is connected with the first control voltage, and the drain electrode of the fourth transistor MP8 is connected with the reference voltage so as to stabilize the reference voltage to a rated value when the reference voltage generating circuit receives external pull-current and causes the reference voltage to decrease;
The current-filling voltage stabilizing branch circuit comprises a fifth transistor MN7, wherein the grid electrode of the fifth transistor MN7 is connected with the second control voltage, the drain electrode of the fifth transistor MN is connected with the reference voltage, and when the reference voltage generating circuit receives external current filling, the reference voltage is stabilized to a rated value when the reference voltage is increased.
In an embodiment of the disclosure, the reference voltage generating circuit is further configured to generate a first current.
In an embodiment of the disclosure, the reference voltage generating circuit includes a first bipolar transistor Q1, a second bipolar transistor Q2, a third bipolar transistor Q3, a first resistor R1, a second resistor R2, and a first current mirror circuit; wherein,,
the first bipolar transistor Q1, the second bipolar transistor Q2, the third bipolar transistor Q3, the first resistor R1, and the second resistor R2 are used to generate the first reference voltage, and the first current mirror circuit is used to generate the first current.
In the embodiment of the disclosure, the base and collector of the first bipolar transistor Q1 and the second bipolar transistor Q2 are both grounded, the emitter of the first bipolar transistor Q1 is connected to the first input terminal of the first current mirror circuit, and the emitter of the second bipolar transistor Q2 is connected to the second input terminal of the first current mirror circuit via the first resistor R1;
The reference voltage generating circuit further comprises a second current source, the base electrode and the collector electrode of the third bipolar transistor Q3 are grounded, the emitter electrode is connected to the second current source and the source electrode of the first transistor MN5 through the second resistor, the second current source is a current source formed by twice mirror images of the first current, and the other end of the second current source is connected to the power supply voltage.
In the embodiment of the disclosure, the voltage conversion circuit includes a first transistor MP5 and a second transistor MP6, where the first transistor MP5 and the second transistor MP6 are connected by a common gate, a source of the first transistor MP5 is connected to the first reference voltage, a drain is grounded through a third current source, and the third current source is a current source formed by mirroring the first current; the source electrode of the second transistor MP6 is connected with the reference voltage, and the drain electrode is connected with the input ends of the pull current voltage stabilizing branch circuit and the current filling voltage stabilizing branch circuit.
In the disclosed embodiment, the first transistor MP5 and the second transistor MP6 have the same feature size.
In the embodiment of the disclosure, the drain electrode of the second transistor MP6 is further connected to a fourth current source, where the fourth current source is a current source formed by mirroring twice the first current, and the other end of the fourth current source is grounded.
In the embodiment of the disclosure, the gate of the third transistor MN6 is connected to the first bias voltage, the drain is connected to the gate of the fourth transistor MP8, and the source of the fourth transistor MP8 is connected to the power supply voltage;
the source of the fifth transistor MN7 is grounded.
In the embodiment of the disclosure, the drain electrode of the third transistor MN6 is further connected to a fifth current source, where the fifth current source is a current source formed by mirroring the first current twice, and the other end of the fifth current source is connected to a power supply voltage.
In the disclosed embodiment, the first bias voltage is generated by a bias branch including a sixth current source, a sixth transistor MN8, and a seventh transistor MN9;
the sixth current source is a current source formed by mirroring the first current, one end of the sixth current source is connected to a power supply voltage, and the other end of the sixth current source is connected to the first bias voltage and the drain electrode of the sixth transistor MN 8;
the gate and drain of the sixth transistor MN8 are shorted, and the source is connected to the drain of the seventh transistor MN9;
the gate and drain of the seventh transistor MN9 are shorted, and the source is grounded.
Fig. 5 shows a block diagram of a chip according to an embodiment of the disclosure.
As shown in fig. 5, the chip includes an electronic device provided by an embodiment of the present disclosure, and the electronic device includes a reference voltage generating circuit provided by an embodiment of the present disclosure.
Specifically, the reference voltage generation circuit includes:
a reference voltage generation circuit for generating a first reference voltage that does not vary with process and temperature;
the voltage stabilizing circuit comprises a voltage converting circuit, a pulling current voltage stabilizing branch circuit and a filling current voltage stabilizing branch circuit, wherein:
the voltage conversion circuit is used for converting the first reference voltage into the reference voltage, converting the reference voltage into a first control voltage when the reference voltage generation circuit receives external pulling current, and converting the reference voltage into a second control voltage when the reference voltage generation circuit receives external pouring current;
the pull-current voltage stabilizing branch circuit comprises a third transistor MN6 and a fourth transistor MP8, wherein the source electrode of the third transistor MN6 is connected with the first control voltage, and the drain electrode of the fourth transistor MP8 is connected with the reference voltage so as to stabilize the reference voltage to a rated value when the reference voltage generating circuit receives external pull-current and causes the reference voltage to decrease;
the current-filling voltage stabilizing branch circuit comprises a fifth transistor MN7, wherein the grid electrode of the fifth transistor MN7 is connected with the second control voltage, the drain electrode of the fifth transistor MN is connected with the reference voltage, and when the reference voltage generating circuit receives external current filling, the reference voltage is stabilized to a rated value when the reference voltage is increased.
The foregoing description is only of the preferred embodiments of the present disclosure and description of the principles of the technology being employed. It will be appreciated by those skilled in the art that the scope of the invention referred to in this disclosure is not limited to the specific combination of features described above, but encompasses other embodiments in which any combination of features described above or their equivalents is contemplated without departing from the inventive concepts described. Such as those described above, are mutually substituted with the technical features having similar functions disclosed in the present disclosure (but not limited thereto).

Claims (18)

1. A reference voltage generating circuit, comprising:
a reference voltage generation circuit for generating a first reference voltage that does not vary with process and temperature;
the voltage stabilizing circuit comprises a voltage converting circuit, a pulling current voltage stabilizing branch circuit and a filling current voltage stabilizing branch circuit, wherein:
the voltage conversion circuit is used for converting the first reference voltage into the reference voltage, converting the reference voltage into a first control voltage when the reference voltage generation circuit receives external pulling current, and converting the reference voltage into a second control voltage when the reference voltage generation circuit receives external pouring current, wherein the voltage conversion circuit comprises a first transistor MP5 and a second transistor MP6, the first transistor MP5 and the second transistor MP6 are connected by adopting a common grid, the source electrode of the first transistor MP5 is connected with the first reference voltage, the drain electrode of the first transistor MP5 is grounded through a third current source, and the third current source is a current source formed by mirroring the first current; the source electrode of the second transistor MP6 is connected with the reference voltage, and the drain electrode is connected with the input ends of the pull current voltage stabilizing branch circuit and the current filling voltage stabilizing branch circuit;
The pull-current voltage stabilizing branch circuit comprises a third transistor MN6 and a fourth transistor MP8, wherein the source electrode of the third transistor MN6 is connected with the first control voltage, and the drain electrode of the fourth transistor MP8 is connected with the reference voltage so as to stabilize the reference voltage to a rated value when the reference voltage generating circuit receives external pull-current and causes the reference voltage to decrease;
the current-filling voltage stabilizing branch circuit comprises a fifth transistor MN7, wherein the grid electrode of the fifth transistor MN7 is connected with the second control voltage, the drain electrode of the fifth transistor MN is connected with the reference voltage, and when the reference voltage generating circuit receives external current filling, the reference voltage is stabilized to a rated value when the reference voltage is increased.
2. The circuit of claim 1, wherein the circuit comprises a plurality of capacitors,
the reference voltage generation circuit is also used for generating a first current.
3. The circuit of claim 2, wherein the circuit further comprises a logic circuit,
the reference voltage generating circuit comprises a first bipolar transistor Q1, a second bipolar transistor Q2, a third bipolar transistor Q3, a first resistor R1, a second resistor R2 and a first current mirror circuit; wherein,,
the first bipolar transistor Q1, the second bipolar transistor Q2, the third bipolar transistor Q3, the first resistor R1, and the second resistor R2 are used to generate the first reference voltage, and the first current mirror circuit is used to generate the first current.
4. The circuit of claim 3, wherein the circuit comprises a plurality of transistors,
the base and collector electrodes of the first bipolar transistor Q1 and the second bipolar transistor Q2 are grounded, the emitter electrode of the first bipolar transistor Q1 is connected to the first input end of the first current mirror circuit, and the emitter electrode of the second bipolar transistor Q2 is connected to the second input end of the first current mirror circuit through the first resistor R1;
the reference voltage generating circuit further comprises a second current source, the base electrode and the collector electrode of the third bipolar transistor Q3 are grounded, the emitter electrode is connected to the second current source and the source electrode of the first transistor MP5 through the second resistor R2, the second current source is a current source formed by twice mirror images of the first current, and the other end of the second current source is connected to the power supply voltage.
5. The circuit of claim 4, wherein the circuit further comprises a logic circuit,
the first transistor MP5 and the second transistor MP6 have the same feature size.
6. The circuit of claim 5, wherein the circuit further comprises a logic circuit,
the drain electrode of the second transistor MP6 is further connected to a fourth current source, where the fourth current source is a current source formed by mirroring the first current twice, and the other end of the fourth current source is grounded.
7. The circuit of claim 6, wherein the circuit further comprises a logic circuit,
the gate of the third transistor MN6 is connected to the first bias voltage, the drain is connected to the gate of the fourth transistor MP8, and the source of the fourth transistor MP8 is connected to the power supply voltage;
the source of the fifth transistor MN7 is grounded.
8. The circuit of claim 7, wherein the circuit further comprises a logic circuit,
the drain electrode of the third transistor MN6 is further connected to a fifth current source, where the fifth current source is a current source formed by mirroring the first current twice, and the other end of the fifth current source is connected to a supply voltage.
9. The circuit of claim 8, wherein the circuit further comprises a logic circuit,
the first bias voltage is generated by a bias branch comprising a sixth current source, a sixth transistor MN8 and a seventh transistor MN9;
the sixth current source is a current source formed by mirroring the first current, one end of the sixth current source is connected to a power supply voltage, and the other end of the sixth current source is connected to the first bias voltage and the drain electrode of the sixth transistor MN 8;
the gate and drain of the sixth transistor MN8 are shorted, and the source is connected to the drain of the seventh transistor MN9;
the gate and drain of the seventh transistor MN9 are shorted, and the source is grounded.
10. The circuit of claim 9, wherein the circuit further comprises a logic circuit,
the first current mirror circuit includes an eighth transistor MN1, a ninth transistor MN2, a tenth transistor MP1, and an eleventh transistor MP2, wherein a source electrode of the eighth transistor MN1 is a first input terminal of the first current mirror, a source electrode of the ninth transistor MN2 is a second input terminal of the first current mirror, a gate drain of the eighth transistor MN1 is shorted and connected to a gate of the ninth transistor MN2 and a drain of the tenth transistor MP1, a gate drain of the eleventh transistor MP2 is shorted and connected to a gate of the tenth transistor MP1 and a drain of the ninth transistor MN2, and sources of the tenth transistor MP1 and the eleventh transistor MP2 are both connected to a power supply voltage.
11. The circuit of claim 10, wherein the circuit further comprises a logic circuit,
the second current source includes a twelfth transistor MP3, where a gate of the twelfth transistor MP3 is connected to a gate of the eleventh transistor MP2, a drain is connected to the second resistor R2, and a source is connected to a power supply voltage.
12. The circuit of claim 11, wherein the circuit further comprises a logic circuit,
the third current source includes a thirteenth transistor MP4, a fourteenth transistor MN3, and a fifteenth transistor MN4, wherein a gate of the thirteenth transistor MP4 is connected to a gate of the twelfth transistor MP3, a drain is connected to a drain of the fourteenth transistor MN3, and a source is connected to a power supply voltage; the gate and drain of the fourteenth transistor MN3 are shorted and connected to the gate of the fifteenth transistor MN4, the sources of the fourteenth transistor MN3 and the fifteenth transistor MN4 are grounded, and the drain of the fifteenth transistor MN4 is connected to the drain of the first transistor MP5 as one end of the third current source.
13. The circuit of claim 12, wherein the circuit further comprises a logic circuit,
the fourth current source includes a sixteenth transistor MN5, the gate of the sixteenth transistor MN5 is connected to the gate of the fifteenth transistor MN4, the drain serving as a fourth current source is connected to the drain of the second transistor MP6, and the source is grounded.
14. The circuit of claim 13, wherein the circuit further comprises a logic circuit,
the fifth current source includes a seventeenth transistor MP7, the gate of the seventeenth transistor MP7 is connected to the gate of the twelfth transistor MP3, the drain serving as a fifth current source is connected to the drain of the third transistor MN6, and the source is connected to the power supply voltage.
15. The circuit of claim 14, wherein the circuit further comprises a logic circuit,
the sixth current source includes an eighteenth transistor MP9, the gate of the eighteenth transistor MP9 is connected to the gate of the twelfth transistor MP3, the drain serving as a sixth current source is connected to the drain of the sixth transistor MN8, and the source is connected to the power supply voltage.
16. The circuit of claim 15, wherein the circuit further comprises a logic circuit,
the transistors MP1, MP2, MP4, MP7, and MP9 have the same feature size, the transistor MP3 has twice the feature size of the transistor MP1, the transistors MN3 and MN4 have the same feature size, and the transistor MN5 has twice the feature size of the transistor MN 3.
17. A chip is characterized in that,
the chip comprising a reference voltage generating circuit as claimed in any one of claims 1 to 16.
18. An electronic device, characterized in that,
the electronic device comprising the chip of claim 17.
CN202211344115.3A 2022-10-31 2022-10-31 Reference voltage generating circuit, chip and electronic equipment Active CN115617115B (en)

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