CN115603729B - Asynchronous TTL serial port to single bus circuit - Google Patents
Asynchronous TTL serial port to single bus circuit Download PDFInfo
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- CN115603729B CN115603729B CN202211594981.8A CN202211594981A CN115603729B CN 115603729 B CN115603729 B CN 115603729B CN 202211594981 A CN202211594981 A CN 202211594981A CN 115603729 B CN115603729 B CN 115603729B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only
- H03K19/01806—Interface arrangements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention discloses an asynchronous TTL serial port to single BUS circuit, which comprises a single chip TTL serial port receiving end RX1, a single chip TTL serial port transmitting end TX1, a single BUS data end BUS, a single-path digital switch U2 and a multi-path digital switch U3, wherein the models of U2 and U3 are NC7SZD384 and CH442E respectively, the RX1 is connected to a pin 2 of U2, the BUS is connected with a pin 1 of U2 and a pin 4 of U3, the pin 3 of U2 is grounded, the pin 4 of U2 is connected with a pull-up resistor R2 and a collector of a triode Q1, the pin 5 of U2 is connected with VCC, the TX1 is connected with the pin 1 and the pin 2 of U3, one end of a resistor R4 is connected with VCC, the other end is connected with a diode D1, D2 and the resistor R3, the resistor R4 is a pull-up resistor of a TX1 signal, the pin 3 of U3 is connected to VCC through a resistor R6, the pin 5 and the pin 9 are grounded, the pin 10 is connected to VCC, the pins 7 pins and the free pins are not connected.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to an asynchronous TTL serial port to single bus circuit.
Background
When the singlechip communicates with some peripheral equipment, such as a series of steering engines, the TTL duplex serial port needs to be converted into a single bus mode, and full-duplex communication is changed into half-duplex communication, namely, data transmission in one direction can be realized at one moment. The existing technical scheme is mainly divided into two categories, one category is signal inverse logic conversion, and the other category is signal positive logic conversion.
As shown in fig. 1-2, a circuit diagram of signal inverse logic conversion and a circuit diagram of signal positive logic conversion in the prior art are respectively shown, where RXD is a signal receiving end of a TTL serial port of a single chip microcomputer, TXD is a signal transmitting end of the TTL serial port of the single chip microcomputer, and SingleBus is a single bus signal end.
The working principle of the signal inverse logic conversion circuit of fig. 1 is analyzed. The output end of a conventional TTL serial port TXD of the singlechip is in a high level when the output end is idle, at the moment, an NPN type triode Q3 in the figure 1 is conducted, and under the action of a pull-up resistor R8, a single bus output end SingleBus is pulled down; when the TXD goes low, the transistor Q3 is turned off and the single bus output port SingleBus goes high. The output of the positive logic at the TXD end of the singlechip is converted into an output signal of the inverse logic at the singleBus end. In the same control logic, when the SingleBus end is at a high level, the NPN type triode Q2 is conducted, and the RXD end is changed into a low level under the action of the pull-up resistor R9; when the SingleBus end is at a low level, the triode Q2 is cut off, and the RXD end becomes a high level. The output of the SingleBus end is converted by a circuit and then becomes an inverse logic signal of the RXD end. From the above analysis, when the TXD terminal signal is converted into the SingleBus terminal signal, the level change of the SingleBus terminal will cause the change of the RXD terminal signal at the same time, which is equivalent to the self-receiving and sending of the inverse logic signal for the single chip.
The working principle of the signal positive logic conversion circuit of fig. 2 is analyzed. When the TXD end of the TTL serial port output end of the singlechip is in a high level, the PNP type triode Q6 is cut off, the NPN type triode Q7 is cut off, and the SingleBus of the unibus output end is pulled up to a high level under the action of the resistors R16 and R22 and the diode D2; when the TXD end of the TTL output end of the singlechip is at a low level, the triode Q6 is conducted, the triode Q7 is conducted, the level of the single bus output end SingleBus is the voltage division value of the resistor R15 in the series voltage division circuits R16, R22, D2 and R15, and the SingleBus end is at a low level at the moment because the resistor R15 is small. When a signal at the SingleBus end is converted to the RXD end, when the SingleBus end is at a high level, the diode D2 is cut off, the triodes Q4 and Q5 are cut off, and the RXD end is at a high level under the action of the pull-up resistor R14; when the SingleBus end is at a low level, the diode D2 is conducted, the triodes Q4 and Q5 are conducted, and the RXD end becomes a low level under the action of the pull-up resistor R14. From the above analysis, the circuit shown in fig. 2 can realize positive logic signal conversion transmission, but the circuit also has a self-transceiving phenomenon.
In a word, the signal inverse logic conversion circuit needs to perform special processing on receiving or sending of signals, and the requirement on control software is high. And no matter the signal is a reverse logic conversion circuit or a positive logic circuit, the signal self-receiving and sending phenomena exist, the requirements for judging the control logic and the data frame of the single chip microcomputer are higher, and meanwhile, data interference is caused to the control software of the single chip microcomputer. Therefore, it is urgently needed to develop an asynchronous TTL serial to single bus circuit to solve the above technical problems.
In view of the above, the present invention is particularly proposed.
Disclosure of Invention
The invention aims to provide an asynchronous TTL serial port to single bus circuit, which is constructed by adopting a digital switch circuit, realizes positive logic transmission of signals, avoids the self-receiving and sending phenomena of signals at a singlechip end, has wide application prospect and is beneficial to popularization and application.
In order to achieve the purpose, the asynchronous TTL serial port to unibus circuit provided by the invention comprises a single chip TTL serial port receiving end RX1, a single chip TTL serial port sending end TX1, a unibus data end BUS, a unipath digital switch U2 and a multipath digital switch U3, wherein the types of U2 and U3 are NC7SZD384 and CH442E respectively, the RX1 is connected to pin 2 of U2, a signal is pulled up to VCC through a resistor R1, the BUS is connected with pin 1 of U2 and pin 4 of U3, the signal is pulled up to VCC through a resistor R23, pin 3 of U2 is grounded, pin 4 of U2 is connected with pull-up resistor R2 and collector of triode Q1, emitter of triode Q1 is grounded, grounding resistor R5 is connected in parallel between base and emitter of triode Q1, pin 5 of U2 is connected with pin TX1 and pin 2 of U3, the signal is connected with base and base of VCC 3 of triode Q1 through two inverse parallel diodes D1 and D2, the other end of VCC 3 is connected to a resistor R3, the other end of VCC 3, the pin of VCC 3 is connected to the resistor R3, the base of the resistor R6, the resistor R3 is connected to the idle resistor R3, the other end of the idle resistor R3, the idle resistor R6 is connected to the idle resistor R3, and the idle resistor R6 of the idle resistor R3, and the idle resistor R6 is connected to the resistor R3, and the other end of the idle resistor R3.
Preferably, when the 4 pin of U2 is low, the 1 pin and the 2 pin of U2 are on; when the pin 9 of the U3 is at a low level, the chip is enabled; when U3 is enabled, when pin 1 of U3 is at low level, pins 2 and 4 of U3 are connected, and pins 8 and 6 of U3 are connected; when pin 1 of U3 is high, pins 3 and 4 of U3 are connected, and pins 7 and 6 of U3 are connected.
Preferably, when the TX1 is at a high level, the pin 1 of the U3 is directly connected to the TX1, the pins 3 and 4 of the U3 are connected, and the BUS single BUS is at a high level; when TX1 is at a low level, a pin 2 and a pin 4 of U3 are connected, a BUS single BUS is at a low level, positive logic of conversion transmission from a TX1 signal to the BUS single BUS is met, meanwhile, when TX1 is at a high level, a diode D1 is connected, a diode D2 is cut off, a triode Q1 is connected under the common drive of resistors R4, R3 and R5, the pin 4 of U2 is at a low level under the action of a pull-up resistor R2, the pin 1 and the pin 2 of U2 are connected, at the moment, the BUS single BUS is at a high level, and RX1 is at a high level; when the TX1 is at a low level, the diode D1 is turned off, the diode D2 is turned on, the transistor Q1 is turned off, the pin 4 of the U2 is at a high level, the pins 1 and 2 of the U2 are turned off, and the RX1 maintains at a high level under the action of the pull-up resistor R1.
Preferably, when the peripheral device transmits data to the RX1 terminal through the BUS single BUS, the half-duplex communication is performed, the TX1 terminal maintains a high level, the triode Q1 is turned on, the pin 4 of the U2 is a low level, the pin 1 and the pin 2 of the U2 are turned on, a signal of the RX1 terminal changes along with the change of the BUS signal, the pin 3 and the pin 4 of the U3 are turned on, the resistors R6 and R23 become pull-up driving resistors, the pin 2 and the pin 4 of the U3 are turned off, and the BUS terminal signal does not affect the TX1 terminal.
Preferably, the triode Q1 is an NPN type triode.
The asynchronous TTL serial port to single bus circuit provided by the invention has the following beneficial effects.
1. The invention realizes the switching of signals based on the high-speed digital switch, the switching time is only about 5ns, and the conversion and transmission of high-speed signals can be realized.
2. The invention can realize automatic discrimination on the transmission direction of the signal and avoid the self-receiving and sending of the data at the TTL serial port end.
3. The invention utilizes the fast switching capability of the digital switch, ensures the invariance of signal level transmission and realizes the positive logic conversion transmission of signals.
Drawings
FIG. 1 is a circuit diagram of a prior art signal inversion logic;
FIG. 2 is a circuit diagram of a prior art positive logic transition of a signal;
fig. 3 is a circuit diagram of an asynchronous TTL serial to single bus circuit provided in the present invention.
Detailed Description
The present invention will be further described with reference to the following specific embodiments and accompanying drawings to assist in understanding the contents of the invention.
Fig. 3 is a circuit diagram of an asynchronous TTL serial-to-single bus circuit according to the present invention. The asynchronous TTL serial port to unibus circuit comprises a single-chip TTL serial port receiving end RX1, a single-chip TTL serial port transmitting end TX1, a single-BUS data end BUS, a single-path digital switch U2 and a multi-path digital switch U3, wherein the models of U2 and U3 are NC7SZD384 and CH442E respectively, the RX1 is connected to a pin 2 of the U2, a signal is pulled up to VCC through a resistor R1, the BUS is connected with a pin 1 of the U2 and a pin 4 of the U3, the signal is pulled up to VCC through a resistor R23, a pin 3 of the U2 is grounded, a pin 4 of the U2 is connected with a pull-up resistor R2 and a collector of a triode Q1, an emitter of the triode Q1 is grounded, and a ground resistor R5 is connected between a base electrode and an emitter of the triode Q1 in parallel, U2's 5 feet connect the VCC, TX1 is connected with U3's 1 foot, 2 feet, and the signal is connected with triode Q1's base resistance R3 through two anti-parallel 4148 diode D1, D2 again, resistance R3's the other end is connected to Q1's base, and in order to improve the driving force of triode base, resistance R4 one end is connected with the VCC, and the other end is connected with diode D1, D2, resistance R3, resistance R4 becomes the pull-up resistance of TX1 signal, VCC is received through resistance R6 to U3's 3 foot, U3's 5 feet, 9 feet ground connection, the VCC is received to U3's 10 feet, U3's 6 feet, 7 feet, 8 feet of U3 are idle not connect. Preferably, the triode Q1 is an NPN-type triode.
When the 4 feet of the U2 are at low level, the 1 foot and the 2 foot of the U2 are connected; when the pin 9 of the U3 is at a low level, the chip is enabled; when U3 is enabled, when pin 1 of U3 is at low level, pins 2 and 4 of U3 are connected, and pins 8 and 6 of U3 are connected; when pin 1 of U3 is high, pins 3 and 4 of U3 are connected, and pins 7 and 6 of U3 are connected.
When TX1 is at a high level, because a pin 1 of U3 is directly connected with TX1, pins 3 and 4 of U3 are connected, and a BUS single BUS is at a high level; when TX1 is at low level, pins 2 and 4 of U3 are connected, the BUS single BUS is at low level, and positive logic of TX1 signal to BUS single BUS conversion transmission is met. Meanwhile, when the TX1 is in a high level, the diode D1 is conducted, the D2 is cut off, the triode Q1 is conducted under the common drive of the resistors R4, R3 and R5, the pin 4 of the U2 is in a low level under the action of the pull-up resistor R2, the pin 1 and the pin 2 of the U2 are conducted, and the BUS single BUS is in a high level at the moment, so that the RX1 is in a high level; when the TX1 is at a low level, the diode D1 is turned off, the diode D2 is turned on, the transistor Q1 is turned off, the pin 4 of the U2 is at a high level, the pins 1 and 2 of the U2 are turned off, and the RX1 maintains at a high level under the action of the pull-up resistor R1. According to the analysis, the circuit can realize positive logic transmission of signals, and avoids self-receiving and sending of serial port signals at a single chip microcomputer.
When the peripheral equipment transmits data to the RX1 end through the BUS single BUS, because of half-duplex communication, the TX1 end keeps high level at the moment, the triode Q1 is conducted, the pin 4 of the U2 is low level, the pin 1 and the pin 2 of the U2 are connected, and signals of the RX1 end change along with the change of the BUS signals. At this time, pins 3 and 4 of U3 are turned on, resistors R6 and R23 become pull-up driving resistors, and since pins 2 and 4 of U3 are turned off, the BUS terminal signal does not affect the TX1 terminal.
The invention is based on the digital switch, and a logic control circuit is built, so that the self-receiving and sending of serial port data are prevented; the invention ensures the reliable conversion transmission of high-speed signals based on the high-speed switching capability of the digital switch; the invention realizes the positive logic conversion transmission of signals by matching a logic control circuit built by a digital switch based on the high and low level detection of transmission signals.
The inventive concept is explained in detail herein using specific examples, which are given only to aid in understanding the core concepts of the invention. It should be understood that any obvious modifications, equivalents and other improvements made by those skilled in the art without departing from the spirit of the present invention are included in the scope of the present invention.
Claims (5)
1. The circuit is characterized by comprising a single chip transistor-transistor (TTL) serial port receiving end RX1, a single chip transistor-transistor (TTL) serial port transmitting end TX1, a single BUS data end BUS, a single digital switch U2 and a multi-path digital switch U3, wherein the types of U2 and U3 are NC7SZD384 and CH442E respectively, the RX1 is connected to a pin 2 of the U2, a signal is pulled up to VCC through a resistor R1, the BUS is connected with a pin 1 of the U2 and a pin 4 of the U3, the signal is pulled up to VCC through a resistor R23, a pin 3 of the U2 is grounded, a pin 4 of the U2 is connected with a pull-up resistor R2 and a collector of a triode Q1, an emitter of the triode Q1 is grounded, a ground resistor R5 is connected in parallel between a base of the triode Q1 and the emitter, a pin 5 of the U2 is connected with VCC, the pin 1 of the TX1 is connected with pins and pin 2 of the U3, the signal is connected with a base R3 of two inverse parallel diodes D1 and D2 of the triode Q1, the other base of the VCC is connected with a base of the U3, the resistor R3, the other end of the U3 is connected with a pin TX 3, the idle resistor R6, and the idle resistor R6, the pin of the U3 is connected with the idle resistor R3, and the other end of the idle resistor R6, the idle resistor R3, the idle resistor R6 is connected with the idle resistor R3, the idle pin of the U3, and the other end of the idle resistor R6, and the idle resistor R3.
2. The asynchronous TTL serial-to-single bus circuit as claimed in claim 1 wherein when pin 4 of U2 is low, pin 1 and pin 2 of U2 are connected; when the pin 9 of the U3 is at a low level, the chip is enabled; when U3 is enabled, when pin 1 of U3 is at low level, pins 2 and 4 of U3 are connected, and pins 8 and 6 of U3 are connected; when pin 1 of U3 is high, pins 3 and 4 of U3 are connected, and pins 7 and 6 of U3 are connected.
3. The circuit for converting an asynchronous TTL serial port into a single BUS according to claim 1, characterized in that when TX1 is at high level, pin 1 of U3 is directly connected with TX1, pin 3 and pin 4 of U3 are connected, and BUS single BUS is at high level; when TX1 is at a low level, pin 2 and pin 4 of U3 are connected, a BUS single BUS is at a low level, positive logic of conversion transmission from a TX1 signal to the BUS single BUS is met, meanwhile, when TX1 is at a high level, a diode D1 is connected, D2 is cut off, under the common driving of resistors R4, R3 and R5, a triode Q1 is connected, under the action of a pull-up resistor R2, pin 4 of U2 is at a low level, pin 1 and pin 2 of U2 are connected, at the moment, the BUS single BUS is at a high level, and RX1 is at a high level; when the TX1 is at a low level, the diode D1 is turned off, the D2 is turned on, the transistor Q1 is turned off, the pin 4 of the U2 is at a high level, the pins 1 and 2 of the U2 are turned off, and the RX1 maintains at a high level under the action of the pull-up resistor R1.
4. The asynchronous TTL serial port to single BUS circuit of claim 1 wherein when the peripheral device transmits data to RX1 via BUS single BUS, half duplex communication is provided, TX1 is kept at high level, transistor Q1 is on, pin 4 of U2 is at low level, pin 1 and pin 2 of U2 are on, the signal of RX1 changes with the change of BUS signal, pin 3 and pin 4 of U3 are on, resistors R6 and R23 become pull-up driving resistors, pin 2 and pin 4 of U3 are off, and the BUS signal does not affect TX 1.
5. The circuit according to claim 1, wherein the transistor Q1 is an NPN type triode.
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| CN202211594981.8A CN115603729B (en) | 2022-12-13 | 2022-12-13 | Asynchronous TTL serial port to single bus circuit |
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| CN202211594981.8A CN115603729B (en) | 2022-12-13 | 2022-12-13 | Asynchronous TTL serial port to single bus circuit |
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| CN115603729A CN115603729A (en) | 2023-01-13 |
| CN115603729B true CN115603729B (en) | 2023-04-07 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| FR2725085B1 (en) * | 1994-09-26 | 1997-01-17 | Matra Mhs | DEVICE FOR INTERFACING LOGIC SIGNALS FROM THE BTL LEVEL TO THE TTL AND CMOS LEVEL |
| CN104124960B (en) * | 2014-06-20 | 2018-02-23 | 华中科技大学 | A kind of non-volatile boolean calculation circuit and its operating method |
| CN104317762A (en) * | 2014-10-28 | 2015-01-28 | 北京四方继保自动化股份有限公司 | Method for adaptively controlling transmitting and receiving directions of RS485 chip by aid of FPGA (field programmable gate array) |
| CN204836132U (en) * | 2015-08-28 | 2015-12-02 | 杭州华三通信技术有限公司 | Serial interface on communication equipment's veneer switches control circuit |
| JP2020136694A (en) * | 2019-02-12 | 2020-08-31 | 株式会社豊田中央研究所 | Output circuit |
| CN217821585U (en) * | 2022-08-15 | 2022-11-15 | 成都恒盛数源电子科技有限公司 | MAX485 receiving and dispatching control signal generating device based on serial port sending signal |
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