CN115602776A - LED chip, LED device, killing equipment and LED chip preparation method - Google Patents
LED chip, LED device, killing equipment and LED chip preparation method Download PDFInfo
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- CN115602776A CN115602776A CN202211152295.5A CN202211152295A CN115602776A CN 115602776 A CN115602776 A CN 115602776A CN 202211152295 A CN202211152295 A CN 202211152295A CN 115602776 A CN115602776 A CN 115602776A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
- H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
-
- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61L—METHODS OR APPARATUS FOR STERILISING MATERIALS OR OBJECTS IN GENERAL; DISINFECTION, STERILISATION OR DEODORISATION OF AIR; CHEMICAL ASPECTS OF BANDAGES, DRESSINGS, ABSORBENT PADS OR SURGICAL ARTICLES; MATERIALS FOR BANDAGES, DRESSINGS, ABSORBENT PADS OR SURGICAL ARTICLES
- A61L2/00—Methods or apparatus for disinfecting or sterilising materials or objects other than foodstuffs or contact lenses; Accessories therefor
- A61L2/02—Methods or apparatus for disinfecting or sterilising materials or objects other than foodstuffs or contact lenses; Accessories therefor using physical phenomena
- A61L2/08—Radiation
- A61L2/10—Ultra-violet radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0025—Processes relating to coatings
Abstract
The embodiment of the application discloses an LED chip, an LED device, a killing device and an LED chip preparation method, wherein the LED chip comprises a first semiconductor layer, a plurality of bosses, a reflective film, a first electrode and a second electrode, and the first semiconductor layer is provided with a first upper surface; each boss is convexly arranged on the first upper surface and comprises a light emitting layer and a second semiconductor layer, each boss is provided with a second upper surface and six side surfaces arranged on the periphery of the second upper surface, and each side surface is connected with the first upper surface and the second upper surface; the reflective film is arranged on each side surface; the first electrode is arranged on the first upper surface and is positioned in the groove; the second electrode is arranged on the second upper surface of the boss. For the LED chip, a plurality of projections which are distributed in a point shape and have six side surfaces are formed on the first upper surface of the first semiconductor layer, a reflective film is attached to each side surface, the reflective film on the side surface can reflect side surface light back to the light-emitting surface, light loss of the side surface light-emitting is reduced, and light-emitting efficiency of the LED chip is improved.
Description
Technical Field
The invention relates to the technical field of photoelectron manufacturing, in particular to an LED chip and a preparation method thereof.
Background
As one of important illumination means in production and life, LEDs (light-emitting diodes) have been used in a plurality of fields such as illumination display, sterilization, disinfection, inspection, and detection. At present, for the field of LEDs, especially the field of deep ultraviolet LEDs, the electro-optic conversion efficiency is one of the key performance indexes for measuring the quality of LEDs, and the light extraction efficiency is one of the key factors influencing the electro-optic conversion efficiency.
In the related art, the LED chip includes an active region, light generated by the active region is emitted in all directions at 360 degrees, and the LED chip generally has only one effective light emitting surface, which causes a large portion of light to be dissipated inside the LED chip, thereby reducing light emitting efficiency.
Disclosure of Invention
The invention mainly aims to provide an LED chip, an LED device, a killing device and an LED chip preparation method for improving light extraction efficiency.
To achieve the above object, an embodiment of the present invention provides an LED chip structure, including:
a substrate;
a buffer layer disposed on the upper surface of the substrate
The first semiconductor layer is arranged on the upper surface of the buffer layer and provided with a first upper surface;
each boss comprises a light emitting layer and a second semiconductor layer which are sequentially laminated on the first upper surface, each boss is provided with a second upper surface and six side surfaces arranged on the periphery of the second upper surface, each side surface is connected with the first upper surface and the second upper surface, the side surfaces and the first upper surface are arranged in an obtuse angle, and a groove is formed between the adjacent side surfaces of two adjacent bosses;
the reflecting film is arranged on each side surface;
the first electrode is arranged on the first upper surface of the first semiconductor layer;
and the second electrode is arranged on the second upper surface of the boss.
In some embodiments, an included angle between the side surface and the first upper surface is greater than or equal to 110 degrees and less than or equal to 150 degrees.
In some embodiments, in the first direction, the bosses have a plurality of rows; and in a second direction forming an included angle with the first direction, the bosses in the two adjacent rows are staggered.
In some embodiments, the first semiconductor layer is an n-type semiconductor layer, the light emitting layer is a multiple quantum well layer, and the second semiconductor layer is a p-type semiconductor layer.
In some embodiments, the reflective film includes an insulating layer, a light-transmitting layer, a reflective layer and a protective layer sequentially stacked on the side surface, and the second electrode is the reflective layer.
In some embodiments, the barrier layer is a SiO2 layer and the light transmitting layer is MgF 2 The second electrode is made of a material to which Rh is added, and the protective layer is an SiO2 layer.
An LED device comprises an LED chip and a substrate, wherein the LED chip is packaged on the substrate.
A killing apparatus comprising an LED device, the LED device being a deep ultraviolet LED device. A method for preparing an LED chip comprises the following steps,
growing a buffer layer, an n-type semiconductor layer, a multi-quantum well layer and a p-type semiconductor layer on a substrate in sequence;
a latticed groove extending to the first upper surface of the n-type semiconductor layer or extending into the n-type semiconductor layer is formed in the second upper surface of the p-type semiconductor layer, the groove is provided with a groove side surface, and the groove side surface and the first upper surface are arranged at an obtuse angle;
forming a reflective film on the groove side surface of the groove;
an n-type electrode is formed on the first upper surface and a p-type electrode is formed on the second upper surface.
In some embodiments, the included angle between the groove side surface and the first upper surface is greater than or equal to 110 degrees and less than or equal to 150 degrees.
In the technical scheme of the embodiment of the invention, the first upper surface of the first semiconductor layer is provided with the plurality of bulges which are distributed in an array manner and are provided with six side surfaces, the side surfaces are attached with the reflective films, and the reflective films on the side surfaces can reflect side surface light to the vertical light-emitting surface, so that the light loss of the side surface light emission is reduced, and the light-emitting efficiency of the LED chip is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
Fig. 1 is a schematic perspective view of a p-type electrode region of an LED chip provided in this embodiment;
fig. 2 is a schematic sectional view of a single microstructure of a p-type electrode region of an LED chip provided in this embodiment;
FIG. 3 is an enlarged, fragmentary view of FIG. 2 at point A;
fig. 4 to 14 are schematic structural diagrams of a junction between an n-type electrode region and a p-type electrode region of an LED chip in a manufacturing process of the microstructure provided in this embodiment;
fig. 15 is a schematic flow chart of a method for manufacturing an LED chip according to this embodiment.
Detailed Description
To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the application, as detailed in the appended claims.
As shown in fig. 1 to 3, the present embodiment provides an LED chip 1, which includes an active region 10, a reflective film 20, a first electrode 17, and a second electrode 40. The active region 10 includes a first semiconductor layer 11, a light emitting layer 12, and a second semiconductor layer 13 stacked in sequence from bottom to top, the second semiconductor layer 13 is provided with a groove 14 extending to the first semiconductor layer 11, and the groove 14 is in a grid shape communicated with each other. The grid-like grooves 14 form a plurality of bosses 15 distributed in dots on the first upper surface 111 of the first semiconductor layer 11, and the grooves 14 are provided between the bosses 15. Each of the bosses 15 has a substantially hexagonal prism shape, and a cross section of each of the bosses 15 may be hexagonal, which may be parallel to the first upper surface 111 of the first semiconductor layer 11. Each of the bosses 15 has a second upper surface 151 and six side surfaces 152 provided on the peripheral side of the second upper surface 151, the second upper surface 151 being a surface of the boss 15 on the side away from the light-emitting layer 12, the side surfaces 152 connecting the second upper surface 151 of the boss 15 and the first upper surface 111 of the first semiconductor layer 11. Each side surface 152 may be regarded as a groove side surface of the groove 14, the first upper surface 111 may be regarded as a groove bottom surface of the groove 14, and the groove 14 is defined by the first upper surface 111 and each side surface 152 of each boss 15. Each side surface 152 is disposed obliquely, and each side surface 152 is disposed at an obtuse angle with respect to the first upper surface 111. The retroreflective sheeting 20 is disposed on each of the side surfaces 152. The first electrode 17 is disposed on the first upper surface 111 of the first semiconductor layer 11 and located in the groove 14. The second electrode 40 is provided on the second upper surface 151 of the boss 15, and the second electrode 40 can reflect light. Each of the lands 15 includes a light-emitting layer 12 and a second semiconductor layer 13 laminated in this order on the first upper surface 111. The side surface 152 of the mesa 15 includes the side surface of the light-emitting layer 12 and the side surface of the second semiconductor layer 13, and the second upper surface 151 of the mesa 15 is the upper surface of the second semiconductor layer 13 on the side away from the light-emitting layer 12. The second upper surface 151 is a backlight surface of the LED chip 1. The second upper surfaces 151 of the respective bosses 15 may be coplanar.
The LED chip 1 may include a substrate 50, the substrate 50 has an upper surface and a lower surface, the upper surface faces the active region 10, the active region 10 is disposed on the upper surface, the first semiconductor layer 11, the light emitting layer 12 and the second semiconductor layer 13 are sequentially stacked on the upper surface, the lower surface faces away from the active region 10, and the lower surface may be a light emitting surface of the LED chip 1. The substrate 50 may be a sapphire substrate, a silicon carbide substrate, or the like. The substrate 50 may be a flat sheet substrate or a patterned substrate. In this embodiment, for the LED chip 1, one side of the backlight surface can be regarded as the upper side, and one side of the light emitting surface can be regarded as the lower side.
The first semiconductor layer 11 may be an n-type semiconductor layer, and the second semiconductor layer 13 may correspond to a p-type semiconductor layer. The n-type semiconductor layer and the p-type semiconductor layer provide electrons and holes, respectively, for radiative recombination. The electrons and holes radiatively recombine in the light-emitting layer 12 and emit photons. The reflective film 20 can reflect the light emitted from the light-emitting layer 12 to the light-emitting surface of the LED chip 1.
The light S emitted from the light-emitting layer 12 includes a backlight directed to the backlight surface of the LED chip 1, a front light directed to the light-emitting surface of the LED chip, and a side light directed to the side surface 152 of the boss 15. Forming a plurality of protrusions 15 with a hexagonal cross section and a dotted distribution on the first upper surface 111 of the first semiconductor layer 11, wherein the reflective film 20 is attached to six side surfaces 152 of the protrusions 15, and the reflective film 20 of the side surfaces 152 can reflect side light back to the light-emitting surface; the back light can be reflected back to the light-emitting surface by the second electrode 40; therefore, while the backlight can be effectively recycled, the light loss of the light emitted from the side surface 152 is greatly reduced, the recycled backlight is converted into the front light capable of being reflected to the light emitting surface, and the light emitting efficiency of the LED chip 1 is improved. Meanwhile, since each boss 15 employs six side surfaces 152, the intensity of light can be effectively ensured while ensuring sufficient reception of side light.
The p-type semiconductor layer (second semiconductor layer 13) may Be formed by doping GaN (gallium nitride), alGaN (aluminum gallium nitride) with impurities such as Mg (magnesium), zn (zinc), or Be (beryllium). In a specific structure, the p-type semiconductor layer includes a p-type AlGaN layer and a p-type GaN layer formed on the p-type AlGaN layer, that is, the active region 10 may include an n-type semiconductor layer, a light emitting layer 12, a p-type AlGaN layer, and a p-type GaN layer, which are sequentially stacked from bottom to top. In a more specific structure, an electron blocking layer is interposed between the p-type AlGaN layer and the light emitting layer 12 to prevent holes from returning to the p-type semiconductor layer and improve internal quantum efficiency, i.e., the active region 10 may include an n-type semiconductor layer, a light emitting layer, an electron blocking layer, a p-type AlGaN layer, and a p-type GaN layer, which are sequentially stacked from bottom to top.
The n-type semiconductor layer (first semiconductor layer 11) may be formed by AlGaN, doping with impurities such as Si (silicon), ge (germanium), sn (tin), se (selenium), te (tellurium), and the like.
The light emitting layer 12 may be a multiple quantum well layer. The multiple quantum well layer (light emitting layer 12) may be a multiple quantum well layer or a GaN/AlGaN layer, alGaN (low Al composition)/AlGaN (high Al composition) which can emit ultraviolet light.
The first electrode 17 is an n-type electrode and the second electrode 40 is a p-type electrode. The n-type electrode and the p-type electrode may be made of one or more of Ti (titanium), ni (nickel), al (aluminum), au (gold). In one specific configuration, the p-type electrode is a Ni-Au alloy. The N-type electrode may also be a Ti-Al-Ni-Au alloy.
The boss 15 has a second upper surface 151 and six side surfaces 152. Six side surfaces 152 are connected end to end in a direction around the axis of the boss 15 to form an annular peripheral wall surface. A grid-like recess 14 is formed between each boss 15. The groove 14 may extend from the second semiconductor layer 13 to the first semiconductor layer 11 to expose the first semiconductor layer 11. Each of the lands 15 may include a light emitting layer 12 and a second semiconductor layer 13, which may include two structures, sequentially stacked. The first structure is that the mesa 15 is composed of only the light-emitting layer 12 and the second semiconductor layer 13; or, during the preparation, a part of the first semiconductor layer 11 is etched, and the first upper surface 111 is the surface exposed after etching, so that the remaining part of the first semiconductor layer 11 becomes a component of the boss 15, that is, the boss 15 may include the first semiconductor layer 11, the light reflecting layer 12 and the second semiconductor layer 13 at the same time.
Referring to fig. 6, the side surface 152 of the bump 15 is disposed at an obtuse angle with respect to the first upper surface 111 of the first semiconductor layer 11. In a specific structure, the angle P between the side surface 152 of the boss 15 and the first upper surface 111 is 110 degrees or more and 150 degrees or less, and within this angle range, a good light reflection effect can be ensured. Correspondingly, the inclination angle of the boss 15 relative to the first upper surface 111 is greater than or equal to 30 degrees and less than or equal to 70 degrees.
As shown in fig. 1, further, in the first direction V, the bosses 15 have a plurality of rows, each row including a plurality of bosses 15. In the second direction H forming an included angle with the first direction V, two rows of adjacent bosses 15 are staggered, so that the distribution density of the bosses 15 can be increased, that is, for the same surface area, more bosses 15 can be formed on the first upper surface 111 of the first semiconductor layer 11, and the distribution density of the grooves 14 is further increased. Among all the bosses 15, one or more bosses 15 may be surrounded by six bosses 15, the surrounded boss 15 may be defined as a central boss, and the six bosses 15 may be defined as peripheral bosses, so that six side surfaces 152 of the central boss are respectively opposite to the side surfaces 152 of the six peripheral bosses, thereby forming the groove 14 capable of surrounding the central boss.
Further, a reflective film 20 is disposed in the groove 14, the reflective film 20 includes an isolation layer 21, a transparent layer 22, a reflective layer 23 and a protection layer 24, and the isolation layer 21, the transparent layer 22, the reflective layer 23 and the protection layer 24 are sequentially stacked and formed on the groove side (the side surface 152) of the groove 14. The isolation layer 21 is made of a high-resistance and light-transmitting material, the isolation layer 21 can isolate the p-type semiconductor layer (the second semiconductor layer 13) and the n-type semiconductor layer (the first semiconductor layer 11) from other layers of the reflective film 20, so as to prevent short circuit caused by electrical bridging between the p-type semiconductor layer and the n-type semiconductor layer in an accidental situation, for example, the isolation layer 21 may be a SiO2 (silicon dioxide) layer. The light transmitting layer 22 is capable of selectively transmitting light of wavelength λ, the light transmitting layer 22 typically having a high transmittance and a low refractive index, for example, the light transmitting layer 22 may be MgF having a thickness of λ/4 2 (magnesium fluoride) layer. The reflective layer 22 can effectively reflect the incident ultraviolet light to the light emitting surface of the LED chip 1, and generally has a high reflectivity to the ultraviolet light. The material of the light reflecting layer 23 is a metal layer such as Al metal, rh (rhodium) metal, or Al — Rh alloy. Specifically, the light-reflecting layer 23 may be formed by adding Rh element to the second electrode 40, that is, the second electrode 40 is the light-reflecting layer 23. The protective layer 24 is a SiO2 layer, which can isolate the metal reflective layer 23 from the outside and prevent oxidation of the metal layer. In one particular arrangement, the retroreflective sheeting 20 may also cover the edge portions of the second upper surfaces 151 of the lands 15. For SiO2 layerThe etching is easier, and BOE solution can be used for wet etching, and other layers are not damaged by the wet etching.
As shown in fig. 1 to 3 and 15, an embodiment of the present invention further provides a method for manufacturing an LED chip, such as a deep ultraviolet LED chip. The preparation method comprises the following steps: s100, sequentially growing a buffer layer 80, an n-type semiconductor layer (first semiconductor layer 11), a multi-quantum well layer (light-emitting layer 12), and a p-type semiconductor layer (second semiconductor layer 13) on a substrate 50; s200, forming a grid-shaped groove 14 extending to the first upper surface 111 of the n-type semiconductor layer from the second upper surface 151 of the p-type semiconductor layer, wherein the groove 14 is provided with a groove side surface (side surface 152) which is arranged at an obtuse angle with the first upper surface 111; s300, forming a reflective film 20 on the groove side surface of the groove 14; in S400, an n-type electrode (first electrode 17) is formed on the first upper surface 111 of the n-type semiconductor layer, and a p-type electrode (second electrode 40) is formed on the second upper surface 151 of the p-type semiconductor layer.
Specifically, the preparation method of the LED chip comprises the following steps:
s1: preparing an epitaxial wafer;
a buffer layer, an n-type semiconductor layer, a multi-quantum well layer, and a p-type semiconductor layer are sequentially grown on the substrate 50 by using a Metal Organic Chemical Vapor Deposition (MOCVD). As shown in fig. 2 and 4, the epitaxial wafer 60 may include a substrate 50 and a buffer layer 80, an n-type semiconductor layer (first semiconductor layer 11), a multi-quantum well layer (light emitting layer 12), and a p-type semiconductor layer (second semiconductor layer 13) grown on the substrate 50.
S2: etching to expose the n-type semiconductor layer (the first semiconductor layer 11) through photoetching and etching processes;
specifically, the epitaxial wafer is spin-coated with a positive photoresist, then exposed, developed to remove the positive photoresist in the n-type semiconductor layer portion, and then placed in an ICP apparatus for etching, and etched down to the first upper surface 111 of the n-type semiconductor layer to expose the n-type semiconductor layer, as shown in fig. 5.
In this step, which corresponds to forming the groove 14 on the epitaxial wafer, the bottom surface of the groove 14 is the first upper surface of the n-type semiconductor layer.
S3: etching a p-type semiconductor layer backlight surface structure by photoetching and etching processes;
specifically, an epitaxial wafer is coated with positive photoresist in a spinning mode and then placed into a photoetching machine for exposure, and the region of a p-type semiconductor layer of a mask for exposure is in a hexagonal grid shape; after exposure, the epitaxial wafer is placed into a developing machine for development, photoresist at the grid position is removed, the photoresist at the n-type semiconductor layer region (n-type electrode region) is reserved, and then etching is carried out through a plasma etching machine until the etching depth reaches the n-type semiconductor layer; the inclination angle of the etching step 15 is 30-70 degrees, wherein the contact area of the p-type semiconductor layer and the n-type semiconductor layer can be over-etched, as shown in fig. 6.
S4: plating an isolation layer 21 on the p-type semiconductor layer region (p-type electrode region) by a photoetching process and a PECVD process;
specifically, an epitaxial wafer is spin-coated with a positive photoresist and then placed in a photoetching machine for exposure, the epitaxial wafer is placed in a developing machine for development after exposure, the photoresist of the p-type semiconductor layer region is removed, the photoresist of the n-type semiconductor layer region is reserved, and then a layer of SiO2 serving as the isolation layer 21 is deposited on the p-type semiconductor layer region by adopting a Plasma Enhanced Chemical Vapor Deposition (PECVD) method.
The thickness of the insulating layer 21 is determined according to design and manufacturing requirements. Illustratively, the thickness of the insulating layer 21 is 4nm or more and 10nm or less.
As shown in fig. 7, an isolation layer 21 is deposited on the second upper surface 151 of the mesa 15, and the edge of the isolation layer 21 may extend to the first upper surface 111 of the n-type semiconductor layer.
After the isolation layer 21 is deposited, sulfuric acid, hydrogen peroxide and water are used for cleaning residual glue on the first upper surface 111 of the epitaxial wafer after being matched in proportion, and the SiO2 layer of the p-type semiconductor layer region is reserved after the residual glue is cleaned in a spin-drying mode.
S5: making an n-type electrode on the n-type semiconductor layer by photoetching and metal evaporation processes;
specifically, a positive photoresist is spin-coated on the epitaxial wafer, and then the epitaxial wafer is placed in a photo-etching machine for exposure, a mask is used for exposure, the epitaxial wafer is placed in a developing machine for development after exposure, the photoresist on the n-type semiconductor layer region is removed, and then an n-type electrode (first electrode 17) is formed on the first upper surface 111 by a metal evaporation method, as shown in fig. 8.
After the first electrode 17 is formed, residual glue on the upper surface of the isolation layer 21 of the epitaxial wafer boss 15 is cleaned by using sulfuric acid, hydrogen peroxide and water in proportion, and the residual glue is cleaned by using pure water and dried.
S6: covering an isolation layer 21 on the n-type electrode by photoetching and PECVD (plasma enhanced chemical vapor deposition) processes;
specifically, an epitaxial wafer is spin-coated with a positive photoresist and then placed in a photo-lithography machine for exposure, a mask is used for exposure, the epitaxial wafer is placed in a developing machine for development after exposure, the photoresist on the n-type semiconductor layer region is removed, and then a SiO2 layer serving as an isolation layer 21 is coated on the first electrode 17 by a PECVD method, as shown in fig. 9.
After the first electrode 17 is covered with the isolation layer 21, sulfuric acid, hydrogen peroxide and water are used for cleaning residual glue on the upper surface of the isolation layer 21 of the epitaxial wafer boss 15 after being matched in proportion, and the residual glue is cleaned by pure water and dried.
S7: the p-type semiconductor layer region is coated with a light transmitting layer 22 by photolithography and PECVD processes
Specifically, a positive photoresist is spin-coated on an epitaxial wafer, the epitaxial wafer is then placed in a photoetching machine for exposure, a mask is used for exposure, the epitaxial wafer is placed in a developing machine for development after exposure, the photoresist on the p-type semiconductor layer region is removed, and then a MgF4 layer serving as a light transmitting layer 22 is covered on the upper surface of the isolation layer 21 of the p-type semiconductor layer by a PECVD method, as shown in fig. 10.
After the light-transmitting layer 22 is covered on the isolation layer 21 of the p-type semiconductor layer, sulfuric acid, hydrogen peroxide and water are used for cleaning residual glue on the upper surface of the isolation layer 21 of the n-type semiconductor layer of the epitaxial wafer after being mixed in proportion, and the residual glue is cleaned by pure water and dried.
S8: windowing the p-type semiconductor layer region through photoetching and etching processes, wherein the window is externally arranged at the position of the hexagonal protrusion;
specifically, an epitaxial wafer is coated with positive photoresist in a spinning mode and then placed into a photoetching machine for exposure, and the p-type semiconductor layer area of a mask plate for exposure is in a hexagonal grid shape; after exposure, the epitaxial wafer is placed into a developing machine for development, the photoresist at the grid is removed, the photoresist at the n-type semiconductor layer region is reserved, and then the etching is carried out through a plasma etching machine until the etching depth reaches the upper surface of the p-type semiconductor layer, namely, the window 16 is formed in the p-type semiconductor layer region, the bottom of the window is the upper surface of the p-type semiconductor layer, namely, the second upper surface 151 of the boss 15, as shown in fig. 11.
S9: evaporating a second electrode 40 on the p-type semiconductor layer region through photoetching and metal evaporation processes, wherein Rh metal materials are added into the second electrode 40;
specifically, spin-coating a positive photoresist on an epitaxial wafer, and then placing the epitaxial wafer into a photoetching machine for exposure, wherein a mask plate is adopted for exposure; and after exposure, the epitaxial wafer is placed into a developing machine for development, the photoresist at the grid position is removed, the photoresist at the n-type semiconductor layer region is remained, then a second electrode 40 is evaporated at the p-type semiconductor layer region through a metal evaporation process, and an Rh metal material is added into the second electrode 40, as shown in fig. 12.
And after the second electrode 40 is evaporated, sulfuric acid, hydrogen peroxide and water are used for cleaning residual glue on the upper surface of the isolation layer 21 of the epitaxial wafer n-type semiconductor layer after being mixed in proportion. The second electrode 40 is added with the Rh metal material, and thus functions as the light reflecting layer 23, that is, a portion of the second electrode 40 covering the light transmitting layer 22 functions as the light reflecting layer 23.
S10: evaporating a SiO2 layer on the epitaxial wafer by a PECVD process;
on the epitaxial wafer, a SiO2 layer as a protective layer 24 is vapor-deposited on the second electrode 40 of the p-type semiconductor layer region and on the isolation layer 21 of the n-type semiconductor layer region by a PECVD process, as shown in fig. 13.
S11: holes are formed at the first electrode and the second electrode through photoetching and etching processes, and then double thickening and a large gold block can be manufactured;
as shown in fig. 14, the first electrode 17 and the second electrode 40 can be exposed by making a hole 18 in a position corresponding to the first electrode 17 and the second electrode 40 (i.e., the light-transmissive layer 23).
The LED chip provided by the embodiment of the invention can be applied to an LED device. The LED device comprises a substrate and an LED chip packaged on the substrate. Such as a silicon substrate, a ceramic substrate, or a PCB board. The LED chip can be combined with the substrate in a mode of patch reflow or thermosonic eutectic soldering. The LED device can be applied to disinfection equipment which can be used for disinfection and sterilization and can adopt a deep ultraviolet LED device as a light source.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all equivalent structural changes made by using the contents of the specification and drawings, or any other related technical fields, which are directly or indirectly applied to the present invention, are included in the scope of the present invention.
Claims (10)
1. An LED chip, comprising,
a substrate;
a buffer layer disposed on the upper surface of the substrate
The first semiconductor layer is arranged on the upper surface of the buffer layer and provided with a first upper surface;
the bosses are arranged on the first upper surface in a protruding mode and comprise a light emitting layer and a second semiconductor layer which are sequentially laminated on the first upper surface, each boss is provided with a second upper surface and six side surfaces arranged on the periphery of the second upper surface, each side surface is connected with the first upper surface and the second upper surface, an obtuse angle is formed between each side surface and the first upper surface, and a groove is formed between the adjacent side surfaces of two adjacent bosses;
a reflective film provided on each of the side surfaces;
the first electrode is arranged on the first upper surface of the first semiconductor layer;
and the second electrode is arranged on the second upper surface of the boss.
2. The LED chip of claim 1, wherein an angle between said side surface and said first upper surface is greater than or equal to 110 degrees and less than or equal to 150 degrees.
3. The LED chip of claim 1, wherein said bosses have a plurality of rows in a first direction; and in a second direction forming an included angle with the first direction, the bosses in two adjacent rows are staggered.
4. The LED chip of claim 1, wherein said first semiconductor layer is an n-type semiconductor layer, said light emitting layer is a multi-quantum well layer, and said second semiconductor layer is a p-type semiconductor layer.
5. The LED chip of claim 1, wherein the reflective film comprises an insulating layer, a light-transmitting layer, a reflective layer, and a protective layer laminated in this order on the side surface, and the second electrode is the reflective layer.
6. The LED chip according to claim 5, wherein the insulating layer is a SiO2 layer, and the light-transmitting layer is MgF 2 A layer to which a material of the second electrode is added with an Rh element, the protective layer being an SiO2 layer.
7. An LED device, comprising,
the LED chip of any one of claims 1-6; and a (C) and (D) and,
the LED chip is packaged on the substrate.
8. A killing apparatus comprising the LED device of claim 7, wherein the LED device is a deep ultraviolet LED device.
9. A method for preparing an LED chip is characterized by comprising the following steps,
growing a buffer layer, an n-type semiconductor layer, a multi-quantum well layer and a p-type semiconductor layer on a substrate in sequence;
a latticed groove extending to the first upper surface of the n-type semiconductor layer or extending to the inside of the n-type semiconductor layer is formed in the second upper surface of the p-type semiconductor layer, the groove is provided with a groove side face, and the groove side face and the first upper surface are arranged at an obtuse angle;
forming a reflective film on the groove side surface of the groove;
and forming an n-type electrode on the first upper surface, and forming a p-type electrode on the second upper surface.
10. The method of claim 9, wherein an angle between the groove side surface and the first upper surface is greater than or equal to 110 degrees and less than or equal to 150 degrees.
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