CN115602688A - Heterogeneous substrate structure and manufacturing method thereof - Google Patents
Heterogeneous substrate structure and manufacturing method thereof Download PDFInfo
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- CN115602688A CN115602688A CN202110776992.7A CN202110776992A CN115602688A CN 115602688 A CN115602688 A CN 115602688A CN 202110776992 A CN202110776992 A CN 202110776992A CN 115602688 A CN115602688 A CN 115602688A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
- H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
Abstract
The invention discloses a heterogeneous substrate structure and a manufacturing method thereof. The heterogeneous substrate structure comprises a glass substrate, an electrode layer, a first sub-circuit board and a first rewiring layer. The electrode layer is located on the glass substrate. The first sub circuit board is positioned on the glass substrate and the electrode layer. The first sub-circuit board has a conductive via. The conductive through hole is positioned in the first sub-circuit board and positioned on the electrode layer. The first rewiring layer is located on the first sub-circuit board and the conductive through holes. The conductive through hole is electrically connected with the electrode layer and the first rewiring layer.
Description
Technical Field
The present disclosure relates to a hetero-substrate structure and a method for fabricating the same.
Background
In the process of Micro LED display, when the thin film transistor is to be bonded to an LED chip (e.g. a pixel unit), the bonding force between the electrode layer of the thin film transistor and the metal of the chip is low, which results in insufficient structural reliability. In addition, the thickness of the electrode layer of the thin film transistor is small, and is different from the thickness of the chip electroplating pad by several times, which causes the problem of uneven stress distribution during bonding, so that the stability of the chip is easy to be insufficient.
Disclosure of Invention
One aspect of the present disclosure is a hetero-substrate structure.
According to one embodiment of the present disclosure, a hetero-substrate structure includes a glass substrate, an electrode layer, a first sub-circuit board and a first redistribution layer. The electrode layer is located on the glass substrate. The first sub circuit board is located on the thin film transistor layer and the electrode layer. The first sub-circuit board has a conductive via. The conductive through hole is positioned in the first sub circuit board and positioned on the electrode layer. The first rewiring layer is located on the first sub-circuit board and the conductive through holes. The conductive through hole is electrically connected with the electrode layer and the first rewiring layer.
In an embodiment of the present disclosure, the hetero-substrate structure further includes an anti-oxidation layer, a pixel unit and a molding material. The anti-oxidation layer is located on the first redistribution layer. The anti-oxidation layer is made of gold. The pixel unit is located on the anti-oxidation layer. The molding material is located on the pixel unit, the anti-oxidation layer and the first sub circuit board.
In an embodiment of the present disclosure, the hetero-substrate structure further includes a dielectric layer, a second redistribution layer, an anti-oxidation layer, a pixel unit and a molding material. The dielectric layer is located on the first sub-circuit board and the first redistribution layer. The second redistribution layer is located on the dielectric layer and extends to the first redistribution layer. The anti-oxidation layer is located on the second redistribution layer. The material of the anti-oxidation layer is gold. The pixel unit is positioned on the oxidation resisting layer. The molding material is located on the pixel unit, the anti-oxidation layer and the dielectric layer.
In an embodiment of the present disclosure, the hetero-substrate structure further includes a thin film transistor layer. The thin film transistor layer is located between the glass substrate and the electrode layer.
One aspect of the present disclosure is a method for fabricating a hetero-substrate structure.
According to an embodiment of the present disclosure, a method for fabricating a hetero-substrate structure includes: forming a glass substrate, wherein the glass substrate is provided with an electrode layer, and the electrode layer is positioned on the glass substrate; forming a first sub-circuit board, wherein the first sub-circuit board is provided with a conductive through hole; and pressing the glass substrate, the first sub circuit board and the first rewiring layer to enable the first sub circuit board to be located between the glass substrate and the first rewiring layer, wherein the conductive through hole is electrically connected with the electrode layer and the first rewiring layer.
In an embodiment of the present disclosure, before the glass substrate, the first sub-circuit board and the first redistribution layer are bonded, the first sub-circuit board is in a semi-cured soft state. The method further comprises the step of applying heat treatment to solidify the first sub circuit board after the glass substrate, the first sub circuit board and the first rewiring layer are laminated.
In an embodiment of the present disclosure, the method further includes: patterning the first redistribution layer; forming an anti-oxidation layer on the first heavy wiring layer in an electroless plating manner, wherein the anti-oxidation layer is made of gold; arranging a pixel unit on the anti-oxidation layer; and forming a molding material on the pixel unit, the anti-oxidation layer and the first sub-circuit board.
In an embodiment of the present disclosure, before laminating the glass substrate, the first sub-circuit board and the redistribution layer, the method further includes: patterning the first redistribution layer; forming a dielectric layer on the first rewiring layer; forming an opening in the dielectric layer; and forming a second redistribution layer on the dielectric layer, wherein the second redistribution layer extends to the first redistribution layer in the opening.
In an embodiment of the present disclosure, the method further includes: forming an antioxidation layer on the second rewiring layer in an electroless plating manner, wherein the antioxidation layer is made of gold; arranging a pixel unit on the anti-oxidation layer; and forming a molding material on the pixel unit, the anti-oxidation layer and the dielectric layer.
In an embodiment of the present disclosure, the step of forming the first sub-circuit board includes: laser drilling a first sub circuit board to enable the first sub circuit board to be provided with a through hole; and filling conductive metal glue in the through hole to form a conductive through hole in the first sub circuit board.
In the above embodiments of the present disclosure, the first sub-circuit board of the hetero-substrate structure may be a connection structure for connecting the electrode layer and the first redistribution layer, so as to improve the bonding strength between the interfaces. In addition, the conductive through hole of the first sub-circuit board can be connected with the electrode layer and the first redistribution layer only by filling the conductive metal adhesive, and the hole filling is not required by an electroplating process, so that the manufacturing cost of electroplating equipment can be saved, and the environment is protected. And the conductive through holes of the first sub circuit board are connected with the electrode layer and the first rewiring layer by filling conductive metal glue, and holes are not filled by an electroplating process, so that the stress of the first sub circuit board when the first sub circuit board is connected with the electrode layer and the first rewiring layer can be reduced, and the glass substrate is prevented from being bent. The first sub circuit board and the first redistribution layer can be used as a welding pad for providing a pixel unit with a stable effect. Compared with the prior art, the bonding force of the first redistribution layer to the metal is good, and the first redistribution layer can be used as a welding pad, so that the structural reliability between the first redistribution layer and the pixel unit can be improved.
Drawings
One embodiment of the disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustrative purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
FIG. 1 illustrates a cross-sectional view of a hetero-substrate structure according to an embodiment of the present disclosure.
FIG. 2 is a cross-sectional view of a hetero-substrate structure according to another embodiment of the present disclosure.
FIG. 3 is a flow chart illustrating a method for fabricating a hetero-substrate structure according to an embodiment of the present disclosure.
Fig. 4 to 6 are cross-sectional views illustrating a method for fabricating a hetero-substrate structure according to an embodiment of the present disclosure at different stages.
Figures 7-8 illustrate cross-sectional views of a method of fabricating a hetero-substrate structure at different stages according to another embodiment of the present disclosure.
Fig. 9 to 13 illustrate cross-sectional views of a method for fabricating a hetero-substrate structure according to yet another embodiment of the present disclosure at different stages.
FIG. 14 is a cross-sectional view of a hetero-substrate structure according to yet another embodiment of the present disclosure.
FIG. 15 is a cross-sectional view of a hetero-substrate structure according to yet another embodiment of the present disclosure.
FIG. 16 is a cross-sectional view of a hetero-substrate structure according to yet another embodiment of the present disclosure.
[ description of main element symbols ]
100,100a,100b,100c,100d,100e: hetero-substrate structure
110: thin film transistor substrate
112: glass substrate
114: thin film transistor layer
116: electrode layer
120: first sub-circuit board
122: conductive vias
130: first rewiring layer
130a: second rewiring layer
140,140a: oxidation resistant layer
150,150a: pixel unit
160: molded material
170: dielectric layer
200: pressure-sensitive adhesive layer
210: PET glue line
O: opening of the container
S1: step (ii) of
S2: step (ii) of
S3: step (ii) of
V: through-hole
Detailed Description
The following disclosure of embodiments provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, the examples are merely examples and are not intended to be limiting. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Spatially relative terms, such as "at 8230," "below," "at 8230," "below," "under," "upper," "over 8230," "upper," and the like, may be used herein for convenience of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or fabrication in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as such.
Fig. 1 illustrates a cross-sectional view of a hetero-substrate structure 100 according to an embodiment of the present disclosure. The hetero-substrate structure 100 includes a glass substrate 112, an electrode layer 116, a first sub-circuit board 120, and a first re-wiring layer 130. For example, the material of the glass substrate 112 may include silicon, ceramic or sapphire, but is not limited thereto. The electrode layer 116 is located on the glass substrate 112. The material of the electrode layer 116 may include a transparent conductive film (ITO), copper, or aluminum, but not limited thereto. The hetero-substrate structure 100 further comprises a thin film transistor layer 114. The thin film transistor layer 114 is located between the glass substrate 112 and the electrode layer 116. In the present disclosure, the combination of the glass substrate 112, the thin film transistor layer 114 and the electrode layer 116 can be referred to as a thin film transistor substrate 110. The first sub-board 120 is located on the thin film transistor layer 114 and the electrode layer 116, and the first sub-board 120 has a conductive via 122. The conductive via 122 is located in the first sub-circuit board 120 and located on the electrode layer 116. In the present embodiment, the material of the first sub-circuit board 120 may include an insulating material, such as a Prepreg (PP), an Ajinomoto build up Film (ABF), a BT (Bimaleimide Triazine) resin, a Photosensitive dielectric (PID), or any one of semi-cured (B-Stage) polymers, but is not limited thereto.
The conductive via 122 of the first sub-circuit board 120 may be made of a conductive metal paste, and is manufactured by coating a Transient Liquid Phase Sintering (TLPS). The conductive vias 122 have conductive and heat conductive effects, are suitable for bonding with metal materials, and are not transformed back to liquid state by heat. The first redistribution layer 130 is located on the first sub-circuit board 120 and the conductive via 122, and the conductive via 122 electrically connects the electrode layer 116 and the first redistribution layer 130. The first redistribution layer 130 may be made of copper. In detail, the first redistribution layer 130 may be a copper foil, and may be etched by a subtractive process (etching) to form the first redistribution layer 130 as shown in fig. 1.
Specifically, the first sub-circuit board 120 of the hetero-substrate structure 100 may be coupled to the electrode layer 116 and the first redistribution layer 130, that is, the first sub-circuit board 120 may be regarded as a connection structure for coupling the electrode layer 116 and the first redistribution layer 130 to improve the coupling force between the interfaces. In addition, since the conductive vias 122 of the first sub-circuit board 120 can be connected to the electrode layer 116 and the first redistribution layer 130 only by filling the conductive metal paste, and the holes are not filled by an electroplating process, the manufacturing cost of electroplating equipment can be saved, and the method is more environment-friendly. In addition, the conductive vias 122 of the first sub-circuit board 120 are connected to the electrode layer 116 and the first redistribution layer 130 by filling conductive metal paste, and are not filled by an electroplating process, so that the stress generated when the first sub-circuit board 120 is connected to the electrode layer 116 and the first redistribution layer 130 can be reduced, and the glass substrate 112 is prevented from being bent. The first sub circuit board 120 and the first redistribution layer 130 may serve as pads for providing a stable effect to the pixel unit 150. Compared with the conventional technique, the bonding force of the first redistribution layer 130 to the metal is better, and the first redistribution layer 130 can be used as a bonding pad, so that the structural reliability between the first redistribution layer 130 and the pixel unit 150 can be increased.
In this embodiment, the hetero-substrate structure 100 further includes an anti-oxidation layer 140, a pixel unit 150, and a Molding material (Molding) 160. The anti-oxidation layer 140 is disposed on the first redistribution layer 130, and the anti-oxidation layer 140 may be made of gold. The oxidation resistant layer 140 covers the top surface of the first redistribution layer 130 to provide an oxidation resistant effect. The pixel unit 150 is located on the anti-oxidation layer 140, and the pixel unit 150 can electrically connect the first redistribution layer 130 and the anti-oxidation layer 140. The molding material 160 is disposed on the first sub-circuit board 120, the anti-oxidation layer 140 and the pixel unit 150. The molding material 160 covers the first sub-circuit board 120, the anti-oxidation layer 140 and the pixel unit 150 to provide insulation and protection effects.
It should be understood that the connection and function of the elements described above will not be repeated and will not be described in detail. In the following description, other forms of hetero-substrate structures will be described.
Fig. 2 illustrates a cross-sectional view of a hetero-substrate structure 100a according to another embodiment of the present disclosure. The hetero-substrate structure 100a includes a glass substrate 112, an electrode layer 116, a first sub-circuit board 120, and a first re-wiring layer 130. The hetero-substrate structure 100a further includes a thin film transistor layer 114. The combination of the glass substrate 112, the thin film transistor layer 114, and the electrode layer 116 may be referred to as a thin film transistor substrate 110. The first sub circuit board 120 has conductive through holes 122. The difference from the embodiment of fig. 1 is that the hetero-substrate structure 100a further includes a dielectric layer 170 and a second redistribution layer 130a. The dielectric layer 170 is located on the first sub-circuit board 120 and the first redistribution layer 130. For example, the material of the dielectric layer 170 may include a dielectric material. The second redistribution layer 130a is located on the dielectric layer 170, and the second redistribution layer 130a extends to the first redistribution layer 130 in the opening O, that is, the conductive via 122, the first redistribution layer 130, and the second redistribution layer 130a are electrically connected to each other. For example, the first redistribution layer 130 and the second redistribution layer 130a may be the same material.
The hetero-substrate structure 100a further includes an anti-oxidation layer 140a, a pixel unit 150a, and a molding material 160. The anti-oxidation layer 140a is disposed on the second redistribution layer 130a, and the anti-oxidation layer 140a may be made of gold. The anti-oxidation layer 140a may be formed on the second redistribution layer 130a by electroless plating. The pixel unit 150a is located on the anti-oxidation layer 140 a. The molding material 160 is disposed on the anti-oxidation layer 140a, the pixel unit 150a and the dielectric layer 170. The first sub circuit board 120 of the hetero-substrate structure 100a may bond the electrode layer 116 and the first redistribution layer 130 to improve a bonding force between interfaces, and the conductive via 122 of the first sub circuit board 120, the first redistribution layer 130, and the second redistribution layer 130a may form a multi-layer connection structure. The conductive via 122 of the first sub-circuit board 120 is electrically connected to the electrode layer 116, the first redistribution layer 130 and the second redistribution layer 130a.
In the following description, a method of fabricating the hetero-substrate structure 100 (see fig. 1) and the hetero-substrate structure 100a (see fig. 2) will be described. The connection and materials of the elements already described will not be repeated and will be described in detail.
Fig. 3 is a flow chart illustrating a method for fabricating a hetero-substrate structure according to an embodiment of the present disclosure. The manufacturing method of the hetero-substrate structure comprises the following steps. First, in step S1, a glass substrate is formed, wherein the glass substrate has an electrode layer on the glass substrate. Next, in step S2, a first sub circuit board is formed, wherein the first sub circuit board has a conductive via. Then, in step S3, the glass substrate, the first sub circuit board and the first redistribution layer are pressed to make the first sub circuit board located between the glass substrate and the redistribution layer, wherein the conductive via is electrically connected to the electrode layer and the redistribution layer. In the following description, each of the above-described steps will be described in detail.
Fig. 4 to 6 are cross-sectional views illustrating a method for fabricating a hetero-substrate structure according to an embodiment of the present disclosure at different stages. Referring to fig. 4, a glass substrate 112 and a thin film transistor layer 114 are formed, wherein the glass substrate 112 has an electrode layer 116, the thin film transistor layer 114 is disposed on the glass substrate 112, and the electrode layer 116 is disposed on the thin film transistor layer 114. In the present disclosure, the combination of the glass substrate 112, the thin film transistor layer 114 and the electrode layer 116 can be referred to as a thin film transistor substrate 110. Next, the first sub circuit board 120 is formed. Before the heat treatment, the first sub-circuit board 120 is in a semi-cured soft state, and a hole may be drilled in the first sub-circuit board 120 and filled with a conductive metal paste to form a conductive via 122.
Next, the first rewiring layer 130 is formed. In some embodiments, the material of the first redistribution layer 130 may be copper. In detail, the first redistribution layer 130 may be a copper foil, so the first redistribution layer 130 has a high coplanarity. Before the glass substrate 112, the first sub-circuit board 120 and the first redistribution layer 130 are bonded, the first sub-circuit board 120 is in a semi-cured soft state and has flexibility and viscosity, so the first sub-circuit board 120 can be used for bonding the thin film transistor substrate 110 and the first redistribution layer 130.
Referring to fig. 5, the glass substrate 112, the first sub-circuit board 120 and the first redistribution layer 130 are then laminated, such that the first sub-circuit board 120 is located between the tft substrate 110 and the first redistribution layer 130, wherein the conductive via 122 is electrically connected to the electrode layer 116 and the first redistribution layer 130. Then, after the glass substrate 112, the first sub-circuit board 120 and the first redistribution layer 130 are bonded, a heat treatment may be performed to cure the first sub-circuit board 120. As a result, the first sub-circuit board 120 firmly connects the tft substrate 110 and the first redistribution layer 130, so as to increase the structural reliability.
Referring to fig. 6, in some embodiments, the method further includes patterning the first redistribution layer 130, and forming an oxidation-resistant layer 140 on the patterned first redistribution layer 130 by electroless plating, wherein the oxidation-resistant layer 140 is made of gold. The oxidation resistant layer 140 covers the top surface of the first redistribution layer 130 to provide an oxidation resistant effect.
Next, referring back to fig. 1, the method further includes disposing the pixel unit 150 on the anti-oxidation layer 140, and forming a molding material 160 on the pixel unit 150, the anti-oxidation layer 140 and the first sub-circuit board 120, so as to form the hetero-substrate structure 100. The molding material 160 covers the first sub-circuit board 120, the anti-oxidation layer 140 and the pixel unit 150 to provide insulation and protection effects and increase the structural reliability of the hetero-substrate structure 100. Specifically, the manufacturing method of the present embodiment does not need to use solder or primer, and can effectively reduce the manufacturing cost of the hetero-substrate structure 100. In addition, since no solder is used, the bonding yield among the thin film transistor substrate 110, the first sub-circuit board 120 and the first redistribution layer 130 can be effectively improved, and the structural reliability of the hetero-substrate structure 100 can be further improved.
Figures 7-8 illustrate cross-sectional views of a method of fabricating a hetero-substrate structure at different stages according to another embodiment of the present disclosure. Referring to fig. 7, the difference from the embodiment of fig. 4 is that before the glass substrate 112, the first sub-circuit board 120 and the first redistribution layer 130 are laminated, the method further includes patterning the first redistribution layer 130, forming a dielectric layer 170 on the first redistribution layer 130, forming an opening O in the dielectric layer 170, and forming a second redistribution layer 130a on the dielectric layer 170, wherein the second redistribution layer 130a extends to the first redistribution layer 130 in the opening O. Also, the method further includes forming an oxidation resistant layer 140a on the second redistribution layer 130a in an electroless plating manner, wherein the oxidation resistant layer 140a is made of gold. The oxidation resistant layer 140a covers the top surface of the second redistribution layer 130a to provide an oxidation resistant effect.
Next, referring to fig. 8, the glass substrate 112, the first sub-circuit board 120 and the first redistribution layer 130 are laminated, such that the first sub-circuit board 120 is located between the tft substrate 110 and the first redistribution layer 130, wherein the conductive via 122 is electrically connected to the electrode layer 116, the first redistribution layer 130 and the second redistribution layer 130a, so as to form a multi-layer connection structure. Since the first sub-circuit board 120 is in a semi-cured soft state and has flexibility and viscosity, the first sub-circuit board 120 can be bonded to the tft substrate 110 and the first redistribution layer 130.
Next, returning to fig. 2, in some embodiments, the method further includes disposing a pixel unit 150a on the anti-oxidation layer 140a, and forming a molding material 160 on the anti-oxidation layer 140a, the pixel unit 150a, and the dielectric layer 170. In this way, the hetero-substrate structure 100a as shown in fig. 2 can be obtained. Specifically, the manufacturing method of the hetero-substrate structure 100a does not need to use solder and primer, and can effectively reduce the manufacturing cost of the hetero-substrate structure 100a. In addition, since no solder is used, the bonding yield among the thin film transistor substrate 110, the first sub-circuit board 120 and the first redistribution layer 130 can be effectively improved, and the structural reliability of the hetero-substrate structure 100a can be further improved.
In the present embodiment, the first sub-circuit board 120 of the hetero-substrate structure 100a may join the electrode layer 116 and the first redistribution layer 130 to improve the joining force between the interfaces, and the conductive via 122 of the first sub-circuit board 120 is electrically connected to the electrode layer 116, the first redistribution layer 130 and the second redistribution layer 130a, so that the hetero-substrate structure 100a has a multi-layer connection structure.
In the following description, another method for fabricating a hetero-substrate structure will be described. The connection and materials of the elements are not repeated here, and will be described in detail.
Fig. 9 to 13 are cross-sectional views illustrating a method for fabricating a hetero-substrate structure according to yet another embodiment of the present disclosure at different stages. Referring to fig. 9, a first redistribution layer 130 and a Pressure Sensitive Adhesive (PSA) layer 200 are formed on two opposite sides of the first sub-circuit board 120. Next, a PET (Polyethylene terephthalate) layer 210 is adhered to the pressure-sensitive adhesive layer 200 of the first sub-circuit board 120. Next, the first sub circuit board 120, the pressure sensitive adhesive layer 200 and the PET adhesive layer 210 are laser drilled to make the first sub circuit board 120 have a through hole V, so as to form the structure shown in fig. 9.
Referring to fig. 9 and 10, the conductive metal paste is filled in the through hole V to form a conductive through hole 122 in the first sub-circuit board 120. After the conductive vias 122 are formed, the PET glue layer 210 can be removed to form the structure shown in fig. 10.
Referring to fig. 11, next, a glass substrate 112 is formed, wherein the glass substrate 112 has an electrode layer 116, and the electrode layer 116 is disposed on the glass substrate 112. Next, the structure shown in fig. 10 is turned upside down by 90 degrees, so that the conductive via 122 is closer to the electrode layer 116 than the first redistribution layer 130.
Referring to fig. 11 and 12, after the pressure-sensitive adhesive layer 200 of the first sub-circuit board 120 is removed, the glass substrate 112, the first sub-circuit board 120 and the first redistribution layer 130 are pressed together, so that the first sub-circuit board 120 is located between the glass substrate 112 and the first redistribution layer 130, wherein the conductive via 122 is electrically connected to the electrode layer 116 and the first redistribution layer 130.
Referring to fig. 13, next, the first redistribution layer 130 is etched to form a line. After the first re-wiring layer 130 forms a line, a pixel unit 150 is formed on the first re-wiring layer 130 to form a hetero-substrate structure 100b as shown in fig. 13. Next, a molding material 160 as shown in fig. 1 may be formed on the pixel unit 150 and the first sub circuit board 120 to cover the pixel unit 150 and the first sub circuit board 120.
In the following description, other forms of hetero-substrate structures will be described. The connection and materials of the elements are not repeated here, and will be described in detail.
Fig. 14 illustrates a cross-sectional view of a hetero-substrate structure 100c according to yet another embodiment of the present disclosure. Referring to fig. 14, the embodiment is different from the embodiment of fig. 1 in that the thin film transistor layer 114 has a thin film transistor structure for active driving, and the conductive via 122 extends into the thin film transistor layer 114 in addition to electrically connecting the electrode layer 116 and the first redistribution layer 130 to electrically connect the thin film transistor structure 114 for active driving. The combination of the glass substrate 112, the thin film transistor layer 114, and the electrode layer 116 may be referred to as a thin film transistor substrate 110. In addition, the hetero-substrate structure 100c is similar to the manufacturing process of fig. 4 to 6, except that the manufacturing process of the glass substrate 112 and the thin film transistor layer 114 is different.
Fig. 15 illustrates a cross-sectional view of a hetero-substrate structure 100d according to yet another embodiment of the present disclosure. Referring to fig. 15, the difference from the embodiment of fig. 2 is that the thin film transistor layer 114 has a thin film transistor structure for active driving, and the conductive via 122 extends into the thin film transistor layer 114 in addition to electrically connecting the electrode layer 116 and the first redistribution layer 130, wherein the conductive via 122 electrically connects the thin film transistor layer 114, the electrode layer 116, the first redistribution layer 130 and the second redistribution layer 130a to form a multi-layer connection structure. In addition, the hetero-substrate structure 100d is similar to the manufacturing process of fig. 7 and 8 except that the manufacturing process of the glass substrate 112 and the thin film transistor layer 114 are different.
Specifically, since the conductive vias 122 of the first sub-circuit board 120 can be connected to the thin film transistor layer 114, the electrode layer 116 and the first redistribution layer 130 only by filling the conductive metal paste, the first sub-circuit board 120 does not need to be filled by an electroplating process, which saves the manufacturing cost of electroplating equipment and is more environment-friendly.
Figure 16 illustrates a cross-sectional view of a hetero-substrate structure 100e according to yet another embodiment of the present disclosure. Referring to fig. 16, the embodiment of fig. 2 is different in that the glass substrate 112 does not have the thin film transistor layer 114 (see fig. 2) thereon, and the electrode layer 116 has a multi-layer structure, which may be regarded as a rewiring structure. The hetero-substrate structure 100e may be applied in a passive driving circuit. In addition, the fabrication process of the hetero-substrate structure 100e is similar to that of fig. 7 and 8, except that the fabrication process of the glass substrate 112 and the electrode layer 116 is different.
Specifically, the conductive vias 122 of the first sub-circuit board 120 are connected to the thin film transistor layer 114, the electrode layer 116 and the first redistribution layer 130 by filling conductive metal paste, and are not filled by an electroplating process, so that the stress generated when the first sub-circuit board 120 is connected to the thin film transistor layer 114, the electrode layer 116 and the first redistribution layer 130 can be reduced, and the glass substrate 112 is prevented from being bent.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (10)
1. A hetero-substrate structure, comprising:
a glass substrate;
an electrode layer on the glass substrate;
a first sub circuit board located on the glass substrate and the electrode layer, wherein the first sub circuit board has a conductive via located in the first sub circuit board and on the electrode layer; and
the first redistribution layer is located on the first sub-circuit board and the conductive via, wherein the conductive via is electrically connected with the electrode layer and the first redistribution layer.
2. The hetero-substrate structure of claim 1, further comprising:
an anti-oxidation layer on the first redistribution layer, wherein the anti-oxidation layer is made of gold;
a pixel unit located on the oxidation resistant layer; and
and the molding material is positioned on the pixel unit, the anti-oxidation layer and the first sub circuit board.
3. The hetero-substrate structure of claim 1, further comprising:
a dielectric layer on the first sub-circuit board and the first redistribution layer;
a second redistribution layer on the dielectric layer and extending to the first redistribution layer;
an anti-oxidation layer positioned on the second rewiring layer, wherein the anti-oxidation layer is made of gold;
a pixel unit located on the anti-oxidation layer; and
and the molding material is positioned on the pixel unit, the oxidation resisting layer and the dielectric layer.
4. The hetero-substrate structure of claim 1, further comprising:
and the thin film transistor crystal layer is positioned between the glass substrate and the electrode layer.
5. A method for fabricating a hetero-substrate structure, comprising:
forming a glass substrate, wherein the glass substrate is provided with an electrode layer, and the electrode layer is positioned on the glass substrate;
forming a first sub circuit board, wherein the first sub circuit board is provided with a conductive through hole; and
and pressing the glass substrate, the first sub circuit board and the first redistribution layer to enable the first sub circuit board to be positioned between the glass substrate and the first redistribution layer, wherein the conductive through hole is electrically connected with the electrode layer and the first redistribution layer.
6. The method of claim 5, wherein the first sub-circuit board is in a semi-cured soft state before the glass substrate, the first sub-circuit board and the first redistribution layer are bonded, the method further comprising:
after the glass substrate, the first sub-circuit board and the first rewiring layer are pressed, heat treatment is carried out to solidify the first sub-circuit board.
7. The method of claim 5, further comprising:
patterning the first redistribution layer;
forming an oxidation resistant layer on the first redistribution layer in an electroless plating manner, wherein the oxidation resistant layer is made of gold;
arranging a pixel unit on the anti-oxidation layer; and
and forming a molding material on the pixel unit, the anti-oxidation layer and the first sub-circuit board.
8. The method of claim 5, further comprising, before bonding the glass substrate, the first sub-circuit board and the redistribution layer together:
patterning the first redistribution layer;
forming a dielectric layer on the first redistribution layer;
forming an opening in the dielectric layer; and
and forming a second redistribution layer on the dielectric layer, wherein the second redistribution layer extends to the first redistribution layer in the opening.
9. The method of claim 8, further comprising:
forming an oxidation-resistant layer on the second redistribution layer in an electroless plating manner, wherein the oxidation-resistant layer is made of gold;
arranging pixel units on the anti-oxidation layer; and
and forming a molding material on the pixel unit, the anti-oxidation layer and the dielectric layer.
10. The method of claim 5, wherein forming the first sub-circuit board comprises:
laser drilling the first sub circuit board to enable the first sub circuit board to be provided with a through hole; and
and filling conductive metal paste in the through hole to form the conductive through hole in the first sub-circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110776992.7A CN115602688A (en) | 2021-07-09 | 2021-07-09 | Heterogeneous substrate structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110776992.7A CN115602688A (en) | 2021-07-09 | 2021-07-09 | Heterogeneous substrate structure and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115602688A true CN115602688A (en) | 2023-01-13 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110776992.7A Pending CN115602688A (en) | 2021-07-09 | 2021-07-09 | Heterogeneous substrate structure and manufacturing method thereof |
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| Country | Link |
|---|---|
| CN (1) | CN115602688A (en) |
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2021
- 2021-07-09 CN CN202110776992.7A patent/CN115602688A/en active Pending
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