CN115598890A - Array substrate and display panel - Google Patents
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- CN115598890A CN115598890A CN202211249705.8A CN202211249705A CN115598890A CN 115598890 A CN115598890 A CN 115598890A CN 202211249705 A CN202211249705 A CN 202211249705A CN 115598890 A CN115598890 A CN 115598890A
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Classifications
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- G—PHYSICS
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/133357—Planarisation layers
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
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- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The application provides an array substrate and display panel, includes: a substrate; a plurality of pixel electrodes disposed on the substrate; the common electrode is arranged on the substrate, is stacked with the plurality of pixel electrodes in the thickness direction of the array substrate, is overlapped with the plurality of pixel electrodes and is electrically insulated, and forms a part of a storage capacitor together with each pixel electrode; the pixel electrode concave-convex structure comprises a pixel electrode concave-convex structure and a pixel electrode convex structure; and/or the common electrode comprises a common electrode concave-convex structure overlapped with at least one pixel electrode, and the common electrode concave-convex structure comprises a common electrode concave structure and a common electrode convex structure. According to the pixel electrode structure, at least one pixel electrode comprises the pixel electrode concave-convex structure, and/or the common electrode comprises the common electrode concave-convex structure overlapped with at least one pixel electrode, so that the capacitance value of at least one storage capacitor is increased, and the crosstalk risk is reduced.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate and a display panel.
Background
With the rapid development of 5G communication technology, virtual Reality (VR) technology is in a rapid development stage. At present, the requirement of the virtual reality technology on the pixel density of a display screen is very high, and the pixel area of a single pixel of the display screen is extremely small, however, for the liquid crystal display screen, the cross talk risk occurs when the pixel area is small.
Therefore, how to improve the crosstalk risk caused by the smaller pixel area of the liquid crystal display screen is a technical problem to be solved.
Disclosure of Invention
An object of the present application is to provide an array substrate and a display panel, so as to increase a capacitance value of a storage capacitor of the array substrate and reduce a crosstalk risk when the display panel displays.
In order to realize the purpose, the technical scheme is as follows:
an array substrate, comprising:
a substrate;
a plurality of pixel electrodes disposed on the substrate; and
a common electrode which is disposed on the substrate, is stacked with the plurality of pixel electrodes in a thickness direction of the array substrate, is overlapped with and electrically insulated from the plurality of pixel electrodes, and forms a part of a storage capacitor together with each pixel electrode;
at least one pixel electrode comprises a pixel electrode concave-convex structure, and the pixel electrode concave-convex structure comprises a pixel electrode concave structure and a pixel electrode convex structure; and/or the presence of a gas in the gas,
the common electrode includes a common electrode concave-convex structure overlapping at least one of the pixel electrodes, and the common electrode concave-convex structure includes a common electrode concave structure and a common electrode convex structure.
In the array substrate of some embodiments, at least one of the pixel electrodes includes a pixel electrode concave-convex structure disposed adjacent to the pixel electrode convex structure;
the common electrode comprises a common electrode concave-convex structure overlapped with at least one pixel electrode, the common electrode concave structure and the common electrode convex structure are arranged adjacently, the common electrode concave structure is overlapped with the pixel electrode concave structure, and the common electrode convex structure is overlapped with the pixel electrode convex structure.
In the array substrate of some embodiments, the array substrate further includes:
the pixel structure comprises a substrate, a plurality of pixel electrodes and a plurality of common electrodes, wherein the pixel electrodes and the common electrodes are arranged on one side, away from the substrate, of the first planarization layer, the surface, away from the substrate, of the first planarization layer is provided with a planarization layer concave-convex structure, the planarization layer concave-convex structure comprises a planarization layer concave structure and a planarization layer convex structure, the planarization layer concave structure is overlapped with the pixel electrode concave structure, and the planarization layer convex structure is overlapped with the pixel electrode convex structure.
In the array substrate of some embodiments, the common electrode is located between the first planarization layer and the plurality of pixel electrodes in a thickness direction of the array substrate, and the planarization layer convex structure is in contact with the common electrode convex structure; or the like, or, alternatively,
in the thickness direction of the array substrate, the pixel electrodes are located between the first planarization layer and the common electrode, and the planarization layer convex structure is in contact with the pixel electrode convex structure.
In the array substrate of some embodiments, the first planarization layer has a thickness at the position of the planarization layer convex structure larger than that of the first planarization layer at the position of the planarization layer concave structure.
In the array substrate of some embodiments, the material of the first planarization layer includes an organic material, and the thickness of the first planarization layer is greater than or equal to 0.5 micrometers and less than or equal to 3 micrometers.
In the array substrate of some embodiments, the array substrate further includes:
the passivation layer is arranged between the public electrode and the pixel electrodes and is in contact with the public electrode and the pixel electrodes, the passivation layer comprises a passivation layer concave-convex structure, the passivation layer concave-convex structure comprises a passivation layer concave structure and a passivation layer convex structure, the passivation layer concave structure is overlapped with the public electrode concave structure and the pixel electrode concave structure, and the passivation layer convex structure is in contact with the public electrode convex structure and the pixel electrode convex structure.
In the array substrate of some embodiments, the array substrate further includes:
and the second planarization layer is arranged on the substrate and is positioned on one side, away from the substrate, of the pixel electrodes and the common electrode.
In the array substrate of some embodiments, the array substrate further includes:
the driving circuit layer is arranged on the substrate, the pixel electrodes and the public electrode are arranged on one side, away from the substrate, of the driving circuit layer, the driving circuit layer comprises a plurality of thin film transistors, and one pixel electrode is electrically connected with at least one thin film transistor.
A display panel comprises the array substrate of some embodiments.
Has the advantages that: the application provides an array substrate and display panel, include pixel electrode concave-convex structure through at least one pixel electrode, pixel electrode concave-convex structure includes pixel electrode concave-convex structure and pixel electrode convex structure, and/or, public electrode includes the public electrode concave-convex structure who overlaps with at least one pixel electrode, public electrode concave-convex structure includes public electrode concave-convex structure and public electrode convex structure, just to the area between at least one pixel electrode of increase and the public electrode, and then increase at least one storage capacitor's capacitance value, the crosstalk risk that exists when improving display panel's storage capacitor is less.
Drawings
FIG. 1 is a schematic cross-sectional view of a display panel according to an embodiment of the present application;
FIG. 2 is a schematic plan view of the pixel electrode and the first planarization layer shown in FIG. 1;
FIG. 3 is a schematic cross-sectional view of a display panel according to another embodiment of the present application;
fig. 4 is a schematic cross-sectional view of a display device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1 and fig. 2, fig. 1 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure, and fig. 2 is a schematic plan view of a pixel electrode and a first planarization layer shown in fig. 1.
In the present embodiment, the display panel 100 is a liquid crystal display panel. The display panel 100 has a display area and a non-display area located at the periphery of the display area. The display panel 100 includes an array substrate 101 and a color filter substrate 102, the array substrate 101 is disposed opposite to the color filter substrate 102, and a liquid crystal layer (not shown) is disposed between the array substrate 101 and the color filter substrate 102.
In the present embodiment, the array substrate 101 includes a substrate 10, a driving circuit layer 20, a first planarization layer 30, a common electrode 40, a passivation layer 50, a plurality of pixel electrodes 60, and a second planarization layer 70.
In the present embodiment, the substrate 10 is a glass substrate. The driving circuit layer 20 is disposed on the substrate 10. The driving circuit layer 20 includes a light-shielding layer 201, a buffer layer 202, and a plurality of thin film transistors T.
The light-shielding layer 201 is used for shielding light and is located in the display region. The light-shielding layer 201 is disposed on the surface of the substrate 10. The material of the light-shielding layer 201 includes a metal, but is not limited thereto, and the material of the light-shielding layer may also include a black organic material.
The buffer layer 202 covers the light-shielding layer 201 and the substrate 10, and is located in the display region and the peripheral region. The material of the buffer layer 202 includes, but is not limited to, silicon nitride, silicon oxide, or silicon oxynitride.
The thin film transistors T are disposed on the surface of the buffer layer 202 away from the substrate 10 and located in the display region. The thin film transistors T are top gate thin film transistors, but are not limited thereto, and the thin film transistors T may be bottom gate thin film transistors. The plurality of thin film transistors T are low-temperature polysilicon thin film transistors, metal oxide transistors or amorphous silicon transistors.
Each thin film transistor T includes an active layer 203, a gate insulating layer 204, a gate electrode 205, an interlayer insulating layer 206, and source-drain electrodes 207.
The active layer 203 is disposed on the buffer layer 202 and overlaps the light-shielding layer 201. The active layer 203 has a channel region and two heavily doped regions, which are located at opposite sides of the channel region. The channel region of the active layer 203 overlaps with the light-shielding layer 201 so that the light-shielding layer 201 shields light incident on the channel region of the active layer 203.
It should be noted that the channel region of the active layer 203 is not subjected to an ion doping process, and the heavily doped region of the active layer 203 is subjected to an ion doping process, where the ion doping process uses ions including, but not limited to, phosphorus ions.
In addition, when the active layer 203 is a low temperature polysilicon active layer, the active layer 203 further has two lightly doped regions, and one lightly doped region is disposed between one heavily doped region and the channel region. The ion doping concentration of the heavily doped region of the active layer 203 is greater than that of the lightly doped region of the active layer 203.
The gate insulating layer 204 covers the active layer 203 and the buffer layer 202, and is located in the display region and the non-display region. The material of the gate insulating layer 204 includes, but is not limited to, silicon nitride, silicon oxide, or silicon oxynitride.
The gate 205 is disposed on the gate insulating layer 204 and overlaps the channel region of the active layer 203. The material of the gate 205 includes, but is not limited to, molybdenum, aluminum, titanium, copper, or silver.
The interlayer insulating layer 206 covers the gate electrode 205 and the gate insulating layer 204, and is located in the display region and the non-display region. The material of the interlayer insulating layer 206 includes, but is not limited to, silicon nitride, silicon oxide, or silicon oxynitride.
The source-drain electrode 207 is disposed on the interlayer insulating layer 206 and located in the display region. The source-drain electrode 207 includes a source 2071 and a drain 2072, the source 2071 is in contact with one heavily doped region of the active layer 203 through a first contact hole penetrating the interlayer insulating layer 206 and the gate insulating layer 204, and the drain 2072 is in contact with the other heavily doped region of the active layer 203 through a second contact hole penetrating the interlayer insulating layer 206 and the gate insulating layer 204.
The driving circuit layer 20 further includes a transfer electrode 2073 located in the non-display region, the transfer electrode 2073 and the source/drain electrode 207 are disposed in the same layer, and the material of the transfer electrode 2073 is the same as that of the source/drain electrode 207. The transmission electrode 2073 and the source/drain electrode 207 are formed by patterning the same metal layer.
In the present embodiment, the first planarization layer 30 is disposed on the substrate 10 and located in the display region and the non-display region. The first planarization layer 30 covers the source-drain electrodes 207, the transfer electrodes 2073 and the interlayer insulating layer 206 of the driving circuit layer 20.
The material of the first planarizing layer 30 includes organic materials including, but not limited to, polyimide, polyacrylate, or silicone. Specifically, the preparation material of the first planarization layer 30 includes an organic photoresist.
The thickness of the first planarizing layer 30 is greater than or equal to 0.5 micrometers and less than or equal to 3 micrometers. For example, the thickness of the first planarizing layer 30 is 1 micron, 1.5 microns, 1.8 microns, 2.0 microns, 2.4 microns, 2.8 microns, or 3 microns.
The surface of the first planarization layer 30 remote from the substrate 10 has a planarization layer concave-convex structure 303 thereon, the planarization layer concave-convex structure 303 includes a planarization layer concave-structure 302 and a planarization layer convex-structure 301, and the planarization layer concave-structure 302 is disposed adjacent to the planarization layer convex-structure 301.
The shape of a cross section of the planarizing convex structure 301 in a direction parallel to the thickness direction of the display panel 100 is rectangular, trapezoidal, semicircular, semi-elliptical, or other shapes. The cross-section of the planarizing concave structure 302 in a direction parallel to the thickness direction of the display panel 100 has a rectangular, inverted trapezoidal, or other shape.
Specifically, in the present embodiment, the shape of the cross section of the planarizing convex structure 301 in the direction parallel to the thickness direction of the display panel 100 is rectangular. The shape of a cross section of the planarizing concave structure 302 in a direction parallel to the thickness direction of the display panel 100 is rectangular.
It is understood that, in other embodiments, the cross section of the convex planarization layer structure 301 in the direction parallel to the thickness direction of the display panel 100 may also be trapezoidal, and the cross section of the concave planarization layer structure 302 in the direction parallel to the thickness direction of the display panel 100 may be inverted trapezoidal, so as to reduce the risk of breaking the thin film layers formed on the convex planarization layer structure 301.
The thickness of the first planarization layer 30 at the position of the planarization layer convex structure 301 is greater than the thickness of the first planarization layer 30 at the position of the planarization layer concave structure 302.
Specifically, the thickness of the first planarization layer 30 at the position of the convex planarization layer structure 301 is greater than or equal to 1.5 micrometers and less than or equal to 3 micrometers, for example, the thickness of the first planarization layer 30 at the position of the convex planarization layer structure 301 is 1.8 micrometers, 2 micrometers, 2.2 micrometers, 2.4 micrometers, 2.6 micrometers or 3 micrometers. The thickness of the first planarization layer 30 at the position of the planarization concave structure 302 is greater than 0 micron and less than or equal to 2 microns, for example, the thickness of the first planarization layer 30 at the position of the planarization concave structure 302 is 0.5 micron, 0.8 micron, 1.0 micron, 1.2 micron, 1.5 micron, 1.8 micron or 2 microns.
It should be noted that, when the material for preparing the first planarizing layer 30 is an organic photoresist, the first planarizing layer 30 is exposed by using a half-tone mask, and after the exposed first planarizing layer 30 is developed, a portion of the first planarizing layer 30 is thinned to form a planarizing concave structure 302, and an unweaved portion of the first planarizing layer 30 is a planarizing convex structure 301.
The recess depth H1 of the planarizing recessed structure 302 is greater than 0 micrometers and less than or equal to 1 micrometer, so as to further reduce the risk of breaking a film layer subsequently formed in the planarizing recessed structure 302. For example, the recess depth H1 of the planarizing recessed structure 302 is 0.1 microns, 0.3 microns, 0.5 microns, 0.7 microns, 0.9 microns, or 1 micron.
In the present embodiment, the common electrode 40 is loaded with a common voltage when the display panel 100 displays. The common electrode 40 is positioned in the display area and the non-display area. In the thickness direction of the array substrate 101, the common electrode 40 is located on the side of the first planarization layer 30 away from the substrate 10, and the common electrode 40 is in contact with the surface of the first planarization layer 30 away from the substrate 10.
In addition, the common electrode 40 is electrically connected to the transfer electrode 2073 through a third contact hole located in the non-display region and penetrating the first planarization layer 30, so that a common voltage signal is transferred to the common electrode 40 through the transfer electrode 2073. The common electrode 40 is provided with an opening corresponding to the drain 2072, and the opening penetrates the common electrode 40 in the thickness direction of the common electrode 40.
The common electrode 40 is a block-shaped transparent electrode. The material of the common electrode 40 includes a transparent conductive material including indium tin oxide or indium zinc oxide.
The common electrode 40 includes a common electrode concave-convex structure 403, the common electrode concave-convex structure 403 includes a common electrode concave structure 402 and a common electrode convex structure 401, and the common electrode concave structure 402 is disposed adjacent to the common electrode convex structure 401. The common electrode convex structure 401 is in contact with the planarization layer convex structure 301 and covers the planarization layer convex structure 301. The common electrode recess structure 402 overlaps the planarization layer recess structure 302.
It should be noted that, after the common electrode 40 is formed on the surface of the first planarization layer 30 away from the substrate 10, the common electrode convex structure 401 is formed on the planarization layer convex structure 301, and the planarization layer concave structure 302 is formed in the planarization layer concave structure 302, and the thickness of the common electrode 40 at the position where the common electrode concave structure 402 and the common electrode convex structure 401 are located is the same or tends to be the same.
In the present embodiment, the plurality of pixel electrodes 60 are loaded with data voltages when the display panel 100 displays, and each pixel electrode 60 is electrically connected to at least one thin film transistor T.
In the present embodiment, the material of the plurality of pixel electrodes 60 includes a transparent conductive material, and the transparent conductive material includes, but is not limited to, indium tin oxide or indium zinc oxide. Each pixel electrode 60 includes a pixel electrode main body portion 604 and slits 605 distributed in the pixel electrode main body portion 604, the pixel electrode main body portion 604 is a transparent conductive portion, and the slits 605 penetrate the pixel electrode 60 in the thickness direction of the pixel electrode 60.
It will be appreciated that in other embodiments, each pixel electrode 60 may also be a monolithic and non-slit transparent conductive portion.
In the embodiment, in the thickness direction of the array substrate 101, the plurality of pixel electrodes 60 are located on the side of the first planarization layer 30 away from the substrate 10, and the plurality of pixel electrodes 60 are located on the same layer and are electrically insulated from each other.
The common electrode 40 and the plurality of pixel electrodes 60 are stacked in the thickness direction of the array substrate 101, the passivation layer 50 is disposed between the common electrode 40 and the plurality of pixel electrodes 60, and the passivation layer 50 is in contact with both the common electrode 40 and the plurality of pixel electrodes 60, so that the common electrode 40 and the plurality of pixel electrodes 60 are electrically insulated. The common electrode 40 overlaps the plurality of pixel electrodes 60, and each pixel electrode 60, a portion of the common electrode 40 overlapping each pixel electrode 60, and the passivation layer 50 together constitute a storage capacitor.
It should be noted that each pixel electrode 60 is connected to the drain electrode of one thin film transistor T through a fourth contact hole penetrating the passivation layer 50 and the first planarization layer 30, and the source electrode of one thin film transistor T is connected to the data line. When the thin film transistor T in the off state has a leakage current, when the data voltage transmitted by the data line changes, the changed data voltage charges the storage capacitor through the leakage current, and the smaller the capacitance value of the storage capacitor is, the larger the voltage changed by charging the storage capacitor due to the leakage current is, the larger the risk of crosstalk is.
It should be noted that, a horizontal component of an electric field formed by the common voltage loaded on the common electrode 40 and the data voltage loaded on the pixel electrode 60 acts on the liquid crystal in the liquid crystal layer, and the liquid crystal deflects under the action of the horizontal component of the electric field to control the light transmittance of the display panel 100, so as to enable the display panel to realize display.
Specifically, in the present embodiment, the common electrode 40 is located between the first planarizing layer 30 and the plurality of pixel electrodes 60, and the common electrode concave-convex structure 403 of the common electrode 40 overlaps at least one pixel electrode 60.
The concave-convex structure 403 of the common electrode 40 of the array substrate 101 of the display panel 100 of this embodiment is overlapped with at least one pixel electrode 60, so that under the condition that the area of a single pixel of the display panel is not changed, the facing area between the common electrode 40 and the at least one pixel electrode 60 is increased, and further, the capacitance value of the storage capacitor formed by the common electrode 40 and the at least one pixel electrode 60 is increased, so as to improve the crosstalk risk existing in the smaller capacitance value of the storage capacitor.
In this embodiment, at least one pixel electrode 60 includes a pixel electrode concave-convex structure 603, the pixel electrode concave-convex structure 603 includes a pixel electrode concave structure 602 and a pixel electrode convex structure 601, the pixel electrode concave structure 602 is disposed adjacent to the pixel electrode convex structure 601, and the thicknesses of the pixel electrodes 60 at the positions where the pixel electrode concave structure 602 and the pixel electrode convex structure 601 are located are the same or tend to be the same.
The common electrode concave structure 402 overlaps with the pixel electrode concave structure 602, the common electrode convex structure 401 overlaps with the pixel electrode convex structure 601, the planarization layer concave structure 302 overlaps with the pixel electrode concave structure 602, and the planarization layer convex structure 301 overlaps with the pixel electrode convex structure 601.
Under the condition that the area of a single pixel of the display panel is not changed, at least one pixel electrode 60 comprises a pixel electrode concave-convex structure 603, a common electrode concave structure 402 is overlapped with the pixel electrode concave structure 602, and a common electrode convex structure 401 is overlapped with a pixel electrode convex structure 601, so that the facing area between the common electrode 40 and at least one pixel electrode 60 is further increased, the capacitance value of a storage capacitor formed by the common electrode 40 and at least one pixel electrode 60 is further increased, and the crosstalk risk caused by the smaller capacitance value of the storage capacitor is further improved.
It is understood that in other embodiments, a plurality of pixel electrodes 60 may be located between the first planarization layer 30 and the common electrode 40, the plurality of pixel electrodes 60 are in contact with the surface of the first planarization layer 30 away from the substrate 10, the planarization layer convex structure 301 is in contact with the pixel electrode convex structure 601, the planarization layer concave structure 302 overlaps the pixel electrode concave structure 602, the common electrode convex structure 401 overlaps the pixel electrode convex structure 601, and the common electrode concave structure 402 overlaps the pixel electrode concave structure 602.
In this embodiment, as shown in fig. 1 and fig. 2, the pixel electrode convex structure 601 is located at a part of the pixel electrode main body portion 604, and the pixel electrode convex structure 601 does not overlap the slit 605, so as to avoid that the pixel electrode convex structure 601 overlaps the slit 605 to affect the horizontal component of the electric field formed between the pixel electrode 60 and the common electrode 40, and further affect the transmittance of the display panel to light. Meanwhile, the pixel electrode concave structure 602 overlaps with another part of the pixel electrode main body portion 604 in addition to the slit 605, and the other part of the pixel electrode main body portion 604 is a part of the pixel electrode main body portion 604 except for the pixel electrode convex structure 601.
In the present embodiment, the passivation layer 50 includes a passivation layer concave-convex structure 503, the passivation layer concave-convex structure 503 includes a passivation layer concave structure 502 and a passivation layer convex structure 501, the passivation layer concave structure 502 overlaps with both the common electrode concave structure 402 and the pixel electrode concave structure 602, and the passivation layer convex structure 501 contacts with both the common electrode convex structure 401 and the pixel electrode convex structure 601.
The passivation layer 50 is an inorganic insulating layer. The passivation layer 50 has a thickness greater than or equal to 800 angstroms and less than or equal to 1500 angstroms.
It should be noted that, after the passivation layer 50 is formed on the common electrode 40 and the first planarization layer 30, the passivation layer convex structure 501 is formed on the common electrode convex structure 401, the passivation layer concave structure 502 is formed in the common electrode concave structure 402 and the planarization layer concave structure 302, and the thickness of the passivation layer 50 at the position where the passivation layer concave structure 502 and the passivation layer convex structure 501 are located is the same or tends to be the same.
In the present embodiment, the second planarization layer 70 plays a role of planarizing the array substrate 101. The second planarization layer 70 is disposed on the substrate 10 and is located on a side of the plurality of pixel electrodes 60 and the common electrode 40 away from the substrate 10.
Specifically, the second planarization layer 70 covers the plurality of pixel electrodes 60 and the passivation layer 50, and the surface of the second planarization layer 70 remote from the substrate 10 is a flat surface.
The second planarizing layer 70 is an organic layer. The material of the second planarizing layer 70 is the same as that of the first planarizing layer 30. Specifically, the preparation material of the second planarization layer 70 is an organic photoresist.
The thickness of the second planarizing layer 70 is greater than or equal to 0.5 micrometers and less than or equal to 3 micrometers. The thickness of the second planarization layer 70 at the position of the convex planarization layer structure 301 is smaller than the thickness of the second planarization layer 70 at the position of the concave planarization layer structure 302.
Please refer to fig. 3, which is a schematic cross-sectional view of a display panel according to another embodiment of the present disclosure. The display panel shown in fig. 3 is substantially similar to the display panel shown in fig. 1, and the same parts are not repeated, except that the surface of the first planarization layer 30 away from the substrate 10 is flat, the common electrode 40 is disposed on the surface of the flat first planarization layer 30 away from the substrate 10, and the common electrode 40 is also flat or tends to be flat; the passivation layer 50 includes a passivation layer concave-convex structure 503 overlapping the at least one pixel electrode 60, the passivation layer concave-convex structure 503 includes a passivation layer concave structure 502 and a passivation layer convex structure 501, the passivation layer convex structure 501 is in contact with a portion of the pixel electrode main body portion 604 of the at least one pixel electrode 60, the passivation layer concave structure 502 overlaps the slit of the at least one pixel electrode 60 and another portion of the pixel electrode main body portion 604 of the at least one pixel electrode 60, and the another portion of the pixel electrode main body portion 604 is a portion of the pixel electrode 60 not in contact with the passivation layer convex structure 501.
In addition, in the present embodiment, at least one pixel electrode 60 includes a pixel electrode concave-convex structure 603, the pixel electrode concave-convex structure 603 includes a pixel electrode concave structure 602 and a pixel electrode convex structure 601, the pixel electrode concave structure 602 is disposed adjacent to the pixel electrode convex structure 601, the pixel electrode convex structure 601 is in contact with the passivation layer convex structure 501 and is a part of the pixel electrode main body portion 604, and the pixel electrode concave structure 602 overlaps the passivation layer concave structure 502.
In the present embodiment, the thickness of the passivation layer 50 at the position of the passivation layer convex structure 501 is greater than the thickness of the passivation layer 50 at the position of the passivation layer concave structure 502.
Specifically, the thickness of the passivation layer 50 at the position of the passivation layer convex structure 501 is greater than or equal to 800 angstroms and less than or equal to 1500 angstroms, for example, the thickness of the passivation layer 50 at the position of the passivation layer convex structure 501 is 800 angstroms, 1000 angstroms, 1200 angstroms, 1300 angstroms or 1500 angstroms.
The thickness of the passivation layer 50 at the position of the passivation layer concave structure 502 is greater than or equal to 200 angstroms and less than or equal to 1200 angstroms, for example, the thickness of the passivation layer 50 at the position of the passivation layer concave structure 502 is 200 angstroms, 400 angstroms, 600 angstroms, 800 angstroms, 1000 angstroms or 1200 angstroms.
It should be noted that, in the present embodiment, a portion of the passivation layer 50 is thinned through a yellow light process and an etching process to form the passivation layer concave structure 502, an un-thinned portion of the passivation layer 50 is the passivation layer convex structure 501, a portion of the pixel electrode 60 formed on the passivation layer convex structure 501 correspondingly forms the pixel electrode convex structure 601, and a portion of the pixel electrode 60 formed in the passivation layer concave structure 502 correspondingly forms the pixel electrode concave structure 602.
The pixel electrode of the display panel comprises the pixel electrode concave-convex structure, the pixel electrode concave-convex structure enables the area of the pixel electrode to be increased, and then the area between the pixel electrode and the common electrode is increased, so that the capacitance value of the storage capacitor is increased, and the risk of crosstalk when the display panel displays is reduced.
It is understood that in other embodiments, the pixel electrode 60 may be disposed on the surface of the flat first planarization layer 30 away from the substrate 10, and the pixel electrode 60 is also flat or tends to be flat; a passivation layer 50 covering the pixel electrode 60 and the first planarization layer 30, the passivation layer 50 including a passivation layer concave-convex structure 503 overlapping at least one pixel electrode 60, the passivation layer concave-convex structure 503 including a passivation layer concave structure 502 and a passivation layer convex structure 501; the common electrode 40 is disposed on the surface of the passivation layer 50 away from the substrate 10, and at this time, the common electrode concave-convex structure 403 includes a common electrode concave structure 402 and a common electrode convex structure 401, the common electrode convex structure 401 is in contact with the passivation layer convex structure 501, and the common electrode concave structure 402 overlaps with the passivation layer concave structure 502.
Please refer to fig. 4, which is a schematic cross-sectional view of a display device according to an embodiment of the present application. The display device 300 is applied to a virtual reality display screen. The display device 300 is a liquid crystal display device, the display device 300 includes the display panel 100 and the backlight module 200 of any of the above embodiments, and the display panel 100 is located at the light emitting side of the backlight module 200.
The above description of the embodiments is only for assisting understanding of the technical solutions and their core ideas of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. An array substrate, comprising:
a substrate;
a plurality of pixel electrodes disposed on the substrate; and
a common electrode which is disposed on the substrate, is stacked with the plurality of pixel electrodes in a thickness direction of the array substrate, is overlapped with and electrically insulated from the plurality of pixel electrodes, and forms a part of a storage capacitor together with each pixel electrode;
at least one pixel electrode comprises a pixel electrode concave-convex structure, and the pixel electrode concave-convex structure comprises a pixel electrode concave structure and a pixel electrode convex structure; and/or the presence of a gas in the gas,
the common electrode includes a common electrode concave-convex structure overlapping at least one of the pixel electrodes, and the common electrode concave-convex structure includes a common electrode concave structure and a common electrode convex structure.
2. The array substrate of claim 1, wherein at least one of the pixel electrodes comprises a pixel electrode concave-convex structure, and the pixel electrode concave structure is arranged adjacent to the pixel electrode convex structure;
the common electrode comprises a common electrode concave-convex structure overlapped with at least one pixel electrode, the common electrode concave structure and the common electrode convex structure are arranged adjacently, the common electrode concave structure is overlapped with the pixel electrode concave structure, and the common electrode convex structure is overlapped with the pixel electrode convex structure.
3. The array substrate of claim 2, further comprising:
the pixel electrode and the common electrode are positioned on one side, far away from the substrate, of the first planarization layer, the surface, far away from the substrate, of the first planarization layer is provided with a planarization layer concave-convex structure, the planarization layer concave-convex structure comprises a planarization layer concave structure and a planarization layer convex structure, the planarization layer concave structure is overlapped with the pixel electrode concave structure, and the planarization layer convex structure is overlapped with the pixel electrode convex structure.
4. The array substrate of claim 3, wherein the common electrode is located between the first planarization layer and the plurality of pixel electrodes in a thickness direction of the array substrate, and the planarization layer convex structure is in contact with the common electrode convex structure; or the like, or, alternatively,
in the thickness direction of the array substrate, the pixel electrodes are located between the first planarization layer and the common electrode, and the planarization layer convex structure is in contact with the pixel electrode convex structure.
5. The array substrate of claim 3, wherein the first planarizing layer has a thickness at the locations of the planarizing layer convex structures that is greater than a thickness of the first planarizing layer at the locations of the planarizing layer concave structures.
6. The array substrate of claim 3, wherein the material of the first planarization layer comprises an organic material, and the thickness of the first planarization layer is greater than or equal to 0.5 micrometers and less than or equal to 3 micrometers.
7. The array substrate of claim 2 or 3, further comprising:
the passivation layer is arranged between the public electrode and the pixel electrodes and is in contact with the public electrode and the pixel electrodes, the passivation layer comprises a passivation layer concave-convex structure, the passivation layer concave-convex structure comprises a passivation layer concave structure and a passivation layer convex structure, the passivation layer concave structure is overlapped with the public electrode concave structure and the pixel electrode concave structure, and the passivation layer convex structure is in contact with the public electrode convex structure and the pixel electrode convex structure.
8. The array substrate of claim 1, further comprising:
and the second planarization layer is arranged on the substrate and is positioned on one side, away from the substrate, of the pixel electrodes and the common electrode.
9. The array substrate of claim 1, further comprising:
the driving circuit layer is arranged on the substrate, the pixel electrodes and the public electrode are arranged on one side, far away from the substrate, of the driving circuit layer, the driving circuit layer comprises a plurality of thin film transistors, and one pixel electrode is electrically connected with at least one thin film transistor.
10. A display panel comprising the array substrate according to any one of claims 1 to 9.
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