CN115588972B - Short circuit current limiting control system - Google Patents
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- H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
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Abstract
The application relates to a short circuit current limiting control system. The system comprises a first current limiter, a second current limiter, a switch unit and a detection system; the first end of the first current limiter is connected with the detection system, the second end of the first current limiter is respectively connected with the first end and the second end of the switch unit, and the third end of the first current limiter is connected with the third end of the switch unit; the first end of the second current limiter is connected with the detection system, the second end of the second current limiter is respectively connected with the first end and the second end of the switch unit, and the third end of the second current limiter is connected with the third end of the switch unit; according to the relationship between the average value of the sum of three-phase current squares of two adjacent time windows and the magnitude of a fault threshold, whether a short-circuit current fault occurs is judged, the anti-interference performance and the detection speed are balanced, and the reliability and the accuracy of the system are improved through the double redundancy arrangement of a current limiter and a control loop, so that the short-circuit current limiting control system with the advantages of rapidity, robustness and accuracy is provided.
Description
Technical Field
The application relates to the technical field of power grid short-circuit protection, in particular to a short-circuit current-limiting control system.
Background
With the development of the power system in China, the load density and the capacity of the power grid are rapidly increased, and the occurrence of short-circuit current faults in the 500kV alternating-current power grid is frequent.
Currently, there are three types of current limiters used in high voltage power system engineering projects, namely series resonant current limiters, switched reactance current limiters, and current limiters based on coupling split reactors.
The current limiter (HCSR-FCL) based on the high-coupling split reactor has the advantages of advanced technology, economy, high efficiency, strong practicability and the like, and is widely applied to solving the current limiting technical problem of voltage levels of 500kV and above.
Because of various disturbances in the grid, most current limiters react slowly at the time of failure, failing to detect the failure and take protective action within 3 ms.
Therefore, there is an urgent need for a current limiter that combines rapidity, robustness and accuracy, limits short-circuit current to a specified time, and ensures the safety of the power system.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a short-circuit current limiting control system that can achieve the combination of rapidity, robustness and accuracy.
The embodiment of the application provides a short circuit current limiting control system, which comprises a first current limiter, a second current limiter, a switch unit and a detection system;
the first end of the first current limiter is connected with the detection system, the second end of the first current limiter is respectively connected with the first end and the second end of the switch unit, and the third end of the first current limiter is connected with the third end of the switch unit;
the first end of the second current limiter is connected with the detection system, the second end of the second current limiter is respectively connected with the first end and the second end of the switch unit, and the third end of the second current limiter is connected with the third end of the switch unit;
the detection system is used for:
acquiring three-phase current of the line to be tested, and determining a first fault detection parameter according to the three-phase current and the following formula:
wherein ,
time window W corresponding to time t 1 Average value of the sum of squares of all three-phase currents, < >>
For time window W 2 Average value of sum of squares of all three-phase currents, wherein the time window W 1 And a time window W 2 All are related to timetWindow of->
For time window W 1 And a time window W 2 Is used for the time difference of (a),T s a time length for each of the time windows;
if the first fault detection parameter is larger than a fault threshold value, judging that a short-circuit current fault occurs;
and under the condition that a short-circuit current fault of a circuit to be detected is detected, a current limiting protection command is sent to a third end of the switch unit, the current limiting protection command is used for driving the switch unit to be in a short-circuit protection state, and when the switch unit is in the short-circuit protection state, the first current limiter and the second current limiter are connected into a loop of the circuit to be detected.
In one embodiment, the detection system is further configured to:
calculating a sum of squares SSC (t) of the three-phase currents from the three-phase currents:
wherein ,i a (t)、i b (t)andi c (t)each of which represents the current of each phase,I m representing the amplitude of the current.
In one embodiment, the detection system is further configured to:
if the sum of squares of the three-phase currents and the fault detection parameter meet any one of the following constraint conditions, determining that a short-circuit current fault occurs:
wherein ,
in order to be a value of the blockage,THis the fault threshold.
In one embodiment, the detection system is further configured to:
if the sum of squares of the three-phase currents and the fault detection parameter meet the following constraint conditions, judging that no short-circuit current fault occurs:
in one embodiment, the detection system includes a current sensor, a controller, and a memory; the current sensors are connected in series on each phase line of the line to be tested in a one-to-one correspondence manner, and the current sensors are used for collecting current on the serial line;
the controller is respectively connected with the current sensors, the memory and the switch unit, and is used for distributing three circulating queues with fixed lengths in the memory so as to store the current acquired by each current sensor in a one-to-one correspondence manner;
the controller is used for:
reading the three-phase current from the circular queue;
determining a second fault detection parameter according to the three-phase current and the following formula:
wherein ,S 1_QA (t)、S 1_QB (t)andS 1_QC (t)the single-phase current square sums of the A phase, the B phase and the C phase in a first data window are respectively shown;S 2_QA (t)、S 2_QB (t)andS 2_QC (t)the single-phase current square sum of the phase A, the phase B and the phase C in a second data window is respectively represented, and the first data window and the second data window are partially overlapped;
and when the second fault detection parameter is larger than a fault threshold value, judging that a short-circuit current fault occurs.
In one embodiment, the controller is configured to, in configuring each of the circular queues in the memory, have a time window length ofL 1 +d+L 2； wherein ,L 1 +drepresenting the length of the first data window in the queue,L 2 +dis the length of the second data window in the queue,dis the overlap length of two of the first and second data windows.
In one embodiment, the controller is configured to configure a circular queue of the memory based on the following expression:
wherein ,f s is the sampling frequency of the current sensor.
In one embodiment, the switching unit includes:
the first end of the first fast switch controller is connected with the second end of the first current limiter and the second end of the second current limiter respectively;
the first end of the second fast switch controller is connected with the second end of the first current limiter and the second end of the second current limiter respectively;
the reactor loop is connected with a plurality of fast switches and reactors in series, and each fast switch is correspondingly connected with the first fast switch controller and the second fast switch controller;
the controller is used for sending a current limiting protection command to the first fast switch controller and the second fast switch controller when judging that the circuit to be tested has a short-circuit current fault, so that the first fast switch controller and the second fast switch controller control corresponding fast switches to be closed, and the first current limiter and the second current limiter are put into the circuit to be tested for current limiting protection.
In one embodiment, the detection system configures the length of the time window to be half of the steady current period of the line under test.
In one embodiment, the controller is connected to the current sensor and the switching unit by optical fiber communication.
The short circuit current limiting control system has at least the following beneficial effects: the short circuit current limiting control system comprises a first current limiter, a second current limiter, a switch unit and a detection system. The first end of the first current limiter is connected with the detection system, the second end of the first current limiter is respectively connected with the first end and the second end of the switch unit, and the third end of the first current limiter is connected with the third end of the switch unit; the first end of the second current limiter is connected with the detection system, the second end of the second current limiter is respectively connected with the first end and the second end of the switch unit, and the third end of the second current limiter is connected with the third end of the switch unit. The detection system judges whether a short-circuit current fault occurs according to the relation between the average value of the sum of three-phase current squares of two adjacent time windows and the magnitude of a fault threshold, if the short-circuit current fault occurs, a current limiter is needed to be put into the control process for current limiting protection, the control process balances the anti-interference performance and the detection speed based on the ratio of the three-phase current squares to the average value as a judgment basis, and the reliability and the accuracy of the system are improved through the double redundancy arrangement of the current limiter and the control loop, so that the short-circuit current limiting control system with the advantages of rapidity, robustness and accuracy is provided.
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In order to more clearly illustrate the technical solutions of embodiments or conventional techniques of the present application, the drawings required for the descriptions of the embodiments or conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a schematic diagram illustrating an operation sequence of a short-circuit current limiting control system according to an embodiment;
FIG. 2 is a schematic diagram of a short circuit current limiting control system according to an embodiment;
FIG. 3 is a schematic diagram of RTC value changes at steady state and short circuit current faults in one embodiment;
FIG. 4 is a schematic diagram of a time window configured in a short circuit current limit control system in one embodiment;
FIG. 5 is a schematic diagram of a circular queue in one embodiment;
FIG. 6 is a schematic circuit diagram of a simulation experiment in one embodiment;
FIG. 7 is a diagram of RTC values under noise in one embodiment.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Examples of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that the terms "first," "second," and the like, as used herein, may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or be connected to the other element through intervening elements. Further, "connection" in the following embodiments should be understood as "electrical connection", "communication connection", and the like if there is transmission of electrical signals or data between objects to be connected.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, the term "and/or" as used in this specification includes any and all combinations of the associated listed items.
In view of the problem that the time period from occurrence of the short-circuit current fault to zero crossing is inconsistent, real-time performance of detection needs to be paid attention to when designing the system. In one embodiment, a short circuit current limit control system is provided, as shown in FIG. 2, comprising a first current limiter 202, a second current limiter 204, a switching unit 206, and a detection system 208. The detection system 208 is a system having current detection and current data processing functions and capable of controlling the state of the switching unit 206.
A first end of the first current limiter 202 is connected to the detection system 208, a second end of the first current limiter 202 is connected to a first end and a second end of the switch unit 206, respectively, and a third end of the first current limiter 202 is connected to a third end of the switch unit 206;
the first end of the second current limiter 204 is connected to the detection system 208, the second end of the second current limiter 204 is connected to the first end and the second end of the switch unit 206, respectively, and the third end of the second current limiter 204 is connected to the third end of the switch unit 206.
Through the redundant arrangement of the first current limiter 202 and the second current limiter 204, reliability is improved, each current limiter is connected with two control ends of the switch unit 206, the first control end and the second control end of the switch unit 206 are respectively used for controlling the current limiter connected with the first control end and the second control end to throw in and cut out a circuit to be tested, based on the connection mode, not only the redundant arrangement of the current limiter is realized, but also the redundant design of a control branch in the switch unit 206 is realized, and reliability is further improved.
The detection system 208 is configured to:
acquiring three-phase current of the line to be tested, and determining a first fault detection parameter according to the three-phase current and the following formula:
wherein ,
time window W corresponding to time t 1 Average value of the sum of squares of all three-phase currents, < >>
For time window W 2 Average value of sum of squares of all three-phase currents, wherein the time window W 1 And a time window W 2 All are related to timetWindow of->
For time window W 1 And a time window W 2 Is used for the time difference of (a),T s a time length for each of the time windows;
if the first fault detection parameter is larger than a fault threshold value, judging that a short-circuit current fault occurs;
in the case that a short-circuit current fault of the line to be tested is detected, a current limiting protection command is sent to the third terminal of the switch unit 206, where the current limiting protection command is used to drive the switch unit 206 to be in a short-circuit protection state, and when the switch unit 206 is in the short-circuit protection state, the first current limiter 202 and the second current limiter 204 are connected to a loop of the line to be tested.
Let it be assumed that at t 0 Short-circuit current fault occurs at moment, at t 1 The time of day short circuit current fault detection system 208 detects a fault. Short-circuit current fault detection time T a = t 1 
t 0 And (5) calculating. The system immediately sends a current limit protection command to fast switch controller 2082 with switch contacts at T b Separation after time, T b Time is the switching time inherent to fast switching. Over a period of arcing time T c Thereafter, the arc in the fast switch is at t 3 (t 3 Zero crossing for short circuit current) to be extinguished until the switching process is completed. Fig. 1 shows the operation sequence of the system.
In this embodiment, when a short-circuit current fault occurs, in order to reduce the impact on the relay protection device, the system's fast switching speed must be faster than the high-voltage ac circuit breaker, i.e., its switching time must be less than the circuit breaker in the relay protection system. Using the ratio of the sum of squares of the characteristics before and after the short-circuit currentAlthough the detection speed can be increased as much as possible as a detection standard, erroneous judgment is likely to occur when there is a spike in the amplitude ratio waveform at two points. Thus, to improve the anti-jamming capability of the 500kV AC grid short-circuit current fault detection system 208, the system uses the ratio of the average value of the sum of three-phase current squares (SSC) of two dataRTC(t) As a detection criterion for short-circuit current faults.
When the power system is operating under normal conditions,SSC(t) At any time, a fixed value, and therefore,RTC(t) And is also a fixed value, independent of the equivalent impedance and phase angle of the power system. In one exampleRTC(t) And approximately 1.0. Even though the three phases of the power system are in an asymmetric state, as long as the load is in a steady state, due to the periodic nature of the current,RTC(t) Still about 1.0.
When a short-circuit current fault occurs,SSC(t) With the increase of the fault current, thenRTC(t)>1.0. When (when)RTC(t)>THWhen the system judges that the line has short-circuit current fault,THis an empirical threshold greater than 1.0 as the fault threshold TH. When a short-circuit current fault occurs,RTC(t) The occurrence of the fault point G1 and the fault detection point GJ shown in fig. 3 are rapidly increased, so that the short-circuit current fault is sensitively detected as shown in fig. 3.
Judging whether a short-circuit current fault occurs according to the relation between the average value of the sum of three-phase current squares of two adjacent time windows and the magnitude of a fault threshold, if so, putting a current limiter into the control process for current limiting protection, balancing anti-interference performance and detection speed based on the ratio of the three-phase current squares and the average value as a judgment basis, and improving the reliability of the system through redundancy setting, so that a short-circuit current limiting control system with the advantages of rapidity, robustness and accuracy is provided.
In one embodiment, the detection system 208 is further configured to:
calculating a sum of squares SSC (t) of the three-phase currents from the three-phase currents:
wherein ，i a (t)、i b (t)Andi c (t)each of which represents the current of each phase,I m representing the amplitude of the current.
Assume that:
wherein ,i a (t)、i b (t) and i c (t) The currents of phases A, B and C, respectively.
In the normal working state, the current is in three-phase symmetry,SSC（t) Is a constant that is related to the current amplitude only and does not change during the current period, and can be expressed as:
wherein ,I m representing the amplitude of the current.
For any timetTwo time windows W are defined 1 and W2 All are of lengtht. Then time window W 1 And a time window W 2 The corresponding time intervals are respectively T-T s , t]And [ T-T ] s -,t-]As shown in fig. 4.
Is provided with
Wherein WDS (a, b) represents window [ a, b ]]Average value of the sum of squares of all three-phase current data.
Then for time window W 1 And a time window W 2 ：
Is provided with
Wherein the value of RTC (t) is the fault criterion of the short-circuit current fault detection method.
In order to avoid the false response of the method caused by too small denominator of the equation of the fault parameter RTC (t) when the line is empty, a locking criterion is added, namely a blocking value is set
. When the line under test is operating at maximum load, blocking value +.>
Should be greater than or equal to the SSC value, and therefore, the criterion for a short circuit current fault can be expressed as: />
。
In one embodiment, the detection system 208 is further configured to:
if the sum of squares of the three-phase currents and the fault detection parameter meet the following constraint conditions, determining that a short-circuit current fault occurs:
at this time, it is explained that the line is not in idle running, and a short-circuit current fault occurs, and at this time, the switch unit 206 needs to be controlled to be in a current-limiting protection state, so that the current-limiting circuit is put into operation, and short-circuit current-limiting protection is performed. Wherein (1)>
In order to be a value of the blockage,THis the fault threshold.
The detection system 208 is also configured to satisfy the following constraints on the sum of squares of the three-phase currents and the fault detection parameters
It is determined that the line under test is empty, and at this time, the first and second restrictors 204 are not required to be controlled to limit current.
In one embodiment, the detection system 208 is further configured to:
if the sum of squares of the three-phase currents and the fault detection parameter meet the following constraint conditions, it is determined that a short-circuit current fault does not occur,
. At this time, the line to be tested is operated under the condition of no-load and no short-circuit current fault occurs.
In one embodiment, the detection system 208 includes a current sensor 2086, a controller 2082, and a memory 2084; the current sensors 2086 are connected in series on each phase line of the line to be tested in a one-to-one correspondence manner, and the current sensors 2086 are used for collecting current on the serial line;
the controller 2082 is respectively connected to the current sensors 2086, the memory 2084 and the switch unit 206, and the controller 2082 is configured to allocate three circulation queues with fixed lengths in the memory 2084, so as to store the current collected by each current sensor 2086 in a one-to-one correspondence manner;
the controller 2082 is configured to:
reading the three-phase current from the circular queue;
determining a second fault detection parameter according to the three-phase current and the following formula:
wherein ,S 1_QA (t)、S 1_QB (t)andS 1_QC (t)the single-phase current square sums of the A phase, the B phase and the C phase in a first data window are respectively shown;S 2_QA (t)、S 2_QB (t)andS 2_QC (t)the single-phase current square sum of the phase A, the phase B and the phase C in a second data window is respectively represented, and the first data window and the second data window are partially overlapped;
and when the second fault detection parameter is larger than a fault threshold value, judging that a short-circuit current fault occurs.
The controller 2082 and the components connected thereto may be combined using fiber optic communications. For example, the controller 2082 may be connected to the current sensor 2086 and the first and second fast switch controllers 2062, 2064 via optical fibers. The connection of the controller 2082 to the first fast switch controller 2062 and the second fast switch controller 2064 may be implemented by current limiters (202 and 204) as described in fig. 2.
In one embodiment, the controller 2082 is configured to, when configuring each of the circular queues in the memory 2084, have a time window length ofL 1 +d+L 2； wherein ,L 1 +drepresenting the length of the first data window in the queue,L 2 +dis the length of the second data window in the queue,dis the overlap length of two of the first and second data windows.
Three fixed length circular queues are allocated in memory 2084 (which may be memory)Q A 、Q B AndQ C ) Corresponding to sampled data received in parallel from three optical channels. Each queue has a length ofL 1 +d+L 2 As shown in fig. 5.L 1 +dRepresenting the first data window in the queueF 1 ,E 1 ]Is provided for the length of (a),dis the overlap length of the two windows,L 2 +dis the second window of data in the queue [F 2 ,E 2 ]Is a length of (c).
Assuming that three-phase current data are received at a time and sent to the corresponding circular queues, respectively, the first and second data windows are in one phase currentSSC(t) The method comprises the following steps:
wherein ,x i (t) Representing elements in the circular queue.
Therefore, the fault criteriaRTC 1 (t) Expressed as:
wherein ,S 1_QA (t)、S 1_QB (t)andS 1_QC (t)respectively representing the sum of squares of currents of A, B, C three phases in a first data window;S 2_QA (t)、S 2_QB (t)andS 2_QC (t)the sum of squares of the currents of the three phases A, B, C over the second data window are represented, respectively. If it isRTC 1 (t) The value of (2) is greater than the set thresholdTHA short-circuit current fault is considered to occur.
In one embodiment, the controller 2082 is configured to configure a circular queue of the memory 2084 based on the following expression:
wherein ,f s is the sampling frequency of the current sensor 2086.
In one embodiment, as shown in fig. 2, the switching unit 206 includes:
a first fast switch controller 2062, the first fast switch controller 2062 having a first end connected to the second end of the first current limiter 202 and the second end of the second current limiter 204, respectively;
a second fast switch controller 2064, the first end of the second fast switch controller 2064 being connected to the second end of the first current limiter 202 and the second end of the second current limiter 204, respectively;
a reactor SC loop, on which a plurality of fast switches (1) (2) (3) (4)) and a reactor SC are connected in series, each of the fast switches being correspondingly connected to the first fast switch controller 2062 and the second fast switch controller 2064;
the controller 2082 is configured to send a current limiting protection command to the first fast switch controller 2062 and the second fast switch controller 2064 when determining that the line to be tested has a short-circuit current fault, so that the first fast switch controller 2062 and the second fast switch controller 2064 control the corresponding fast switch to be closed, and the first current limiter 202 and the second current limiter 204 are put into the line to be tested for current limiting protection.
In one embodiment, the reactor may be a high coupling split reactor and the current limiter is a high coupling split reactor based current limiter (HCSR-FCL).
In one embodiment, the detection system 208 configures the time window to be half the period of the steady current of the line under test. Since the period of the steady state current is T and the period of the current square wave is T/2, the current square wave data with window length of T/2 can reflect all the characteristics of the current. Thus, the time window lengthT s T/2 may be taken. When T is 20ms, T s =10 ms. The time interval t reflects the overlapping and updating characteristics of the data in the two time windows. When (when)ΔtWhen set to 1ms, the failure detection method can operate with optimal performance.
In one embodiment, the controller 2082 is coupled to the current sensor 2086 and the switching unit 206 via fiber optic communications. Fiber optic communication implementations may be implemented using the FT3 protocol.
In order to verify the performance of the designed system, real-time and anti-interference simulation experiments are carried out in a real-time digital simulation system (real-time digital simulation system, RTDS).
Building a simulation platform shown in fig. 6:
in RTDS, three-phase current is output by RTDS through the analog signal output GTAO interface, and the amplification range is 0-20A. The 3 collectors (current sensors 2086) sample the line current under test at a rate of 10 samples/second and then send the sampled current data to the controller 2082 via 3 fiber channels. The controller 2082 receives three-channel current data in parallel, and performs short-circuit current fault detection. If a failure of the reactor SC is detected, a 12V DC I/O signal will be output.
Meanwhile, in order to observe the performance of fault detection, waveforms of a current signal and an I/O signal and 12V direct current are superimposed on an oscilloscope, and the time T required for fault detection is directly measured, as shown in the following formula:
wherein ,t sampling representing the time spent by the harvester;t transfer representing the time taken for data conversion;t detection representing the time taken for fault detection;t IO representing the time taken to transmit the I/O signal.
The experiment detects four short-circuit current faults, and each type of test is carried out by adopting different initial phase angles of faults and different fault positions. The initial phase angle of the faults is 0-180 degrees, and the faults occur at the front, middle and tail ends of the electric wire respectively at intervals of 20 degrees. Threshold valueTHSet to 1.5. The required average detection times for the four short-circuit current faults are shown in table 1. The farther the fault position is, the longer the detection time is, and the average detection time of four faults is less than 1ms, which indicates that the system has better real-time performance.
Table 1 detection times for four short-circuit current faults
In order to verify the anti-interference capability of the system, two common interferences, namely harmonic and noise, are respectively added into the power grid model to test the RTC value of the system, and when the RTC value is smaller than a threshold value, the system is indicated to have no erroneous judgment. The experimental results are shown in FIG. 7. The measured values of the RTC are smaller than a threshold value of 1.5, which shows that the method has good anti-interference capability.
According to the short-circuit current limiting control system provided by the embodiment of the application, firstly, a 500kV alternating-current reactor-current limiter system is designed, and secondly, a short-circuit fault detection algorithm based on the ratio of the three-phase current square sum is adopted, so that the real-time performance and the anti-interference performance of short-circuit current fault detection are met, and the fault detection system 208 is verified through simulation on an RTDS platform. Experimental results show that the system provided by the application can effectively, accurately and real-timely detect the short-circuit fault and timely limit the short-circuit current.
In the description of the present specification, reference to the terms "some embodiments," "other embodiments," "desired embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (9)
1. The short circuit current limiting control system is characterized by comprising a first current limiter, a second current limiter, a switch unit and a detection system;
the first end of the first current limiter is connected with the detection system, the second end of the first current limiter is respectively connected with the first end and the second end of the switch unit, and the third end of the first current limiter is connected with the third end of the switch unit;
the first end of the second current limiter is connected with the detection system, the second end of the second current limiter is respectively connected with the first end and the second end of the switch unit, and the third end of the second current limiter is connected with the third end of the switch unit;
the detection system is used for:
acquiring three-phase current of a line to be tested, and determining a first fault detection parameter according to the three-phase current and the following formula:
if the first fault detection parameter is larger than a fault threshold value, judging that a short-circuit current fault occurs;
under the condition that a short-circuit current fault of a circuit to be detected is detected, a current limiting protection command is sent to a third end of the switch unit, the current limiting protection command is used for driving the switch unit to be in a short-circuit protection state, and when the switch unit is in the short-circuit protection state, the first current limiter and the second current limiter are connected into a loop of the circuit to be detected;
the detection system comprises a current sensor, a controller and a memory; the current sensors are connected in series on each phase line of the line to be tested in a one-to-one correspondence manner, and the current sensors are used for collecting current on the serial line;
the controller is respectively connected with the current sensors, the memory and the switch unit, and is used for distributing three circulating queues with fixed lengths in the memory so as to store the current acquired by each current sensor in a one-to-one correspondence manner;
the controller is used for:
reading the three-phase current from the circular queue;
determining a second fault detection parameter according to the three-phase current and the following formula:
and when the second fault detection parameter is larger than the fault threshold value, judging that a short-circuit current fault occurs.
2. The system of claim 1, wherein the detection system is configured to:
calculating a sum of squares SSC (t) of the three-phase currents from the three-phase currents:
3. The system of claim 2, wherein the detection system is further configured to:
if the sum of squares of the three-phase currents and the fault detection parameter meet any one of the following constraint conditions, determining that a short-circuit current fault occurs:
4. The system of claim 2, wherein the detection system is further configured to:
if the sum of squares of the three-phase currents and the fault detection parameter meet the following constraint conditions, judging that no short-circuit current fault occurs:
5. the system of any one of claims 1 to 4, wherein the controller is configured to, in configuring each of the circular queues in the memory, have a time window length ofL 1 +d+L 2； wherein ,L 1 +drepresenting the length of the first data window in the queue,L 2 +dis the length of the second data window in the queue,dis the overlap length of two of the first and second data windows.
6. The system of claim 5, wherein the controller is configured to configure the circular queue of the memory based on the following expression:
7. The system of claim 1, wherein the switching unit comprises:
the first end of the first fast switch controller is connected with the second end of the first current limiter and the second end of the second current limiter respectively;
the first end of the second fast switch controller is connected with the second end of the first current limiter and the second end of the second current limiter respectively;
the reactor loop is connected with a plurality of fast switches and reactors in series, and each fast switch is correspondingly connected with the first fast switch controller and the second fast switch controller;
the controller is used for sending a current limiting protection command to the first fast switch controller and the second fast switch controller when judging that the circuit to be tested has a short-circuit current fault, so that the first fast switch controller and the second fast switch controller control corresponding fast switches to be closed, and the first current limiter and the second current limiter are put into the circuit to be tested for current limiting protection.
8. The system of claim 2, wherein the detection system configures the length of the time window to be half of a steady current period of the line under test.
9. The system of claim 1, wherein the controller is in communication with the current sensor and the switching unit via optical fibers.
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