CN115586924A - Control system and implementation method for controlling low-speed peripheral by single instruction set soft core - Google Patents

Abstract

The invention discloses a control system and an implementation method for controlling low-speed peripherals by a single instruction set soft core. The field programmable logic array device realizes a single instruction set soft core, and the soft core comprises a scheduling controller, an instruction memory, a result memory and an external interface; the scheduling controller acquires a fixed format instruction from the instruction memory, executes operation through a peripheral interface and stores an operation result into a result memory; the processor modifies the contents of the instruction memory via the high speed bus and accesses the result store to obtain the results of the operation. The invention solves the problem of low processor efficiency caused by overlong time for operating the low-speed peripheral equipment by the high-performance processor.

Description

Control system and implementation method for controlling low-speed peripheral by single instruction set soft core

Technical Field

The invention relates to an embedded system, in particular to a control system and an implementation method for controlling a low-speed peripheral by a single instruction set soft core.

Background

The embedded system is a special computer system which takes application as a center, is based on modern computer technology and can flexibly cut software and hardware modules according to user requirements (function, reliability, cost, volume, power consumption, environment and the like). Embedded systems are application-centric, with the goal of meeting the specific needs of the user. In addition, the application occasions of the embedded system mostly have higher requirements on reliability and real-time performance, so that a special system serving for a specific application is the main mode of the embedded system, and the universality and the expandability of the system are not emphasized.

With the deep development of microelectronic technology and integrated circuit technology, the performance of a core device, namely a processor, of an embedded system is continuously improved, and the dominant frequency exceeds 1GHz. However, low speed peripherals such as IIC, SPI, UART, etc. still exist in the system. In order to implement complete system functions, if the processor directly controls the low-speed peripheral, since there is a significant gap between the high main frequency of the processor and the low data bandwidth of the low-speed peripheral (for example, the typical clock frequency of the IIC is 400k, and one operation time needs tens of us or more), the processor needs a lot of time to wait for the response of the low-speed peripheral, which results in inefficient execution of the processor and reduced system availability.

In addition, the embedded processor is oriented to complex and various application scenarios, so that the difference of design index requirements (functional performance, reliability, cost and power consumption) is very large, so that it is difficult to have one set of scheme to meet all system requirements in reality, and therefore, the requirement of realizing more flexible peripheral expansion based on the established hardware scheme of the processor always exists.

Disclosure of Invention

The invention aims to: the invention aims to provide a control system and a realization method for controlling a low-speed peripheral by a single instruction set soft core, which realize the peripheral operation of a soft core controller through a programmable logic device, and directly access an operation result without waiting for the peripheral response by a processor.

The technical scheme is as follows: the control system comprises a processor, a field programmable logic device and a plurality of low-speed peripherals; the processor is communicated with the field programmable logic device through a high-speed bus, the field programmable logic device is responsible for operating low-speed peripherals, and the processor is not directly connected with the peripherals.

Furthermore, the field programmable logic device is a soft core controller and comprises a scheduling controller, an instruction memory, a result memory and an external interface; the scheduling controller obtains the current operation instruction from the instruction memory, transmits the current operation instruction to the peripheral interface to implement peripheral operation, and stores an operation result fed back by the peripheral interface into the result memory.

Further, when the system comprises a plurality of peripherals, the number of the peripheral interfaces is determined by the number of the peripherals; each peripheral interface corresponds to a peripheral one by one.

The control system realizing method of the invention comprises the following steps:

s110, in an initialization stage, a CPU configures the content of an instruction memory;

s120, in the operation stage, the scheduling controller acquires a current operation instruction from the instruction memory and transmits the current operation instruction to the peripheral interface;

s130, the peripheral interface finishes the instruction execution and feeds back the execution result; any peripheral interface can only execute the command of matching the target peripheral serial number with the peripheral interface serial number in the command;

s140, the scheduling controller stores the operation result into a result memory;

s150, the CPU accesses the result memory and acquires the operation result.

Furthermore, the content of the instruction memory is written in by the processor in the initialization stage, and the content in the instruction memory is not changed any more after the system enters the operation stage.

Further, in step S110, the format and the length of each operation instruction in the instruction memory are fixed, and the operation instruction includes the following fields: target peripheral serial number, operation type, operation length, operation address, operation code, result address, interrupt mark and end mark.

Further, in step S120, the scheduling controller sequentially fetches instructions in order for execution, and when the instruction execution with the valid end flag is completed, which indicates that all instructions in the loop have been executed, the scheduling controller will fetch instructions from the head of the instruction memory again and start a new loop;

any peripheral interface can only execute the command of matching the target peripheral serial number with the peripheral interface serial number in the command.

Further, in step S130, the peripheral interface supports a preset timeout threshold, and when the execution time of the peripheral operation exceeds the threshold and cannot be completed, the peripheral interface interrupts the current operation and feeds back execution timeout failure information to the scheduling controller; when the peripheral operation is finished within the threshold time, the peripheral interface feeds back execution finishing information to the scheduling controller.

Further, in step S140, the scheduling controller receives execution completion information fed back by the peripheral interface, and writes the execution completion information into the result memory according to the result address specified in the instruction; if the current instruction interrupt flag is valid, the scheduling controller initiates an interrupt request to the processor.

Further, in step S150, the CPU accesses the contents in the result memory in response to the interrupt request.

Compared with the prior art, the invention has the following remarkable effects:

1. the processor and the single instruction set are communicated through the high-speed bus, so that the problem of overlong waiting time when the high-performance processor operates low-speed peripherals is solved, and the execution efficiency of the processor is improved;

2. the FPGA-based soft core controller only supports an instruction set with a single format, and effectively limits the complexity of a soft core and the required FPGA logic resource, thereby taking the system performance and the economy into consideration;

3. the field programmable property of the FPGA device can realize the customization of the types and the quantity of the peripheral interfaces according to the requirements, so that the embedded system can support richer application scenes.

Drawings

FIG. 1 is a schematic diagram of the system architecture of the present invention;

FIG. 2 is a general flow chart of a method of implementing the present invention;

FIG. 3 is a diagram illustrating an instruction format in an implementation of the present invention;

FIG. 4 is a transition diagram of the operation state of the scheduling controller in the method for implementing the present invention;

fig. 5 is a diagram illustrating a transition of the operating state of the peripheral interface scheduler according to the embodiment of the present invention.

Detailed Description

The invention is described in further detail below with reference to the drawings and the detailed description.

As shown in fig. 1, the control system of the present invention includes a processor (CPU), a field programmable logic device (FPGA) and at least one low-speed peripheral, where the CPU implements control and access functions of each low-speed peripheral through the FPGA. The FPGA realizes that 1 soft core controller is responsible for CPU communication and peripheral control, and a programmable logic device (FPGA) can realize peripheral interfaces of different types and self-defined quantity through hardware description language programming and also supports high-bandwidth communication with a processor through a high-speed communication interface. The soft core controller can be logically divided into 4 modules, which are respectively: the system comprises a scheduling controller, an instruction memory, a result memory and a peripheral interface; the number of the scheduling controller, the instruction memory and the result memory is 1, and the number of the peripheral interfaces is the same as the number of the peripheral controlled by the soft core controller, wherein the number of the peripheral interfaces is the same as the number of the peripheral actually existing in the system.

As shown in fig. 2, the low-speed peripheral method implemented based on the soft core controller includes the following steps:

s1, a CPU configures the content of an instruction memory in an initialization stage;

the format and length of each operation instruction in the instruction memory are fixed, and the content at least comprises the following fields:

a1, target peripheral serial number: designating the serial number of the peripheral equipment which needs to be operated by the instruction, and sequentially coding the serial number, wherein the serial number corresponds to the peripheral equipment one by one;

a2, operation type: the operation type of the instruction is specified and divided into reading and writing;

a3, operating length: specifying a length of the instruction operation, the length being associated with the field length;

a4, operation address: the command needs to access the address information of the peripheral equipment, and the effective value range is determined by the allowed addressing range of the corresponding peripheral equipment;

a5, operation code: the content of the write operation, when the instruction is a read operation, the field does not function;

a6, result address: the reading operation result is stored in the destination address of the result memory, and the effective range of the address is determined by the effective storage depth of the corresponding result memory;

a7, interrupt flag: indicating whether to initiate an interrupt request to the processor after the current operation is finished;

a8, end flag: indicating whether the current instruction is the last instruction in instruction memory.

S2, in the operation stage, the scheduling controller acquires a current operation instruction from the instruction memory, transmits the current operation instruction to the peripheral interface to execute peripheral operation, and stores an operation result fed back by the peripheral interface into a result memory;

and when the instruction execution of the end mark is effective, namely all the instructions in the current cycle are executed, the scheduling controller fetches the instructions from the head of the instruction memory again and starts a new cycle.

The content of the instruction memory is written by the processor in the initialization phase, and the content in the instruction memory is not changed after the system starts to enter the operation phase.

And S3, the CPU accesses the result storage to obtain an operation result.

The soft core controller may have a plurality of peripheral interfaces, and any peripheral interface can only execute the command with the target peripheral serial number matched with the peripheral interface serial number in the command.

The peripheral interface of the soft core controller supports a preset overtime threshold, when the execution time of the peripheral operation exceeds the threshold and still cannot be finished, the peripheral interface interrupts the current operation and feeds back execution overtime failure information to the scheduling controller, and when the peripheral operation finishes the operation within the threshold time, the peripheral interface feeds back execution completion information to the scheduling controller.

As shown in fig. 4, the scheduling controller receives execution completion information fed back by the peripheral interface, writes the execution completion information into the result memory according to the result address specified in the instruction, and if the current instruction interrupt flag is valid, the scheduling controller initiates an interrupt request to the processor, and the processor responds to the interrupt request to access the content in the result memory.

In this embodiment, the embedded system is composed of a CPU processor (TI corporation DSP, C6655), an FPGA (Xilinx corporation XC7a100TFGG 484), and three peripherals: UART (Universal Asynchronous Receiver/Transmitter) Interface, SFP (Small Form plug) optical module of IIC Interface (InterIntegrated Circuit bus) Interface and SRAM (Serial Peripheral Interface) device of SPI Interface (Serial Peripheral Interface). The CPU processor 101 and the FPGA 102 realize a communication function through a PCIE bus (Gen 1 x1,2.5 Gbps), the FPGA is connected to three peripheral devices through corresponding peripheral interfaces, and the peripheral devices are, as shown in fig. 1, a universal serial transceiver 103, an SPF optical module 104, and an SRAM device 105.

In this embodiment, the soft core controller implemented by the FPGA may be divided into 4 modules, which are: 1 scheduling controller 113, 1 instruction memory, 1 result memory 112, and three peripheral interfaces; the peripheral numbers of the three peripheral interfaces are respectively 1,2 and 3. The peripheral interface 1 realizes a UART interface 114 and controls the universal serial transceiver to realize a data transceiving function, and the highest data bandwidth is 115200bps; the external interface 2 realizes an IIC interface 115, reads the real-time information of the SFP optical module, and the data bandwidth is up to 400Kbps; the peripheral interface 3 is a parallel synchronous data bus SPI interface 116, the clock frequency is 40MHz, and the data bit width is 8 bits.

In this embodiment, as shown in fig. 3, the instruction format is as follows:

1) Target peripheral serial number: the word length is 4bit, and the system has 3 peripherals in total, so the effective value range is 0x1,0x2 and 0x3;

2) The operation type is as follows: word length is 2 bits, read as 0x1; write to 0x2;

3) Operation length: the word length is 2 bits, the effective range is 0x 0-0 x3, byte unit;

4) The operation address: the word length is 8 bits, the effective range is 0x 0-0 xff, and addressing is carried out according to bytes;

5) Operation code: the word length is 32 bits, and the effective range is 0x 0-0 xffffffff;

6) Result address: the word length is 12 bits, the effective range is 0x 0-0 xfff, and addressing is carried out according to bytes;

7) An interrupt flag: the word length is 1bit;0x0 indicates that no interrupt signal needs to be sent to the CPU after the present instruction is executed, and 0x1 indicates that no interrupt signal needs to be sent to the CPU after the present instruction is executed.

8) End mark: a word size of 1bit,0x0 indicates that the present instruction is not the last 1 instruction, and 0x1 indicates that the present instruction is the last 1 instruction.

In this embodiment, as shown in fig. 5, according to the parameters of the peripheral chip and the specific hardware circuit, the timeout time of the peripheral interface 1 is set to 2ms, the timeout time of the peripheral interface 2 is set to 15ms, and the timeout time of the peripheral interface 3 is set to 1ms. When the operation of the peripheral interface is not normally completed when the corresponding peripheral exceeds the overtime threshold, the peripheral interface returns overtime failure information to the scheduling module; and when the operation of the peripheral interface is normally finished within the overtime time threshold corresponding to the peripheral, the peripheral interface returns operation finishing information to the scheduling module.

In this embodiment, an end flag and an interrupt flag are set in the last 1 effective instruction, and when the scheduling module completes execution of the instruction, an interrupt request is sent to the CPU, and the CPU reads effective contents of the entire instruction memory through the PCIE high-speed bus.

The above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims (10)

1. A control system for controlling low-speed peripheral equipment by a single instruction set soft core is characterized in that: the system comprises a processor, a field programmable logic device and a plurality of low-speed peripherals; the processor is communicated with the field programmable logic device through a high-speed bus, the field programmable logic device is responsible for operating low-speed peripherals, and the processor is not directly connected with the peripherals.

2. The single instruction set soft core control system for low speed peripherals of claim 1, wherein the field programmable logic device is a soft core controller comprising a scheduling controller, an instruction memory, a result memory, and a peripheral interface; the scheduling controller obtains the current operation instruction from the instruction memory, transmits the current operation instruction to the peripheral interface to implement peripheral operation, and stores an operation result fed back by the peripheral interface into the result memory.

3. The control system of claim 2, wherein when a plurality of peripherals are included in the system, the number of peripheral interfaces is determined by the number of peripherals; each peripheral interface corresponds to a peripheral one by one.

4. A method for realizing the control of low-speed peripheral equipment by a single instruction set soft core is characterized by comprising the following steps:

s110, in an initialization stage, a CPU configures the content of an instruction memory;

s120, in the operation stage, the scheduling controller acquires a current operation instruction from the instruction memory and transmits the current operation instruction to the peripheral interface;

s130, the peripheral interface finishes the instruction execution and feeds back the execution result; any peripheral interface can only execute the command of matching the target peripheral serial number with the peripheral interface serial number in the command;

s140, the scheduling controller stores the operation result into a result memory;

s150, the CPU accesses the result memory to obtain the operation result.

5. The method as claimed in claim 4, wherein the contents of the instruction memory are written by the processor during an initialization phase, and the contents of the instruction memory are not changed after the system enters a run phase.

6. The method as claimed in claim 4, wherein in step S110, the format and length of each operation instruction in the instruction memory are fixed, and the operation instruction includes the following fields: the system comprises a target peripheral serial number, an operation type, an operation length, an operation address, an operation code, a result address, an interrupt mark and an end mark.

7. The method as claimed in claim 4, wherein in step S120, the scheduling controller fetches the instructions in sequence for execution, and when the instruction with the valid ending flag is completed, indicating that all the instructions in the current cycle have been completed, the scheduling controller fetches the instructions from the head of the instruction memory again to start a new cycle;

any peripheral interface can only execute the command of matching the target peripheral serial number with the peripheral interface serial number in the command.

8. The method for implementing the single instruction set soft core controlling the low-speed peripheral according to claim 4, wherein in step S130, the peripheral interface supports a preset timeout threshold, and when the execution time of the current peripheral operation exceeds the threshold and cannot be completed, the peripheral interface interrupts the current operation and feeds back execution timeout failure information to the scheduling controller; when the peripheral operation is finished within the threshold time, the peripheral interface feeds back execution finishing information to the scheduling controller.

9. The method as claimed in claim 4, wherein in step S140, the scheduling controller receives the execution completion information fed back by the peripheral interface, and writes the execution completion information into the result memory according to the result address specified in the instruction; and if the current instruction interrupt flag is valid, the scheduling controller initiates an interrupt request to the processor.

10. The method as claimed in claim 9, wherein the CPU accesses the contents of the result memory in response to the interrupt request in step S150.

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