CN115580118A - Drive circuit for high-efficiency Buck converter - Google Patents
Drive circuit for high-efficiency Buck converter Download PDFInfo
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- CN115580118A CN115580118A CN202211149632.5A CN202211149632A CN115580118A CN 115580118 A CN115580118 A CN 115580118A CN 202211149632 A CN202211149632 A CN 202211149632A CN 115580118 A CN115580118 A CN 115580118A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Inverter Devices (AREA)
- Dc-Dc Converters (AREA)
Abstract
The application discloses drive circuit for high efficiency Buck converter includes: a through protection circuit, a high-side circuit and a low-side circuit; the direct connection protection circuit is respectively connected with the high-side circuit and the low-side circuit; the direct-current protection circuit is used for preventing the circuit from being damaged; the high-side circuit is used for receiving the PWM signal transmitted by the direct connection protection circuit and generating dynamic dead time from a high side to a low side; the low-side circuit is used for receiving the PWM signal transmitted by the through protection circuit and generating the dead time from the low side to the high side. According to the method, the application scene of a wide input voltage range is combined, the charging and discharging time of the capacitor of the SW node is changed by using the inductor current, so that the dynamic adjustment of dead time under different load current conditions is realized, the DC-DC reliability is ensured, the power loss is reduced, and the efficiency is improved; meanwhile, a narrow pulse generating circuit part is omitted, so that the aims of further reducing static power consumption and improving system efficiency are fulfilled.
Description
Technical Field
The application relates to the field of driving circuits, in particular to a driving circuit for a high-efficiency Buck converter.
Background
The DC-DC converter is widely used in power electronic devices due to its characteristics of high efficiency, strong on-load capability, and the like. In order to improve the efficiency and reliability of the converter, the technology of the dead time optimization adjustment and the narrow pulse transmission is greatly developed. However, the fixed dead time cannot be adapted to various applications, that is, only the converter can be ensured not to have the MOS transistor pass-through phenomenon of the high side and the low side.
And the prior art attempts to solve the above problems include: whether the dead time at the stage is proper or not is judged by detecting whether the drain voltage of the low-side NMOS tube is zero or not, and a corresponding control signal is generated by a comparison circuit and is output to a logic circuit. Aiming at the dead time control technology of the Miller platform, the Miller platform in the switching process of the MOS tube is used as a detection point for judging whether the dead time is appropriate or not. And monitoring the size of the dead time in real time by utilizing a PFGA digital control mode, and correcting the dead time in real time according to the size of the load current so as to achieve the optimal dead time. The self-zeroing switched capacitor comparator is used for improving the detection precision of the switch node voltage LX, and further the optimized dead time is realized. Neither of these techniques then enables dynamic adjustment of the dead time under different load current conditions.
Disclosure of Invention
The driving circuit disclosed by the application combines the application scene of wide input voltage range, can realize the dynamic adjustment of dead time under different load current conditions, and simultaneously carries out optimization processing on the narrow pulse signal generation mode so as to achieve the purpose of improving the system efficiency.
To achieve the above object, the present application provides a driving circuit for a high efficiency Buck converter, comprising: a through protection circuit, a high side circuit and a low side circuit;
the through protection circuit is respectively connected with the high-side circuit and the low-side circuit;
the direct-current protection circuit is used for preventing the circuit from being damaged;
the high-side circuit is used for receiving the PWM signal transmitted by the direct-current protection circuit and generating dynamic dead time from a high side to a low side;
the low-side circuit is used for receiving the PWM signal transmitted by the direct-current protection circuit and generating dead time from low side to high side.
Preferably, the pass-through protection circuit is composed of a nand gate and a nor gate, and the work flow includes: the high-side MOS tube and the low-side MOS tube are prevented from being simultaneously turned on to transmit large current, and further the circuit is prevented from being damaged.
Preferably, the high-side circuit includes: the circuit comprises a narrow pulse generating circuit, a narrow pulse transmission circuit, a first level shift circuit, a PWM signal recovery circuit, a first output driving circuit and an adaptive dead time circuit.
Preferably, the adaptive dead time circuit includes: the current sampling circuit, the charging path and the discharging path are formed;
the current sampling circuit is used for collecting sampling current signals.
Preferably, the work flow of the high-side circuit comprises: after receiving the PWM signal, generating a narrow pulse signal through a narrow pulse generating circuit; then the high-efficiency transmission of the PWM signals and the conversion from a low voltage domain to a high voltage domain are realized through the narrow pulse transmission circuit, the first level shift circuit and the PWM signal recovery circuit; then, amplifying the driving signal through the first output driving circuit to generate a high-side driving signal so as to drive a high-side PMOS power tube with a larger rear-stage size; and finally, the self-adaptive dead time circuit simultaneously collects the high-side driving signal and the sampling current signal to generate the dynamic dead time.
Preferably, the work workflow of the narrow pulse generating circuit includes: and generating the narrow pulse signal at the rising edge and the falling edge through the NAND gate respectively by utilizing the time difference between the driving signal subjected to logic transmission and short delay of dead time and the PWM signal.
Preferably, the low-side circuit includes: the circuit comprises a second level shift circuit, a delay matching circuit, a second output driving circuit and a fixed dead time circuit.
Preferably, the work flow of the low-side circuit comprises: after receiving the PWM signal, firstly, the second level shift circuit carries out power supply and ground conversion, and the driving circuit is prevented from generating interference on a logic circuit of a front stage; then, the time sequence matching with the high-side circuit is realized by utilizing the time delay matching circuit; then, amplifying the driving signal through the second output driving circuit to generate a low-side driving signal so as to drive a low-side NMOS power tube with a larger rear-stage size; and finally, the fixed dead time circuit collects the low-side driving signal to generate the dead time.
Compared with the prior art, the beneficial effects of this application are as follows:
according to the method and the device, on the basis of the dynamic dead time, the application scene of a wide input voltage range is combined, the charging and discharging time of the capacitor of the SW node is changed by using the inductor current, the dynamic adjustment of the dead time under the condition of different load currents is further realized, the DC-DC reliability is ensured, and meanwhile, the power loss and the efficiency are reduced. Compared with the RC charging mode of the traditional narrow pulse circuit, the method has the advantages that the narrow pulse is generated by performing logic operation on the PWM signal and the delayed driving signal PWM _ T, and a narrow pulse generating circuit part is omitted, so that the aims of further reducing static power consumption and improving system efficiency are fulfilled.
Drawings
In order to more clearly illustrate the technical solution of the present application, the drawings needed to be used in the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for a person skilled in the art to obtain other drawings without any inventive exercise.
FIG. 1 is a schematic diagram of a system configuration according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a fixed dead time circuit configuration according to an embodiment of the application;
FIG. 3 is a schematic diagram of a narrow pulse signal according to an embodiment of the present application;
FIG. 4 is a schematic diagram of an adaptive dead-time circuit according to an embodiment of the present application;
fig. 5 is a schematic diagram of a narrow pulse generating circuit according to an embodiment of the present application.
Description of reference numerals: 1. a pass-through protection circuit; 2. a narrow pulse generating circuit; 3. a narrow pulse transmission circuit; 4. a first level shift circuit; 5. a PWM signal recovery circuit; 6. a first output driver circuit; 7. an adaptive dead time circuit; 8. a second level shift circuit; 9. a delay matching circuit; 10. a second output driving circuit; 11. a fixed dead time circuit.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, the present application is described in further detail with reference to the accompanying drawings and the detailed description.
Fig. 1 is a schematic structural diagram of a system according to an embodiment of the present application, including: a through protection circuit 1, a high side circuit HS and a low side circuit LS. The direct connection protection circuit is composed of a NAND gate and an OR gate, and aims to prevent MOS (metal oxide semiconductor) tubes on high and low sides from being turned on simultaneously to transmit large current and further damage the circuit.
The high-side circuit HS is composed of a narrow pulse generating circuit 2, a narrow pulse transmission circuit 3, a first level shift circuit 4, a PWM signal recovery circuit 5, a first output driving circuit 6 and an adaptive dead time circuit 7; and the low side circuit LS is composed of a second level shift circuit 8, a delay matching circuit 9, a second output drive circuit 10, and a fixed dead time circuit 11.
After receiving the PWM signal, the high-side circuit HS first generates a narrow pulse signal by the narrow pulse generating circuit 2; then the high-efficiency transmission of the PWM signals and the conversion from a low-voltage domain to a high-voltage domain are realized through the narrow pulse transmission circuit 3, the first level shift circuit 4 and the PWM signal recovery circuit 5; then, the driving signal is amplified through the first output driving circuit 6 to generate a high-side driving signal, and then a high-side PMOS power tube with a larger size at the rear stage is driven; finally, the adaptive dead time circuit 7 collects the high-side driving signal and the sampling current signal at the same time to generate dynamic dead time.
After receiving the PWM signal, the low side circuit LS first performs power and ground conversion through the second level shift circuit 8, thereby preventing the driving circuit from generating interference to the previous logic circuit; then, the time sequence matching with the high-side circuit is realized by using a delay matching circuit 9; then, amplifying the driving signal by a second output driving circuit 10 to generate a low-side driving signal, and further driving a rear-stage large-size low-side NMOS power tube; finally, the fixed dead time circuit 11 collects the low-side driving signal to generate dead time.
The application aims at the correlation between the switching action of the high-side MOS tube and the low-side MOS tube of the Buck converter and the voltage at the node SW, and finds that the voltage at the node SW is the potential of the input voltage VIN after charging and discharging of the parasitic capacitor CSW, as shown in FIG. 2.
The dead time expression can thus be derived:
in the formula, t dead As dead time, C SW Is parasitic capacitance at SW, I L Is the inductor current. As can be seen from equation (1), the dead time t dead Is positively correlated with the input voltage and negatively correlated with the inductor current. Therefore, the dynamic adjustment of the dead time can be realized according to the magnitude of the input voltage and the change of the inductive current.
In addition, aiming at the problem of increase of area and power consumption caused by the traditional narrow pulse generation mode, the scheme that the PWM signal and the driving signal PWM _ T after logic transmission and dead time delay are subjected to logic operation is provided, and the rising edge narrow pulse and the falling edge narrow pulse corresponding to the PWM signal are respectively generated, as shown in fig. 3, so that the area and the power consumption of a system are further reduced.
The circuit configuration of the adaptive dead time circuit 7 for generating the dynamic dead time is shown in fig. 4 by M 1 ～M 3 Formed charging path, resistor R, M 4 ～M 7 The discharge path and the current sampling circuit are formed, wherein the current sampling circuit is used for collecting an inductive current sampling value I SENSE . PWM _ HS is a high-side PWM signal, I CH Is a capacitor C SW In the present embodiment, M 7 Using high voltage devices for protection of M 4 、M 5 The current mirror is formed.
When PWM _ HS is changed from low level to high level, namely, high-side power tube S 1 Off, M 3 Starting, sampling the current I SENSE By M 1 、M 2 The current mirror is constructed to generate a current I 1 At the same time, the input voltage V IN Pass resistor R, M 5 、M 6 Generating a current I 3 The expression is
In the formula, V od7 Is M 7 Over-drive voltage of V od6 Is M 6 Over-drive voltage of V od5 Is M 5 The overdrive voltage of (d). Then, I 3 Generating a current I by means of a current mirror 2 And I is CH 、I 1 And I 2 The relationship is as follows:
I CH ＝I 1 -I 2 (3)
from the formula (3), the charging current I in this stage CH Is I 1 And I 2 Difference of (d), charging current I CH In the capacitor C SW The generated voltage passes through a back-stage buffer to obtain a PWM _ T signal, and then the PWM _ T signal is input into a low-side driving circuit LS to open a low-side follow current tube S 2 . The PWM _ T signal is a signal obtained by delaying PWM _ HS by a dead time, and is affected by the input voltage and the load current.
In the above process, when the load current increases, the inductor current increases, and the sampling current I is then increased SENSE Increase of current I 1 The charging time is reduced along with the increase of the charging time, namely the dead time is reduced; when the input voltage V IN When increasing, flows through M 5 Current of (I) 3 With a consequent increase in 1 The current I drawn 2 The capacitance C is increased as shown by the formula (2) SW Charging current I CH Decreasing, the resulting dead time increases. Thus, the inductor current I L And an input voltage V IN And the dynamic adjustment of the dead time of the Buck converter can be realized by introducing the Buck converter at the same time.
When the low-side tube is turned off, the dead time for turning on the high-side tube is generated by a fixed dead time circuit, as shown in fig. 2, so that the high-side tube and the low-side tube are prevented from being directly connected.
The circuit structure of the narrow pulse generating circuit 2 is shown in fig. 5, and the narrow pulse generating circuit mainly comprises a PWM signal, a driving signal PWM _ T subjected to logic transmission and dead time delay, and a logic gate circuit. The principle is that a time difference exists between a driving signal PWM _ T and a PWM signal after logic transmission and short dead time delay, and narrow pulse signals are generated on rising edges and falling edges through a NAND gate by utilizing the time difference of the driving signal PWM _ T and the PWM signal.
The above-described embodiments are merely illustrative of the preferred embodiments of the present application, and do not limit the scope of the present application, and various modifications and improvements made to the technical solutions of the present application by those skilled in the art without departing from the spirit of the present application should fall within the protection scope defined by the claims of the present application.
Claims (8)
1. A drive circuit for a high efficiency Buck converter, comprising: a through protection circuit, a high-side circuit and a low-side circuit;
the through protection circuit is respectively connected with the high-side circuit and the low-side circuit;
the direct-current protection circuit is used for preventing the circuit from being damaged;
the high-side circuit is used for receiving the PWM signal transmitted by the direct-connection protection circuit and generating dynamic dead time from a high side to a low side;
the low-side circuit is used for receiving the PWM signal transmitted by the direct-current protection circuit and generating dead time from a low side to a high side.
2. The driving circuit for a high efficiency Buck converter according to claim 1, wherein the shoot-through protection circuit is formed by a nand gate and a nor gate, and the work flow includes: the high-side MOS tube and the low-side MOS tube are prevented from being simultaneously turned on to transmit large current, and further the circuit is prevented from being damaged.
3. The driving circuit for a high efficiency Buck converter according to claim 2, wherein the high side circuit includes: the circuit comprises a narrow pulse generating circuit, a narrow pulse transmission circuit, a first level shift circuit, a PWM signal recovery circuit, a first output driving circuit and an adaptive dead time circuit.
4. The driving circuit for a high efficiency Buck converter according to claim 3, wherein the adaptive dead-time circuit includes: the current sampling circuit, the charging path and the discharging path are formed;
the current sampling circuit is used for collecting sampling current signals.
5. The driving circuit for a high-efficiency Buck converter according to claim 4, wherein the work flow of the high-side circuit comprises: after receiving the PWM signal, generating a narrow pulse signal through a narrow pulse generating circuit; then the high-efficiency transmission of the PWM signals and the conversion from a low voltage domain to a high voltage domain are realized through the narrow pulse transmission circuit, the first level shift circuit and the PWM signal recovery circuit; then, amplifying the driving signal through the first output driving circuit to generate a high-side driving signal so as to drive a high-side PMOS power tube with a larger rear-stage size; and finally, the self-adaptive dead time circuit simultaneously collects the high-side driving signal and the sampling current signal to generate the dynamic dead time.
6. The driving circuit for a high-efficiency Buck converter according to claim 5, wherein a work flow of said narrow pulse generating circuit comprises: and generating the narrow pulse signal at the rising edge and the falling edge through the NAND gate respectively by utilizing the time difference between the driving signal subjected to logic transmission and short delay of dead time and the PWM signal.
7. The driving circuit for a high efficiency Buck converter according to claim 1, wherein the low side circuit includes: the circuit comprises a second level shift circuit, a delay matching circuit, a second output driving circuit and a fixed dead time circuit.
8. The driving circuit for a high efficiency Buck converter according to claim 7, wherein the workflow of the low side circuit includes: after receiving the PWM signal, firstly, the second level shift circuit carries out power supply and ground conversion, and the driving circuit is prevented from generating interference on a logic circuit of a front stage; then, the time sequence matching with the high-side circuit is realized by utilizing the time delay matching circuit; then, amplifying the driving signal through the second output driving circuit to generate a low-side driving signal so as to drive a low-side NMOS power tube with a larger rear stage size; and finally, the fixed dead time circuit collects the low-side driving signal to generate the dead time.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211149632.5A CN115580118B (en) | 2022-09-21 | 2022-09-21 | Driving circuit for high-efficiency Buck converter |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211149632.5A CN115580118B (en) | 2022-09-21 | 2022-09-21 | Driving circuit for high-efficiency Buck converter |
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| CN115580118B CN115580118B (en) | 2023-11-10 |
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-
2022
- 2022-09-21 CN CN202211149632.5A patent/CN115580118B/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101944845A (en) * | 2010-08-06 | 2011-01-12 | 东南大学 | Switch-level circuit with adaptive control of dead time |
| CN102170228A (en) * | 2011-04-29 | 2011-08-31 | 电子科技大学 | A dead time control circuit used in a DC-DC converter |
| CN102904220A (en) * | 2012-11-07 | 2013-01-30 | 东南大学 | Under-voltage protection method of high-voltage half-bridge driving chip and high-voltage half-bridge circuit |
| US20170187284A1 (en) * | 2015-12-23 | 2017-06-29 | Intel Corporation | Digitally controlled zero voltage switching |
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