CN115579287B - Manufacturing method and structure of bidirectional TVS device - Google Patents

Manufacturing method and structure of bidirectional TVS device Download PDF

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CN115579287B
CN115579287B CN202211568974.0A CN202211568974A CN115579287B CN 115579287 B CN115579287 B CN 115579287B CN 202211568974 A CN202211568974 A CN 202211568974A CN 115579287 B CN115579287 B CN 115579287B
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CN115579287A (en
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杨国江
于世珩
毛嘉云
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Jiangsu Changjing Technology Co ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
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    • H01ELECTRIC ELEMENTS
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01ELECTRIC ELEMENTS
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
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    • H01L29/8613Mesa PN junction diodes

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Abstract

The invention discloses a manufacturing method and a structure of a bidirectional TVS device, wherein the method comprises the following steps: firstly, carrying out first infinite source injection and a first push junction on an isolation window on an N-type substrate, forming a P + type region after the front surface and the back surface of the N-type substrate are diffused and then intersecting, forming a PN junction structure with reverse bias between the P + type region and the N-type substrate, then carrying out second infinite source injection and a second push junction on the first surface and the second surface of the N-type substrate, forming a P-type main junction region in the N-type substrate, forming a PN junction structure with forward bias between the P-type main junction region and the N-type substrate, then forming a passivation layer and a metal layer through mesa etching, deposition, etching and electroplating, and finally, translating a preset distance from the intersection line of the interface of the P + type region and the N-type substrate and the arc concave surface to the alignment metal layer for cutting to obtain the bidirectional TVS device.

Description

Manufacturing method and structure of bidirectional TVS device
Technical Field
The invention relates to the field of semiconductors, in particular to a manufacturing method and a structure of a bidirectional TVS device.
Background
The Transient diode (TVS) is a diode-type high-efficiency protection device, has short response time and strong surge absorption capability, and is often used in combination with components such as resistors and capacitors to perform Transient high-Voltage suppression protection. The TVS is connected in parallel with the front end of the protected circuit, and is in a high impedance state in a normal state, when large-amplitude transient interference voltage or pulse current appears in the circuit, the TVS is rapidly switched into a reverse conduction state in a very short time to clamp the voltage below the maximum clamping voltage, and when the surge disappears, the TVS is restored to the previous high impedance state to play a role in protecting other components. However, the current TVS manufacturing process has the problems of complex process and high cost, and the high-voltage bidirectional design may cause the risk of glue overflow and short circuit during packaging.
Disclosure of Invention
In view of this, the present invention provides a method and a structure for manufacturing a bidirectional TVS device, so as to solve the problems of complex process and high cost in the related art, and design all the main regions of the TVS of the conventional bidirectional structure to the front.
In order to achieve the purpose, the invention mainly adopts the following technical scheme:
the embodiment of the application provides a manufacturing method of a bidirectional TVS device, which comprises the following steps: s1, providing an N-type substrate, wherein the N-type substrate is provided with a first surface and a second surface which are opposite to each other, and a first oxidation layer is formed on the first surface and the second surface; s2, forming an injection window in the first oxide layer in an isolation mode, carrying out first infinite source injection from the injection window, carrying out first knot pushing under a diffusion condition to obtain a P + type region, and isolating the N type substrate; s3, removing the first oxide layer, and sequentially performing second infinite source injection and second junction pushing from the first surface and the second surface under a mask to form a P-type main junction region in the N-type substrate; s4, forming a second oxide layer and a light resistance layer on the first surface and the second surface in sequence respectively through deposition and etching; s5, forming an arc concave surface through mesa etching so as to expose the undoped part of the N-type substrate and expose a PN junction at the arc concave surface; s6, removing the second oxide layer and the photoresist layer, depositing, etching under a mask, and covering the areas close to the two ends of the first surface, the side face of the P-type main junction, the shared area of the N-type substrate and the arc concave surface, and the partial area of the surface of the P + type region to form a passivation layer; s7, through electroplating, a top metal layer is formed next to the passivation layer and covers a part of the first surface, an alignment metal layer is formed next to the passivation layer and covers a part of the upper surface of the P + type region, and a bottom metal layer is formed covering the second surface; s8, translating a preset distance from the intersection line of the interface of the P + type area and the N-type substrate and the arc-shaped concave surface to the position of the alignment metal layer to determine the cutting surface, and cutting along the cutting surface to obtain the bidirectional TVS device.
Preferably, in the step S1, the resistivity of the N-type substrate is 50 to 85 Ω · cm, and the thickness of the first oxide layer is greater than 2.5 μm.
Preferably, in step S2, the width of the implantation window is greater than 50 μm.
Preferably, in step S2, the concentration of the first infinite source implant is 1 × 10 20 cm -3 (ii) a And/or the depth of the first infinite source injection is 15 to 20 mu m.
Preferably, in step S2, the atmosphere of the first knot is H 2 、O 2 、N 2 Or a combination thereof; and/or the temperature range of the first push knot is 1200-1250 ℃; and/or the time of the first knot pushing is 150h.
Preferably, in step S3, the concentration of the second infinite source implant is 1 × 10 19 cm -3 (ii) a And/or the depth of the P-type main junction is 40 to 55 mu m.
Preferably, in step S3, the atmosphere of the second push knot is H 2 、O 2 、N 2 Or a combination thereof; and/or the temperature of the second push knot is lower than the temperature of the first push knot; and/or the second knot pushing time is 20h.
Preferably, in step S5, the mesa etching refers to etching from the junction between two sides of the photoresist layer and the second oxide layer to two sides of the N-type substrate along an arc-shaped surface, where the arc-shaped surface refers to an arc-shaped cross section penetrating through the photoresist layer, the second oxide layer, the P-type main junction, and the P + junction.
Preferably, in step S5, the mesa etching depth is greater than 120 μm.
An embodiment of the present application provides a bidirectional TVS device, which includes in its cross-sectional structure: an N-type substrate having opposing first and second surfaces; the N-type undoped region is formed in the middle region of the N-type substrate, and the side face of the N-type undoped region is a double-arc-shaped curved surface; a first P-type main junction region formed within the N-type substrate proximate the first surface; a second P-type main junction region formed in the N-type substrate adjacent to the second surface, the first P-type main junction region and the second P-type main junction region both penetrating through the N-type substrate along a horizontal direction; the P + type regions are formed at two ends of the N-type substrate, one side face of each P + type region is coplanar with the N-type undoped region, and the P + type regions are interacted with the second P-type main junction regions at two ends close to the second surface; one side surface of the first P-type main junction and partial areas of the double-arc-shaped side surfaces of the N-type undoped region are sequentially connected to form an arc-shaped concave surface; the passivation layer covers the areas, close to the two ends, of the first P-type main junction, the arc-shaped concave surface and part of the upper surface of the P + type region; a top metal layer disposed proximate to the passivation layer covering a portion of the first P-type main junction upper surface; and the bottom metal layer is arranged to cover the second surface.
Compared with the prior art, the invention has the beneficial effects that: the bidirectional TVS device provided by the embodiment of the application has the advantages that the contact area of the bottom is large, the main function is in the front area structure, and the contact heat dissipation area is large.
Drawings
Fig. 1 is a schematic flow chart illustrating a method for manufacturing a bidirectional TVS device according to an embodiment of the present invention.
Fig. 2 a-fig. 2l are schematic structural diagrams of a bidirectional TVS device manufacturing method according to an embodiment of the present invention;
fig. 2m is a schematic structural diagram of a bidirectional TVS device according to an embodiment of the present invention.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
The invention provides a manufacturing method of a bidirectional TVS device, as shown in FIG. 1, the method comprises the following steps:
step S1: providing an N-type substrate, wherein the N-type substrate is provided with a first surface and a second surface which are opposite, and a first oxidation layer and an injection window are formed on the first surface and the second surface.
Fig. 2a to fig. 2l are schematic structural diagrams in the manufacturing process of a bidirectional TVS device according to an embodiment of the present application, and referring to fig. 2a first, step S1 is completed through the following steps:
step S11: an N-type substrate 100 is provided, the N-type substrate 100 having a first surface S1 and a second surface S2 opposite to each other. The substrate is a silicon substrate, an N-type substrate is formed through ion implantation, the resistivity of the N-type substrate is 50 to 85 omega cm so as to meet the high-voltage requirement of the bidirectional TVS device, and the thickness of the N-type substrate is 200 micrometers.
Step S12: depositing an oxide layer on the first surface and the second surface respectively. Referring to fig. 2b, an oxide layer 110 is deposited on the first surface S1 and the second surface S2, respectively, where the thickness of the oxide layer 110 is greater than 2.5 μm.
Step S13: an initial mask is covered over the oxide layer. With continued reference to fig. 2b, an initial mask 120 is covered on the oxide layer 110 formed on the first surface S1 and the second surface S2 of the N-type substrate 100, respectively.
Step S14: and etching the oxide layer through an initial mask to form a first oxide layer, and forming an injection window on the N-type substrate. Referring to fig. 2c, the oxide layer 110 is etched through the initial mask 120 to obtain a first oxide layer 110a, and four implantation windows 111 are respectively formed at two ends of the first surface S1 and the second surface S2 of the N-type substrate 110.
Step S2: and carrying out first infinite source injection from the injection window, carrying out first knot pushing under a diffusion condition to obtain a P + type region, and isolating the N type substrate. Step S2 is completed by the following steps:
step S21: a first infinite source implant is performed from the implant window. Referring to fig. 2d, a first implantation of an infinite source is performed from four implantation windows 111 to the N-type substrate 100 to form 4P + type doped regions 131, wherein the implantation concentration of the first implantation of the infinite source is greater than 1E20cm -3 The implantation depth is 15 μm to 20 μm. The N-type substrate further includes left and right opposite first and second sides P1 and P2.
Step S22: and carrying out first junction pushing under a diffusion condition to obtain a P + type region, and isolating the N type substrate. Referring to fig. 2e, the first junction is performed under diffusion conditions, and the P + type doped regions are diffused at the front and back sides of the N-type substrate 100 at the same time, so that 2P + type doped regions 131 near the same end of the N-type substrate 100 intersect to form a P + type region 132, and the P + type region 132 separates the adjacent N-type substrates 100. The diffusion conditions here are: at 1250 ℃ in H 2 、O 2 、N 2 Or any combination of the above three gases for 150 hours. After the first junction pushing, the four P + type doped regions 131 are diffused to obtain two double-arc P + type regions 132, the first side of the P + type region 132 is coplanar with the first side P1 and the second side P2 of the N-type substrate 100, and the second side of the P + type region 132 is a double-arc intersecting surface 134. Here, during the first junction push-on process, the first oxide layer 110a will generate a thin oxide layer at the four implantation windows 111 to cover the surfaces of the four implantation windows.
After the diffusion process of step S2 is completed, the device surface is cleaned, and then step S3 is performed: and removing the first oxide layer, and sequentially performing second infinite source injection and second junction pushing from the first surface and the second surface to form a P-type main junction in the N-type substrate.
Referring to fig. 2f, the first oxide layer 110a is removed, and a second infinite source implant is sequentially performed from the first surface S1 and the second surface S2, where the implantation concentration of the second infinite source implant is 1E19cm -3 Subsequently, a second push junction is performed again to form the P-type main junction 133, and the diffusion conditions of the second push junction are as follows: the temperature is 1200-1250 ℃, and the temperature is H 2 、O 2 、N 2 Or performing second sintering diffusion in an atmosphere of any combination of the three gases, wherein the diffusion time is 20h, and the diffusion depth is 40 to 55 mu m. Here, the temperature of the second push knot is lower than that of the first push knot to reduce the influence of the second push knot on the first push knot. In the embodiment of the application, a continuous PNP structure is formed through two infinite source implantations, so that two pairs of PN junction structures with opposite bias voltages are formed to form a diode structure with bidirectional conduction.
And S4, sequentially forming a second oxide layer and a light resistance layer on the first surface and the second surface respectively through deposition and etching. Step S4 is completed by the following steps:
step S41: and depositing a second oxide layer and an initial photoresist layer on the first surface and the second surface respectively. Referring to fig. 2g, a second oxide layer 140 and an initial photoresist layer are formed on the first surface S1 and the second surface S2 by deposition.
Step S42: and etching the initial photoresist layer on the first surface by using a mask to form a photoresist layer. Continuing to refer to fig. 2g, a mask is used to etch the initial photoresist layer on the first surface S1 to obtain a photoresist layer 150, where the photoresist layer 150 on the first surface S1 has etched grooves at two ends close to the N-type substrate 100, and the photoresist layer 150 on the second surface S2 completely covers the entire second surface S2.
Step S5: and forming an arc-shaped concave surface through mesa etching so as to expose the undoped part of the N-type substrate and expose the PN junction at the arc-shaped concave surface. The mesa etching refers to etching from the junction between the two sides of the photoresist layer and the first surface, the junction between the two ends facing the N-type substrate along an arc and a cross section parallel to the second surface of the N-type substrate, the arc concave surface penetrates through the photoresist layer, the oxide layer and the P-type main junction, and a cross section parallel to the second surface is formed on the upper surface of the P + region, and the mesa etching can adopt a chemical wet etching method.
Referring to fig. 2h, arc-shaped concave surfaces A1 and A2 are formed by mesa etching, the etching sequentially passes through the second oxide layer 140, the P-type main junction 133 and the N-type substrate 100, and finally stops on the side surfaces P1 and P2 at the two ends of the N-type substrate 100, so as to form the arc-shaped concave surfaces A1 and A2 at the two ends of the N-type substrate 100, and form a cross section S3 parallel to the second surface S2 on the upper surface of the P + -type region 132, where the arc-shaped concave surfaces A1 and A2 and the cross section S3 together form an etching structure. At this time, the P-type main junction 133 and the undoped portion of the N-type substrate 100 are exposed, and the formed 2 reverse bias PN junction structures 161 and two forward bias PN junction structures 162 are exposed at the arc-shaped concave surfaces A1 and A2 and are respectively located at the interface between the P-type main junction 133 and the N-type substrate 100 and the interface between the P + -type region 132 and the N-type substrate 100. Here, the mesa etching depth D1 is greater than 120 μm, i.e., the distance between the cross section S3 and the photoresist layer 150 on the first surface S1 is greater than 120 μm. In the embodiment of the application, a PNP structure is formed in the device through two times of infinite source injection, two pairs of PN junctions with opposite bias voltages are exposed through mesa etching, and forward bias or reverse bias can be realized in the process of conducting the bidirectional TVS.
And S6, removing the second oxidation layer and the light resistance layer, depositing, etching under a mask, and covering the area close to the two ends of the first surface, the side surface of the P-type main area, the common area of the N-type substrate and the arc concave surface and the partial area of the surface of the P + type area to form a passivation layer.
Referring to fig. 2i, after removing the second oxide layer 140 and the photoresist layer 150, an insulating material 170 is deposited on the first surface S1, the second surface S2 and the arc structures A1 and A2, wherein the insulating material 170 is deposited by a Low Pressure Chemical Vapor Deposition (LPCVD), and the insulating material 170 is silicon oxide, nitride, polysilicon, SIPOS, or the like. The insulating material 170 is etched through the second mask, and referring to fig. 2j, the insulating material 170 is etched to obtain a passivation layer 171 and a groove 172 covering regions close to two ends of the first surface S1, a side surface of the P-type main junction, a common region of the N-type substrate 100 and the arc-shaped concave surfaces A1 and A2, and a partial region of the surface of the P-type main junction 133, where the passivation layer 171 is located on the surface of the PN junctions 161 and 162 to protect the PN junction structure. In the embodiment of the application, the main electric field regions in the formed device are positioned at the arc concave surfaces A1 and A2, are formed in the front surface region of the N-type substrate, and the passivation layer is deposited to protect the electric field regions from being stable.
And S7, forming a top metal layer close to the passivation layer and covering a part of the first surface through electroplating, forming an alignment metal layer close to the passivation layer and covering a part of the upper surface of the P + type region, and forming a bottom metal layer covering the second surface.
Referring to fig. 2k, a top metal layer 180a is formed in the groove 172 covering a portion of the first surface S1 next to the passivation layer 171, an alignment metal layer 180b is formed on a portion of the upper surface covering the P + -type region 132 next to the passivation layer 171, and a bottom metal layer 180c is formed on the second surface S2. Here, the top metal layer 180a, the alignment metal layer 180b, and the bottom metal layer 180c are obtained by an Electroless Nickel Gold (ENIG) method. Here, the alignment metal layer 180b functions as a dicing sight, and the alignment metal layer 180b is set to have a width smaller than that of a dicing blade and is removed after dicing. In the embodiment of the application, a continuous PNP structure is formed by two times of infinite source injection, and both the top metal layer and the bottom metal layer formed here can be used as a cathode and an anode, so that the diode can be conducted in two directions.
Step S8: and translating a preset distance from the intersection line of the interface of the P + type area and the N type substrate and the arc-shaped concave surface to the aligned metal layer to determine the cutting surface, and cutting along the cutting surface to obtain the bidirectional TVS device.
Referring to fig. 2l,base:Sub>A planebase:Sub>A-base:Sub>A where an intersection of the N-type concave surface A2 and an interface of the P + type region 132 and the N-type substrate 100 is located is translated to the alignment metal layer 180B bybase:Sub>A preset distance W to obtainbase:Sub>A cutting plane B-B, the cutting is performed with the cutting plane B-B, and the alignment metal layer 180B is removed to obtain the bidirectional TVS device. Here, the predetermined distance W is 60 μm or more. In the embodiment of the application, a continuous PNP structure is formed by two times of infinite source injection, so that two PN junctions with opposite bias voltages are formed, the breakdown voltage is improved, the bidirectional TVS device obtained by cutting can be conducted in two directions, and the main electric field area is stable at the coplanar position of the N-type substrate and the arc-shaped concave surface A2 and protected by the passivation layer.
Referring to fig. 2m, a cross-sectional structure of a bidirectional TVS device 10 includes:
an N-type substrate having opposing first and second surfaces S1 and S2; an N-type undoped region 100 'formed in the middle region of the N-type substrate, wherein the lateral surface of the N-type undoped region 100' is a double-arc curved surface; here, the upper surface of the N-type undoped region 100' is parallel to the first surface S1, the lower surface is parallel to the second surface S2, and both side surfaces are double-arc curved surfaces.
The bidirectional TVS device 10 further includes: a first P-type main junction region 133a formed in the N-type substrate proximate to the first surface S1; a second P-type main junction region 133b formed in the N-type substrate proximate to the second surface S2, the first P-type main junction region 133a and the second P-type main junction region 133b both penetrating the N-type substrate along a horizontal direction; the first and second P-type main regions formed by the second infinite source implant, the lower surface of the first P-type main region 133a is coplanar with the upper surface of the N-type undoped region 100', and thus, a PN junction structure 162 is formed between the first P-type main region 133a and the N-type undoped region 100'.
The bidirectional TVS device 10 further includes: p + type regions 132 formed at both ends of the N-type substrate, a side surface of the P + type region 132 being coplanar with the N-type undoped region 100', the P + type regions 132 being alternated with the second P-type main junction regions 133b at both ends near the second surface S2; here, the P + -type region 132 is formed by a first infinite source implantation, the PN junction structure 161 is formed between the P + -type region 132 and the N-type undoped region 100', and an overlap region is formed near both ends of the second surface S2 at the time of two infinite source implantations.
The bidirectional TVS device 10 further includes: one side surface of the first P-type main junction 133a and a partial region of the double-arc side surface of the N-type undoped region 100' are sequentially connected to form an arc-shaped concave surface A1; here, the arc-shaped concave surface A1 is obtained by mesa etching to expose two PN junction structures.
The bidirectional TVS device 10 further includes: a passivation layer 171 covering the regions of the first P-type main junction 133a near the two ends, the arc-shaped concave surface A1, and a portion of the upper surface of the P + -type region 132; a top metal layer 180a disposed next to the passivation layer 171 and covering a portion of an upper surface of the first P-type main junction region 133a; and a bottom metal layer 180c disposed to cover the second surface S2. Here, the passivation layer protects the main electric field region of the bidirectional TVS device, and a PNP triple-layer structure is formed, so that the TVS can be conducted in both directions, and in the TVS bidirectional conduction process, both the top metal layer and the bottom metal layer can be used as a cathode and an anode.
In summary, by the manufacturing method of the bidirectional TVS device provided by the present invention, the alignment metal layer is removed after cutting, so that the problem of solder overflow during packaging can be effectively solved, and the bottom contact area of the bidirectional TVS device obtained by performing infinite source diffusion using a paper source is large, and has a large contact heat dissipation area; when the P-type diffusion region is formed, the stability of the PN junction can be ensured through a long-time thermal diffusion process; in addition, the PN junction structures formed between the N-type substrate and the P-type main junction region and between the N-type substrate and the P + type region can enable the breakdown voltage to exceed 2000V, a passivation layer is used in the surface region of a main electric field region to protect a device, and the device has stable heat set and junction temperature in application. The bidirectional TVS device manufactured according to the invention can complete the manufacturing process of the bidirectional TVS device by using a paper source and 3 photoetching plates, simplifies the process, obtains the tape-out process of the discrete device with the lowest cost and high quality, and achieves the win-win situation on the chip manufacturing and packaging requirements.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and any person skilled in the art can make various changes, modifications, substitutions and alterations without departing from the principle and spirit of the present invention, and the scope of the present invention is defined by the claims and their equivalents.

Claims (10)

1. A method of fabricating a bidirectional TVS device, said method comprising the steps of:
s1, providing an N-type substrate, wherein the N-type substrate is provided with a first surface and a second surface which are opposite, and a first oxidation layer is formed on the first surface and the second surface;
s2, forming an injection window in the first oxide layer in an isolation mode, carrying out first infinite source injection from the injection window, carrying out first knot pushing under a diffusion condition to obtain a P + type region, and isolating the N type substrate;
s3, removing the first oxidation layer, performing second infinite source injection and second junction pushing from the first surface and the second surface, and forming a P-type main junction region in the N-type substrate;
s4, sequentially forming a second oxidation layer and a light resistance layer on the first surface and the second surface respectively through deposition and etching;
s5, forming an arc-shaped concave surface through mesa etching so as to expose the undoped part of the N-type substrate and expose the PN junction at the arc-shaped concave surface;
s6, removing the second oxide layer and the photoresist layer, depositing, etching under a mask, and covering the areas close to the two ends of the first surface, the side face of the P-type main junction, the shared area of the N-type substrate and the arc concave surface, and the partial area of the surface of the P + type region to form a passivation layer;
s7, through electroplating, a top metal layer is formed next to the passivation layer and covers a part of the first surface, an alignment metal layer is formed next to the passivation layer and covers a part of the upper surface of the P + type region, and a bottom metal layer is formed covering the second surface;
and S8, translating a preset distance from the intersection line of the interface of the P + type area and the N-type substrate and the arc-shaped concave surface to the aligned metal layer to determine a cutting surface, and cutting along the cutting surface to obtain the bidirectional TVS device.
2. The method according to claim 1, wherein in step S1, the resistivity of the N-type substrate is 50-85 Ω -cm, and the thickness of the first oxide layer is greater than 2.5 μm.
3. The method of claim 1, wherein in step S2, the width of the implantation window is greater than 50 μm.
4. The method of claim 1 wherein the first implantation concentration in step S2 is 1 x 10 20 cm -3 (ii) a And/or the injection depth of the first infinite source is 15 to 20 mu m.
5. The method according to claim 1 or 4, wherein in step S2, the atmosphere of the first knot is H 2 、O 2、 N 2 Or a combination thereof; and/or the temperature range of the first push knot is 1200-1250 ℃; and/or the time of the first knot pushing is 150h.
6. The method of claim 1 wherein the second infinite source implant has a concentration of 1 x 10 in step S3 19 cm -3 (ii) a And/or the depth of the P-type main junction is 40 to 55 mu m.
7. The method according to claim 1 or 6, wherein in step S3, the atmosphere of the second knot is H 2 、O 2、 N 2 Or a combination thereof; and/or the temperature of the second push knot is lower than the temperature of the first push knot; and/or the second knot pushing time is 20h.
8. The method according to claim 1, wherein in step S5, the mesa etching is etching from a boundary between two sides of the photoresist layer and the second oxide layer to two sides of the N-type substrate along an arc-shaped surface, and the arc-shaped surface is an arc-shaped cross section passing through the photoresist layer, the second oxide layer, the P-type main junction and the P + -type junction.
9. The method according to claim 1 or 8, wherein in step S5, the mesa etching depth is greater than 120 μ ι η.
10. A bidirectional TVS device, wherein a cross-sectional structure of the bidirectional TVS device includes:
an N-type substrate having opposing first and second surfaces;
the N-type undoped region is formed in the middle region of the N-type substrate, and the side face of the N-type undoped region is a double-arc-shaped curved surface;
a first P-type main junction region formed within the N-type substrate proximate the first surface;
a second P-type main junction region formed in the N-type substrate adjacent to the second surface, the first P-type main junction region and the second P-type main junction region both penetrating through the N-type substrate along a horizontal direction;
the P + type regions are formed at two ends of the N-type substrate, one side face of each P + type region is coplanar with the N-type undoped region, and the P + type regions are interacted with the second P-type main junction regions at two ends close to the second surface;
one side surface of the first P-type main junction and partial areas of the double-arc-shaped side surfaces of the N-type undoped region are sequentially connected to form an arc-shaped concave surface;
the passivation layer covers the areas, close to the two ends, of the first P-type main junction, the arc-shaped concave surface and part of the upper surface of the P + type region;
a top metal layer disposed proximate to the passivation layer covering a portion of the first P-type main junction upper surface;
and the bottom metal layer is arranged to cover the second surface.
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101399201A (en) * 2008-11-13 2009-04-01 杭州杭鑫电子工业有限公司 Method for manufacturing silicon bidirectional trigger diode
CN101916786A (en) * 2010-06-22 2010-12-15 南通明芯微电子有限公司 High-power planar junction bidirectional TVS diode chip and production method thereof
CN102543722A (en) * 2011-12-26 2012-07-04 天津中环半导体股份有限公司 High-voltage transient voltage suppressor chip and production process
CN109390385A (en) * 2017-12-05 2019-02-26 上海长园维安微电子有限公司 A kind of unidirectional TVS device and preparation method thereof with negative resistance charactertistic
CN110233177A (en) * 2019-03-15 2019-09-13 捷捷半导体有限公司 Reverse polarity diodes and preparation method thereof
CN110676310A (en) * 2013-10-17 2020-01-10 意法半导体(图尔)公司 High-voltage vertical power component
CN217405410U (en) * 2022-05-27 2022-09-09 江苏环鑫半导体有限公司 TVS diode surface layer passivation structure

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2969823B1 (en) * 2010-12-23 2013-09-20 St Microelectronics Tours Sas BIDIRECTIONAL SHOCKLEY DIODE TYPE MESA
US20160293592A1 (en) * 2015-03-31 2016-10-06 Vishay General Semiconductor Llc Thin bi-directional transient voltage suppressor (tvs) or zener diode

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101399201A (en) * 2008-11-13 2009-04-01 杭州杭鑫电子工业有限公司 Method for manufacturing silicon bidirectional trigger diode
CN101916786A (en) * 2010-06-22 2010-12-15 南通明芯微电子有限公司 High-power planar junction bidirectional TVS diode chip and production method thereof
CN102543722A (en) * 2011-12-26 2012-07-04 天津中环半导体股份有限公司 High-voltage transient voltage suppressor chip and production process
CN110676310A (en) * 2013-10-17 2020-01-10 意法半导体(图尔)公司 High-voltage vertical power component
CN109390385A (en) * 2017-12-05 2019-02-26 上海长园维安微电子有限公司 A kind of unidirectional TVS device and preparation method thereof with negative resistance charactertistic
CN110233177A (en) * 2019-03-15 2019-09-13 捷捷半导体有限公司 Reverse polarity diodes and preparation method thereof
CN217405410U (en) * 2022-05-27 2022-09-09 江苏环鑫半导体有限公司 TVS diode surface layer passivation structure

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