CN115567034A - Analog filter bandwidth calibration circuit and calibration method - Google Patents

Analog filter bandwidth calibration circuit and calibration method Download PDF

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Publication number
CN115567034A
CN115567034A CN202211310287.9A CN202211310287A CN115567034A CN 115567034 A CN115567034 A CN 115567034A CN 202211310287 A CN202211310287 A CN 202211310287A CN 115567034 A CN115567034 A CN 115567034A
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target
comparator
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不公告发明人
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Chuangyao Suzhou Communication Technology Co ltd
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    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
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    • H03H11/04—Frequency selective two-port networks

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Abstract

The application relates to a bandwidth calibration circuit and a calibration method for an analog filter, in particular to the technical field of bandwidth calibration. The circuit comprises a first band-gap reference current source, a second band-gap reference current source, a target capacitor, n resistance units and n comparators; the first bandgap reference current source is grounded through the first node and the target capacitor in sequence; the first node is connected to the first input end of the n-path comparator; the second band-gap reference current source is grounded through the n resistor units connected in series in sequence; in the n resistor units connected in series, the first end of the kth resistor unit is connected to the second end of the (k-1) th resistor unit; k is more than 1 and less than or equal to n; the first ends of the n resistance units are respectively connected to the second input ends of the n paths of comparators; the output ends of the n-way comparators are connected to the capacitor array of the filter to adjust the capacitance of the filter. Based on the circuit structure, the precision and the speed of the bandwidth calibration of the analog filter are improved.

Description

Analog filter bandwidth calibration circuit and calibration method
Technical Field
The present application relates to the field of bandwidth calibration technologies, and in particular, to a bandwidth calibration circuit and a bandwidth calibration method for an analog filter.
Background
In the chip manufacturing process, due to the process angle difference, values of resistors, capacitors and other devices in chips on different batches of wafers are different, and the bandwidth of the filter is affected, so that the bandwidths of different chips need to be calibrated.
At present, a single comparator is adopted to realize the bandwidth calibration of an analog filter, the scheme obtains the waveform of a comparison period at the output end of the comparator by comparing an input voltage with a reference voltage for many times, and finally obtains a calibration binary code by calculating the time of the comparison period, and the size of a capacitor array of the filter is adjusted by the binary code to calibrate the bandwidth of the filter.
However, existing implementations have a period of inactivity in each comparison cycle, reducing the accuracy of the calibration and requiring multiple comparisons at a slower rate.
Disclosure of Invention
The application provides a bandwidth calibration circuit and a calibration method of an analog filter, which improve the precision and speed of bandwidth calibration of the analog filter.
The analog filter bandwidth calibration circuit comprises a first band-gap reference current source, a second band-gap reference current source, a target capacitor, n resistance units and n comparators;
the first bandgap reference current source is grounded through a first node and the target capacitor in sequence;
the first node is connected to a first input end of the n-path comparator;
the second band-gap reference current source is grounded through the n resistor units which are connected in series in sequence; in the n resistor units connected in series, the first end of the kth resistor unit is connected to the second end of the (k-1) th resistor unit; k is more than 1 and less than or equal to n;
the first ends of the n resistance units are respectively connected to the second input ends of the n paths of comparators;
the output end of the n-path comparator is connected to the capacitor array of the filter so as to adjust the size of the capacitor of the filter.
In one possible implementation, the circuit further comprises a first switch; the first bandgap reference current source is grounded through a first node, a first switch and a target capacitor in sequence;
the first switch is used for controlling the connection or disconnection between the target capacitor and the first bandgap reference current source.
In a possible implementation manner, the first input terminal of the n-way comparator is a non-inverting input terminal, and the second input terminal of the n-way comparator is an inverting input terminal.
In one possible implementation, the first bandgap reference current source and the second bandgap reference current source generate the same current.
In still another aspect, an analog filter bandwidth calibration method is provided, and is applied to an analog filter bandwidth calibration circuit, where the circuit includes a first bandgap reference current source, a second bandgap reference current source, a target capacitor, n resistance units, and n comparators; the first bandgap reference current source is grounded through a first node and the target capacitor in sequence; the first node is connected to a first input end of the n-path comparator; the second band-gap reference current source is grounded through the n resistor units which are connected in series in sequence; in the n resistor units connected in series, the first end of the kth resistor unit is connected to the second end of the (k-1) th resistor unit; k is more than 1 and less than or equal to n; the first ends of the n resistance units are respectively connected to the second input ends of the n paths of comparators; the output end of the n-path comparator is connected to the capacitor array of the filter;
the method comprises the following steps:
acquiring target charging time; the target charging time is the predicted time for charging the target capacitor to a specified voltage;
charging the target capacitor through the first bandgap reference current source according to the target charging time to obtain a target voltage on the target capacitor;
comparing the voltage on the first ends of the n resistance units with the target voltage through the n-path comparators respectively to generate a target binary code;
and adjusting the capacitance of the filter according to the target binary code.
In one possible implementation, the method further includes:
and on the simulation software, the target capacitor is subjected to simulation charging to a specified voltage, and the target charging time is obtained.
In a possible implementation manner, the performing analog charging on the target capacitor to a specified voltage to obtain a target charging time includes:
charging the target capacitor through the first bandgap reference current source to obtain a simulation voltage;
respectively comparing the simulation voltage with n reference voltages through n paths of comparators, and acquiring a simulation binary code at the output end of the n paths of comparators; the n reference voltages are voltages at first ends of the n resistance units when the n resistance units connected in series are powered through a second band-gap reference current source;
and adjusting the charging time and the simulation voltage until the target bit of the simulation binary code is 1, the codes in the simulation binary code higher than the target bit are all 0, the codes in the simulation binary code lower than the target bit are all 1, taking the adjusted simulation voltage as a specified voltage, and taking the adjusted charging time as the target charging time.
In one possible implementation manner, the n-bit codes in the target binary code are respectively generated from the output ends of the n-way comparators;
and the first input end of the n-way comparator is a non-inverting input end, and the second input end of the n-way comparator is an inverting input end.
In a possible implementation manner, for each of the n-way comparators, when the voltage of the non-inverting input terminal of the comparator is greater than the voltage of the inverting input terminal of the comparator, the corresponding code bit of the comparator in the target binary code is 1;
and when the voltage of the non-inverting input end of the comparator is less than the voltage of the inverting input end of the comparator, the code bit corresponding to the comparator in the target binary code is 0.
In a possible implementation manner, the adjusting the capacitance of the filter according to the target binary code includes:
when the binary coding bit corresponding to the output end of the comparator is 1, the filter capacitor corresponding to the output end of the comparator is conducted;
and when the binary coded bit corresponding to the output end of the comparator is 0, the filter capacitor corresponding to the output end of the comparator is disconnected.
The technical scheme provided by the application can comprise the following beneficial effects:
in the analog filter bandwidth calibration circuit shown in the application, the circuit comprises a first band-gap reference current source, a second band-gap reference current source, a target capacitor, n resistance units and n comparators; the first bandgap reference current source is grounded through a first node and the target capacitor in sequence; the first node is connected to the first input end of the n-way comparator; the second band-gap reference current source is grounded through the n resistor units which are connected in series in sequence; in the n resistor units connected in series, the first end of the kth resistor unit is connected to the second end of the (k-1) th resistor unit; k is more than 1 and less than or equal to n; the first ends of the n resistance units are respectively connected to the second input ends of the n paths of comparators; the output end of the n-way comparator is connected to the capacitor array of the filter so as to adjust the capacitance of the filter. When the target capacitance is different from the ideal value, the filter capacitance can be adjusted through the output result of the n-way comparator. Therefore, the circuit structure is simple in structure and improves the precision and speed of bandwidth calibration when the bandwidth calibration function of the analog filter is realized.
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In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings used in the detailed description or the prior art description will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic diagram illustrating an analog filter bandwidth calibration circuit according to an exemplary embodiment.
FIG. 2 is a schematic diagram illustrating an analog filter bandwidth calibration method according to an exemplary embodiment.
Detailed Description
The technical solutions of the present application will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Fig. 1 is a schematic diagram illustrating an analog filter bandwidth calibration circuit according to an exemplary embodiment. The circuit structure can be applied to the analog filter bandwidth calibration scene, and the accuracy and the speed of analog filter bandwidth calibration are improved. As shown in fig. 1, the circuit includes a first bandgap reference current source, a second bandgap reference current source, a target capacitor, n resistance units, and n comparators;
the first bandgap reference current source is grounded through a first node and the target capacitor in sequence;
the first node is connected to the first input end of the n-path comparator;
the second band-gap reference current source is grounded through the n resistor units which are connected in series in sequence; in the n resistor units connected in series, the first end of the kth resistor unit is connected to the second end of the (k-1) th resistor unit; k is more than 1 and less than or equal to n;
the first ends of the n resistance units are respectively connected to the second input ends of the n-path comparators.
The output end of the n-way comparator is connected to the capacitor array of the filter so as to adjust the size of the capacitor of the filter.
In one possible implementation, the circuit further includes a first switch; the first bandgap reference current source is grounded through a first node, a first switch and a target capacitor in sequence; the first switch is used for controlling the connection or disconnection between the target capacitor and the first bandgap reference current source.
In one possible implementation manner, the first input terminal of the n-way comparator is a non-inverting input terminal, and the second input terminal of the n-way comparator is an inverting input terminal.
In one possible implementation, the first bandgap reference current source and the second bandgap reference current source generate the same current.
The operation principle of the analog filter bandwidth calibration circuit shown in fig. 1 is as follows:
in the manufacturing process of the chip, due to the difference of the process angle, the actual performance and the ideal value of the resistor, the capacitor and other devices in the chips on different batches of wafers are different, so that the bandwidth of the analog filter is affected, and therefore, before the analog filter is manufactured by using the chip, the bandwidth of different chips needs to be calibrated.
Firstly, in simulation software, under a typical process corner, a first band-gap reference current source and a target capacitor are switched on, so that the target capacitor is subjected to analog charging to a specified voltage through the first band-gap reference current source, and the time of the analog charging is taken as a target charging time. All devices in the simulation software are in an ideal state, and a target value in the ideal state can be obtained through simulation. The process corner is the range of performance provided to the designer. A bandgap reference current source, i.e. a current source providing a reference current, the first bandgap reference current source may provide a first bandgap reference current i bg . The minimum composition unit of the target capacitor C is the same as that of the capacitor in the filter, so that the size of the capacitor in the filter can be adjusted based on the target capacitor C.
Optionally, a first switch is disposed between the first bandgap reference current source and the target capacitor C, and when the first switch is closed, the first bandgap reference current source and the target capacitor C may be turned on.
Optionally, the effect of turning on or off the first bandgap reference current source and the target capacitor C may also be achieved by other circuit structures.
Optionally, the obtaining the target charging time may include the following steps:
charging a target capacitor through a first band-gap reference current source to obtain a target capacitor upper plate voltage (namely, an artificial voltage) as an n-circuit comparator A 1 ～A n An input voltage of the first input terminal. Simultaneously, n resistor units R connected in series through a second band-gap reference current source pair 1 ～R n Supplying power by using the voltage of the first ends of the n resistance units as a reference voltage V ref,1 ～V ref,n And connected to the second input of the n-way comparator in sequenceAnd (4) an end.
Acquiring the simulation binary code through the output end of the n-path comparator, adjusting the charging time until the target bit of the simulation binary code is 1, wherein the codes in the simulation binary code, which are higher than the target bit, are all 0, the codes in the simulation binary code, which are lower than the target bit, are all 1, and recording the adjusted charging time as the target charging time.
Optionally, when the first input terminal of the n-way comparator is a non-inverting input terminal and the second input terminal of the n-way comparator is an inverting input terminal, the binary coded bit is from the high bit to the low bit of the comparator a 1 To A n Is obtained at the output of (1).
Optionally, the currents generated by the first bandgap reference current source and the second bandgap reference current source are the same. In a practical application scenario, the first bandgap reference current source and the second bandgap reference current source can be adjusted according to requirements.
Optionally, the resistances of the n resistance units may be the same, and the number of the resistances and the connection mode in the n resistance units may also be adjusted according to actual requirements. The minimum component of the resistors in the n resistor units should be the same as the minimum component of the resistors generating the bandgap reference current and the filter resistor in the bandgap reference circuit.
Further, after the target charging time in an ideal state is obtained, a target capacitor is selected in an actual test environment, the target capacitor is charged through the first band-gap reference current source, and the target charging time is kept, so that the upper plate voltage of the charged target capacitor is used as an input voltage (namely, a target voltage) and is connected to the first input end of the n-circuit comparator.
The target capacitor size may deviate from the target capacitor size in the simulation environment, and the minimum constituent unit of the target capacitor is the same as the minimum constituent unit of the filter capacitor, that is, the filter capacitor size also deviates from the filter capacitor size in the simulation environment. Therefore, the filter capacitance needs to be sized.
It should be noted that the TX filter in fig. 1 refers to a transmitter filter, and the RX filter refers to a receiver filter.
Furthermore, the n resistor units connected in series are supplied with power through the second band-gap reference current, the voltage of the first ends of the n resistor units is used as a reference voltage and is sequentially connected to the second input end of the n-path comparator, and the size of the capacitor of the filter is adjusted according to the binary code of the output end of the n-path comparator at the moment.
Optionally, the filter includes a digital logic circuit, the output ends of the n comparators in the test environment may be connected to the digital logic circuit, and the digital logic circuit adjusts the size of the filter capacitor according to the outputs of the n comparators.
Optionally, the filter capacitor may be a capacitor array formed by a plurality of capacitors connected in parallel, each capacitor may correspond to a switching tube, and the switching tube may control the on/off of the capacitor according to an instruction of the digital logic circuit.
In summary, in the analog filter bandwidth calibration circuit shown in the present application, the circuit includes a first bandgap reference current source, a second bandgap reference current source, a target capacitor, n resistor units, and n comparators; the first bandgap reference current source is grounded through a first node and the target capacitor in sequence; the first node is connected to the first input end of the n-path comparator; the second band-gap reference current source is grounded through the n resistor units which are connected in series in sequence; in the n resistor units connected in series, the first end of the kth resistor unit is connected to the second end of the (k-1) th resistor unit; k is more than 1 and less than or equal to n; the first ends of the n resistance units are respectively connected to the second input ends of the n paths of comparators; the output end of the n-way comparator is connected to the capacitor array of the filter so as to adjust the size of the capacitor of the filter. When the target capacitance is different from the ideal value, the filter capacitance can be adjusted through the output result of the n-path comparator. Therefore, the circuit structure is simple in structure and improves the precision and speed of bandwidth calibration when the bandwidth calibration function of the analog filter is realized.
Please refer to fig. 2, which is a diagram illustrating an analog filter bandwidth calibration method according to an exemplary embodiment. The method can be applied to an analog filter bandwidth calibration circuit as shown in fig. 1, and as shown in fig. 2, the method comprises the following steps:
step 201, acquiring target charging time; the target charging time is an expected time to charge the target capacitor to a specified voltage.
Optionally, in the simulation software, the target capacitor C is charged to a specified voltage in a simulation manner, and the target charging time t is obtained.
Optionally, the target capacitor C is charged by the first bandgap reference current source to obtain the simulation voltage V in 。
Further, by n-way comparator A 1 ～A n Respectively comparing the simulated voltages V in And n reference voltages V ref,1 ～V ref,n At n-way comparator A 1 ～A n The output end of the analog binary code acquisition module acquires an analog binary code; the n reference voltages are voltages at first ends of the n resistance units when the n resistance units connected in series are powered through the second band-gap reference current source.
Optionally, when the first input terminal of the n-way comparator is a non-inverting input terminal and the second input terminal of the n-way comparator is an inverting input terminal, the analog binary coded bit is from the high bit to the low bit of the comparator a 1 To A n Is obtained at the output of (a).
Specifically, the first bandgap reference current source generates a first bandgap reference current i bg Can be represented by the following formula:
Figure BDA0003907782600000081
wherein, V bg The band-gap reference voltage is kept constant under different process angles; r bg A resistance in the bandgap reference circuit that generates a bandgap reference current.
Simulated voltage V in From a first bandgap reference current i bg The simulation voltage V is obtained at the charging time t of the upper-level plate of the target capacitor C in Can be represented by the following formula:
Figure BDA0003907782600000091
reference voltage V ref,1 ～V ref,n From a second bandgap reference current i bg When the n resistance units are powered, the voltage on the first ends of the n resistance units is V ref,n For example, it can be represented by the following formula:
Figure BDA0003907782600000092
wherein R is ref,n Is a reference voltage V ref,n Corresponding resistance value of the resistor array, alpha being R ref And R bg The ratio of (a) to (b).
Further, the charging time is adjusted until the target bit of the simulation binary code is 1, the codes higher than the target bit in the simulation binary code are all 0, the codes lower than the target bit are all 1, and the adjusted charging time is used as the target charging time. The filter capacitor size at this moment can be set to be a middle value by the arrangement, so that the binary code can be conveniently adjusted according to the deviation of the target capacitor in a subsequent test environment.
Step 202, charging the target capacitor through the first bandgap reference current source according to the target charging time, and obtaining the target voltage on the target capacitor.
In a test environment, charging the target capacitor for the target charging time, namely controlling variables to enable the charging process of the target capacitor to be the same as that of an ideal target capacitor in simulation software, comparing the voltage generated by the target capacitor and the voltage on the first ends of the n resistor units to generate a binary code, and comparing the difference between the binary code in the test environment and the simulation binary code in an ideal state to adjust the size of the filter capacitor in the test environment.
It should be noted that the analog filter bandwidth calibration circuit shown in fig. 1 corresponds to both the simulation case and the test case, in the simulation case, V in Representing the simulated voltage in the test caseLower, V in Representing the target voltage.
And step 203, comparing the voltages at the first ends of the n resistance units with the target voltage through the n-way comparator respectively, and generating a target binary code.
Alternatively, the number of bits of the binary code can be selected according to actual needs. Under extreme process corners, when all bits of the binary code are 1, it is indicated that the capacitance difference between the target capacitance and the ideal target capacitance may be larger than the adjustable range, so that the number of bits of the binary code high bits, i.e. in the resistor unit R, may be increased 1 The number of the resistor units and the number of the corresponding comparators are increased between the first bandgap reference current source and the second bandgap reference current source; under extreme process corners, when all bits of the binary code are 0, it is indicated that the capacitance difference between the target capacitance and the ideal target capacitance may be smaller than the adjustable range, so that the number of bits of the binary code low bit, i.e. in the resistor unit R, may be increased n The number of the resistor units and the number of the corresponding comparators are increased between the ground terminal and the resistor units.
Optionally, n-bit codes in the target binary code are generated from output ends of the n-way comparators respectively; the first input end of the n-path comparator is a non-inverting input end, and the second input end of the n-path comparator is an inverting input end.
Optionally, for each comparator in the n-way comparators, when the voltage at the non-inverting input terminal of the comparator is greater than the voltage at the inverting input terminal of the comparator, the code bit corresponding to the comparator in the target binary code is 1; when the voltage of the non-inverting input terminal of the comparator is less than the voltage of the inverting input terminal of the comparator, the corresponding code bit of the comparator in the target binary code is 0.
When the first input end of the n-way comparator is the non-inverting input end and the second input end is the inverting input end, namely the target voltage V on the target capacitor in A voltage V connected to the non-inverting input terminal of the comparator and the first terminals of the n resistor units ref,1 ～V ref,n Is connected to the inverting input terminal. At this time, comparator A is used 1 ～A n Corresponding to the target binary code from high order toThe lower order coded bits. Due to the voltage V on the first terminals of the n resistance units ref,1 ～V ref,n Decreasing, using the k-th encoding bit corresponding to the k-th comparator as the target encoding bit, if the k-th encoding bit is 1, then V in ＞V ref,k Coded bit (A) higher than the k-th coded bit 1 ～A k-1 ) Are all 0, lower than the k-th coded bit (A) k+1 ～A n ) The coded bits of (a) are all 1's.
And step 204, adjusting the capacitance of the filter according to the target binary code.
When the binary coding bit corresponding to the output end of the comparator is 1, the filter capacitor corresponding to the output end of the comparator is conducted;
and when the binary coded bit corresponding to the output end of the comparator is 0, the filter capacitor corresponding to the output end of the comparator is disconnected.
Optionally, the filter includes a digital logic circuit, and the binary code at the output end of the n comparators in the test environment can be input into the digital logic circuit, and the digital logic circuit adjusts the size of the filter capacitor according to the binary code.
Optionally, the digital logic circuit may include a digital processing chip, and since one input end of the n-way comparator is theoretically connected to a voltage value obtained by charging through a target charging time under a simulation condition in a test environment, and the other input end is connected to a voltage value generated by a different resistor structure, a binary number formed by output values of the n-way comparator represents an error between an actual value generated by a target capacitor in the filter and a theoretical value in design, so that the digital processing chip may adjust the number of the target capacitors connected to the filter according to the error, calibrate the capacitors in the filter to be close to the theoretical value, and reduce the error of the capacitor of the filter.
Optionally, the filter capacitor may be a capacitor array formed by a plurality of capacitors connected in parallel, each capacitor may correspond to a switching tube, and the switching tube may control the on/off of the capacitor according to an instruction of the digital logic circuit.
When the target capacitance is larger than the ideal target capacitance, the target voltage is smaller than the simulation voltage, the binary code at the moment is smaller than the simulation binary code, and the filter capacitance is reduced after the bandwidth calibration process; when the target capacitance is smaller than the ideal target capacitance, the target voltage is larger than the simulation voltage, the binary code at the moment is larger than the simulation binary code, and the filter capacitance becomes larger after the bandwidth calibration process.
In summary, in the analog filter bandwidth calibration circuit shown in the present application, the circuit includes a first bandgap reference current source, a second bandgap reference current source, a target capacitor, n resistor units, and n comparators; the first bandgap reference current source is grounded through a first node and the target capacitor in sequence; the first node is connected to the first input end of the n-path comparator; the second band-gap reference current source is grounded through the n resistor units which are connected in series in sequence; in the n resistor units connected in series, the first end of the kth resistor unit is connected to the second end of the (k-1) th resistor unit; k is more than 1 and less than or equal to n; the first ends of the n resistance units are respectively connected to the second input ends of the n paths of comparators; the output end of the n-way comparator is connected to the capacitor array of the filter so as to adjust the size of the capacitor of the filter. When the target capacitance is different from the ideal value, the filter capacitance can be adjusted through the output result of the n-path comparator. Therefore, the circuit structure is simple in structure and improves the precision and speed of bandwidth calibration when the bandwidth calibration function of the analog filter is realized.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims (10)

1. The analog filter bandwidth calibration circuit is characterized by comprising a first band-gap reference current source, a second band-gap reference current source, a target capacitor, n resistance units and n comparators;
the first bandgap reference current source is grounded through a first node and the target capacitor in sequence;
the first node is connected to a first input end of the n-path comparator;
the second band-gap reference current source is grounded sequentially through the n resistor units which are connected in series; in the n resistor units connected in series, the first end of the kth resistor unit is connected to the second end of the (k-1) th resistor unit; k is more than 1 and less than or equal to n;
the first ends of the n resistance units are respectively connected to the second input ends of the n paths of comparators;
the output end of the n-path comparator is connected to the capacitor array of the filter so as to adjust the size of the capacitor of the filter.
2. The circuit of claim 1, further comprising a first switch; the first bandgap reference current source is grounded through a first node, a first switch and a target capacitor in sequence;
the first switch is used for controlling the connection or disconnection between the target capacitor and the first bandgap reference current source.
3. The circuit of claim 1, wherein the first input of the n-way comparator is a non-inverting input and the second input of the n-way comparator is an inverting input.
4. The circuit of claim 1, wherein the first bandgap reference current source and the second bandgap reference current source generate the same current.
5. The analog filter bandwidth calibration method is applied to an analog filter bandwidth calibration circuit, and the circuit comprises a first band-gap reference current source, a second band-gap reference current source, a target capacitor, n resistance units and n comparators; the first bandgap reference current source is grounded through a first node and the target capacitor in sequence; the first node is connected to a first input end of the n-path comparator; the second band-gap reference current source is grounded through the n resistor units which are connected in series in sequence; in the n resistor units connected in series, the first end of the kth resistor unit is connected to the second end of the (k-1) th resistor unit; k is more than 1 and less than or equal to n; the first ends of the n resistance units are respectively connected to the second input ends of the n paths of comparators; the output end of the n-path comparator is connected to the capacitor array of the filter;
the method comprises the following steps:
acquiring target charging time; the target charging time is the predicted time for charging the target capacitor to a specified voltage;
charging the target capacitor through the first bandgap reference current source according to the target charging time to obtain a target voltage on the target capacitor;
comparing the voltage on the first ends of the n resistance units with the target voltage through the n-path comparators respectively to generate a target binary code;
and adjusting the capacitance of the filter according to the target binary code.
6. The method of claim 5, further comprising:
and on the simulation software, the target capacitor is subjected to simulation charging to a specified voltage, and the target charging time is obtained.
7. The method of claim 6, wherein the analog charging of the target capacitor to a specified voltage to obtain a target charging time comprises:
charging the target capacitor through the first bandgap reference current source to obtain a simulation voltage;
respectively comparing the simulation voltage with n reference voltages through n paths of comparators, and acquiring a simulation binary code at the output end of the n paths of comparators; the n reference voltages are voltages at first ends of the n resistance units when the n resistance units connected in series are powered through a second band-gap reference current source;
and adjusting the charging time and the simulation voltage until the target bit of the simulation binary code is 1, the codes in the simulation binary code higher than the target bit are all 0, the codes in the simulation binary code lower than the target bit are all 1, taking the adjusted simulation voltage as a specified voltage, and taking the adjusted charging time as the target charging time.
8. The method of claim 5, wherein the n-bit codes in the target binary code are generated from the outputs of n-way comparators, respectively;
the first input end of the n-path comparator is a non-inverting input end, and the second input end of the n-path comparator is an inverting input end.
9. The method according to claim 8, wherein for each of the n-way comparators, when the voltage at the non-inverting input terminal of the comparator is greater than the voltage at the inverting input terminal of the comparator, the code bit corresponding to the comparator in the target binary code is 1;
and when the voltage of the non-inverting input end of the comparator is less than the voltage of the inverting input end of the comparator, the code bit corresponding to the comparator in the target binary code is 0.
10. The method of claim 5, wherein adjusting the capacitance of the filter according to the target binary code comprises:
when the binary coding bit corresponding to the output end of the comparator is 1, the filter capacitor corresponding to the output end of the comparator is conducted;
and when the binary coding bit corresponding to the output end of the comparator is 0, the filter capacitor corresponding to the output end of the comparator is disconnected.
CN202211310287.9A 2022-10-25 2022-10-25 Analog filter bandwidth calibration circuit and calibration method Pending CN115567034A (en)

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