CN115549854A

CN115549854A - Cyclic redundancy check method, cyclic redundancy check device, storage medium and electronic device

Info

Publication number: CN115549854A
Application number: CN202110742121.3A
Authority: CN
Inventors: 不公告发明人
Original assignee: Shanghai Cambricon Information Technology Co Ltd
Current assignee: Shanghai Cambricon Information Technology Co Ltd
Priority date: 2021-06-30
Filing date: 2021-06-30
Publication date: 2022-12-30

Abstract

The embodiment of the application provides a cyclic redundancy check method, a cyclic redundancy check device, a storage medium and electronic equipment, wherein the method comprises the following steps: acquiring data to be processed; splitting the data to be processed according to the bit width of the data to be processed to obtain N first-level sub-data to be processed, wherein N is a positive integer; and distributing the N first-stage sub-to-be-processed data to the M-stage CRC calculation module to obtain a target CRC calculation result corresponding to the to-be-processed data. According to the CRC calculation method and device, the data to be processed can be split, the multiple pieces of first-level sub data to be processed obtained after splitting are distributed to the M-level CRC calculation module to be subjected to CRC calculation, CRC calculation of high-bit-width data can be achieved, and the CRC efficiency can be improved.

Description

Cyclic redundancy check method, cyclic redundancy check device, storage medium and electronic device

Technical Field

The present application relates to the field of processor technologies, and in particular, to a cyclic redundancy check method and apparatus, a storage medium, and an electronic device.

Background

In the data communication process, hardware is often required to perform Cyclic Redundancy Check (CRC) processing on communication data packets to ensure data correctness. However, when the data bit width is large, the conventional cyclic redundancy check method is difficult to meet the timing requirement of the digital circuit.

Disclosure of Invention

The embodiment of the application provides a cyclic redundancy check method, a cyclic redundancy check device, a storage medium and electronic equipment, which can realize CRC calculation of high-bit-width data, can meet the time sequence requirement of a digital circuit and is beneficial to improving the cyclic redundancy check efficiency.

In a first aspect, an embodiment of the present application provides a cyclic redundancy check method, which is applied to a cyclic redundancy check system, where the cyclic redundancy check system includes M-level CRC calculation modules, where M is a positive integer; the method comprises the following steps:

acquiring data to be processed;

splitting the data to be processed according to the bit width of the data to be processed to obtain N pieces of first-level sub-data to be processed, wherein N is a positive integer;

and distributing the N pieces of first-stage sub data to be processed to the M-stage CRC calculation module to obtain a target CRC calculation result corresponding to the data to be processed.

In a second aspect, an embodiment of the present application provides a cyclic redundancy check method, which is applied to a CRC calculation module; the method comprises the following steps:

receiving first-level sub data to be processed, wherein the first-level sub data to be processed is any one of N first-level sub data to be processed, and the N first-level sub data to be processed are obtained by splitting the data to be processed by a cyclic redundancy check system according to the bit width of the data to be processed;

and acquiring a preset value, and performing CRC calculation on the first-level sub data to be processed and the preset value to obtain a CRC calculation result corresponding to the first-level sub data to be processed, wherein the preset value is a preset initial value or a previous-level CRC calculation result corresponding to a previous-level CRC calculation module, and the CRC calculation result is used for determining a target CRC calculation result corresponding to the data to be processed.

In a third aspect, an embodiment of the present application provides a cyclic redundancy check apparatus, which is applied to a cyclic redundancy check system, where the cyclic redundancy check system includes an M-level CRC calculation module, where M is a positive integer; the device comprises:

the acquisition unit is used for acquiring data to be processed;

the splitting unit is used for splitting the data to be processed according to the bit width of the data to be processed to obtain N first-level sub-data to be processed, wherein N is a positive integer;

and the distribution unit is used for distributing the N first-level sub-to-be-processed data to the M-level CRC calculation module to obtain a target CRC calculation result corresponding to the to-be-processed data.

In a fourth aspect, an embodiment of the present application provides a combined processing apparatus, which includes the cyclic redundancy check apparatus according to the third aspect, a universal interconnect interface, and other processing apparatuses. The cyclic redundancy check device interacts with the other processing devices to jointly complete the operation designated by the user. The combined processing device may further include a storage device, which is respectively connected with the cyclic redundancy check device and the other processing device, for storing data of said cyclic redundancy check means and said other processing means.

In a fifth aspect, an embodiment of the present application provides a neural network chip, where the neural network chip includes the cyclic redundancy check apparatus described in the third aspect above, or the combined processing apparatus described in the fourth aspect above.

In a sixth aspect, an embodiment of the present application provides a neural network chip package structure, which includes the neural network chip described in the fifth aspect.

In a seventh aspect, an embodiment of the present application provides a board, where the board includes a storage device, an interface device, a control device, and the neural network chip in the fifth aspect; wherein, the neural network chip is respectively connected with the storage device, the control device and the interface device; the storage device is used for storing data; the interface device. The chip is used for realizing data transmission between the chip and external equipment; and the control device is used for monitoring the state of the chip.

In an eighth aspect, an embodiment of the present application provides an electronic device, where the electronic device includes a memory, a processor, a communication bus, and a communication interface, where the processor and the communication interface memory complete communication with each other through the communication bus; the memory is used for storing computer programs; the processor is configured to implement some or all of the steps described in the above first aspect or second aspect when executing the program stored in the memory.

In a ninth aspect, embodiments of the present application provide a computer-readable storage medium including a computer program stored thereon for data exchange, wherein the computer program, when executed by a processor, implements some or all of the steps as described in the first or second aspect of embodiments of the present application.

In a tenth aspect, embodiments of the present application provide a computer program product, where the computer program product includes a non-transitory computer-readable storage medium storing a computer program, where the computer program is operable to cause a computer to perform some or all of the steps as described in the first aspect or the second aspect of embodiments of the present application. The computer program product may be a software installation package.

The embodiment of the application provides a cyclic redundancy check method, a cyclic redundancy check device, a storage medium and electronic equipment, which can acquire data to be processed; splitting the data to be processed according to the bit width of the data to be processed to obtain N first-level sub-data to be processed, wherein N is a positive integer; and distributing the N first-stage sub-to-be-processed data to the M-stage CRC calculation module to obtain a target CRC calculation result corresponding to the to-be-processed data. According to the CRC calculation method and device, the data to be processed can be split, the multiple pieces of first-level sub data to be processed obtained after splitting are distributed to the M-level CRC calculation module to be subjected to CRC calculation, CRC calculation of high-bit-width data can be achieved, and the CRC efficiency can be improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of a CRC calculation module according to an embodiment of the present disclosure;

fig. 3a is a schematic flowchart of a cyclic redundancy check method according to an embodiment of the present application;

fig. 3b is a schematic processing flow diagram of a cyclic redundancy check method according to an embodiment of the present application;

fig. 4 is a schematic flowchart of a cyclic redundancy check method according to an embodiment of the present application;

fig. 5a is a block diagram illustrating functional units of a cyclic redundancy check apparatus according to an embodiment of the present disclosure;

FIG. 5b is a block diagram illustrating functional units of another cyclic redundancy check apparatus according to an embodiment of the present disclosure;

fig. 6 is a structural diagram of a combined processing device provided in an embodiment of the present application;

fig. 7 is a schematic structural diagram of a board card provided in the embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

For a better understanding of the aspects of the embodiments of the present application, the following description is provided for a possible background of the embodiments of the present application.

Generally, during data transmission, an error may occur inevitably due to noise interference, and the like, and the error may cause one or more frames transmitted on a link to be corrupted (for example, a bit error occurs, 0 becomes 1, or 1 becomes 0), so that a receiver receives wrong data. Therefore, hardware is often required to perform Cyclic Redundancy Check (CRC) processing on the communication data packets to ensure the correctness of the data received by the receiver.

Currently, when implementing CRC calculation, most hardware adopts a parallel calculation method, that is, CRC calculation is performed on multi-bit (bit) data in one clock cycle, and the result of the calculation in the current clock cycle is saved, and participates in CRC calculation again with the data in the next clock cycle, and so on until the data calculation in the last clock cycle is completed, the calculation result is spliced at the end of the data and is output together with the data.

The target CRC parallel computation can obtain a CRC computation Register Level (RTL) code with any length and data bit width through open source software, and currently, in the implementation process of CRC parallel computation, the mainstream implementation scenario is as follows: the data bit width is 512 bits, and the clock frequency is 1Ghz, but when the bit width of the data is large and the clock frequency is high, the RTL code provided by the open source software is difficult to meet the requirement of the circuit timing sequence.

The present application will be described in detail with reference to specific examples.

Referring to fig. 1, fig. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure, and as shown in fig. 1, the electronic device includes a memory, an input device, an output device, and a processor, where the electronic device may further include a communication bus, and the processor, the input device, the output device, and the memory may be connected to each other through the bus. Optionally, the electronic device may further include an instruction storage unit disposed adjacent to the processor.

The processor is configured to implement the following steps when executing the program stored in the memory:

acquiring data to be processed; splitting the data to be processed according to the bit width of the data to be processed to obtain N first-level sub-data to be processed, wherein N is a positive integer; and distributing the N first-stage sub-to-be-processed data to an M-stage CRC calculation module to obtain a target CRC calculation result corresponding to the to-be-processed data.

Further, the processor may be a Central Processing Unit (CPU), an intelligent Processing Unit (NPU), a Graphics Processing Unit (GPU), or an Image Processing Unit (Image Processing Unit), which is not limited in this application.

Referring to fig. 2, fig. 2 is a schematic diagram of an architecture of an M-level CRC calculation module according to an embodiment of the present disclosure, where the architecture may include the M-level CRC calculation module, and the M-level CRC calculation module may be disposed in a chip for detecting data accuracy during a chip processing process. For example, the chip may be a processor chip, which may be a general-purpose processor chip (such as a CPU), or an intelligent processor chip, and is not limited herein.

Each stage of CRC calculation module may be configured to receive data to be processed issued by the processor, and each CRC calculation module may correspond to hardware resource data, where the hardware resource data may include at least one of the following: data bit width, clock frequency, etc., without limitation. Since the hardware resource data corresponding to each stage of CRC calculation module may be different or the same, when the data to be processed is allocated to the M stages of CRC calculation modules, the bit widths of the first stage sub-processed data divided by each CRC calculation module may be different or the same.

Referring to fig. 3a, fig. 3a is a schematic flowchart illustrating a cyclic redundancy check method according to an embodiment of the present disclosure, where the method is applied to a processor of an electronic device. The electronic equipment processor comprises a cyclic redundancy check system, wherein the cyclic redundancy check system comprises an M-level CRC calculation module, and M is a positive integer; as shown in fig. 3a, the method comprises the steps of:

and S310, acquiring data to be processed.

The embodiment of the application is applied to an electronic device processor, the electronic device processor may include a cyclic redundancy check system, and the cyclic redundancy check system may include an M-level CRC calculation module, where M is a positive integer.

The data to be processed may refer to data that needs to be subjected to Cyclic Redundancy Check (CRC). Optionally, the bit width of the data to be processed may be greater than the maximum data bit width of the CRC calculation module, for example, the maximum data bit width of the CRC calculation module may be 512 bits, and the data to be processed may be 1024 bits, 1536 bits, 2048 bits, and the like, which is not limited herein.

S320, splitting the data to be processed according to the bit width of the data to be processed to obtain N first-stage sub-data to be processed, wherein N is a positive integer.

Specifically, hardware resource data of the M-level CRC calculation module may be determined, the hardware resource data including at least one of: the clock frequency, the data bit width, and the like are not limited herein, and furthermore, the data to be processed may be split according to the bit width of the data to be processed and the hardware resource data of the M-level CRC calculation module, so as to obtain N first-level sub-data to be processed.

For example, if it is determined that the cyclic redundancy check system can realize calculation of 512 bits in one period under the condition that the cyclic redundancy check system meets the timing requirement, then the to-be-processed data of 1536 bits can be split into 3 pieces of 512-bit data according to the corresponding bit width and the data bit width of the CRC calculation module, where each 512-bit data is a first-level sub-to-be-processed data.

In one possible example, each first-level sub-pending data is the same or different in bit width. Since the hardware resource data of each CRC calculation module may be different, when the to-be-processed data is split according to the hardware resource data of the CRC calculation module, bit width of each first-stage sub-to-be-processed data may be different, and the bit width may be the same as the data bit width of the CRC calculation module. Specifically, when the hardware resource data of each CRC calculation module is the same, the data bit width of the data to be processed at each stage is the same, that is, when the data to be processed is uniformly split according to the data bit width of the CRC calculation module. Of course, the data to be processed may also be directly divided into the first-level sub data to be processed with the same bit width, which is not limited in this application.

In one possible example, each first-stage sub-to-be-processed data corresponds to one clock cycle, i.e., the CRC calculation module of each stage can process one first-stage to-be-processed data in one clock cycle.

In a possible example, splitting the data to be processed according to the bit width of the data to be processed to obtain N first-level sub-data to be processed may include the following steps: determining a splitting ratio corresponding to the data to be processed according to the data bit width of each CRC calculation module and the bit width of the data to be processed, wherein the data bit width of the CRC calculation module comprises a theoretical maximum data bit width and an actual maximum data bit width; and splitting the data to be processed according to the splitting proportion to obtain N first-level sub data to be processed.

The data bit width may be understood as a maximum data bit width corresponding to data that can be processed by the CRC calculation module, and the data bit width may include at least one of: the theoretical maximum data bit width and the actual maximum data bit width are not limited herein; the theoretical maximum data bit width can be understood as the maximum data bit width corresponding to the data which can be processed by the CRC calculation module under the normal processing condition, and the actual maximum data bit width can be understood as the maximum data bit width corresponding to the data which can be processed by the CRC calculation module in the actual work. For example, if the CRC calculation module can process data with a theoretical maximum data bit width of 512 bits, but due to the influence of the chip production process, the CRC calculation module may not reach the theoretical maximum data bit width, and the actual maximum data bit width of the CRC module may be smaller than or equal to the theoretical maximum data bit width.

In specific implementation, the splitting ratio corresponding to the data to be processed is determined according to the bit width of the data to be processed and the theoretical maximum data bit width or the actual maximum data bit width of the CRC calculation module, and the splitting ratio can be determined according to specific situations. For example, if the actual maximum data bit width of the CRC calculation module can reach the theoretical maximum data bit width, that is, the actual maximum data bit width is equal to the theoretical maximum data bit width, a split ratio may be determined for the to-be-processed data according to the bit width of the to-be-processed data and the theoretical maximum data bit width of the CRC calculation module, and the to-be-processed data may be split into N first-level sub-to-be-processed data according to the split ratio. If the actual maximum data bit width of the CRC calculation module is smaller than the theoretical maximum data bit width, a splitting ratio may be determined for the data to be processed according to the bit width of the data to be processed and the actual maximum data bit width of the CRC calculation module, and the data to be processed is split into N first-level sub-data to be processed according to the splitting ratio.

For example, there are 3 levels of CRC calculation modules, and the theoretical maximum data bit width corresponding to each level of CRC calculation module is 512 bits, then it is determined that the split ratio corresponding to the data to be processed is: 1. For another example, there are 3 levels of CRC calculation modules, the theoretical maximum data bit widths corresponding to each level of CRC calculation module are 256bit, 512bit, if the bit width of the data to be processed is 1024bit, if the actual maximum data bit width of the 3 levels of CRC calculation modules can reach the theoretical maximum data bit width corresponding to each level of CRC calculation modules, the corresponding split ratio of the data to be processed can be determined according to the bit width of the data to be processed and the theoretical maximum data bit width corresponding to each CRC module as follows: 1.

Therefore, in the embodiment of the present application, in a specific implementation, the data to be processed may be split according to the data bit width of each CRC calculation module and the bit width of the data to be processed, so as to meet the design requirement of each CRC calculation module, and each first-stage sub-data to be processed is adapted to the CRC calculation module, which is beneficial to improving the data processing efficiency.

Optionally, when the to-be-processed data is split, the to-be-processed data may be split in advance as in the above embodiment, or may be split in real time according to a CRC calculation module allocated by an electronic device processor or a system in the processing process, and a specific splitting manner is consistent with the above embodiment, and the to-be-processed data may be split according to a data bit width of the CRC calculation module, which is not described herein again.

Optionally, after the splitting, if the actual maximum data bit width corresponding to the CRC calculation module is greater than the bit width of the first-stage sub data to be processed, zero padding is performed on the first-stage sub data to be processed. When each first-stage sub data to be processed can be allocated to any one of the M-stage CRC calculation modules, there may be a case that a bit width of the first-stage sub data to be processed is smaller than a data bit width (an actual maximum data bit width or a theoretical maximum data bit width, a specific data bit width may be determined according to a splitting rule, and if the data to be processed is divided according to the theoretical maximum data bit width, the data bit width at the position is the theoretical maximum data bit width), then, in order to make the CRC calculation smoothly performed, zero padding processing may be performed on the first-stage sub data to be processed, so that the bit width of the first-stage sub data to be processed is the same as the data bit width (the actual maximum data bit width or the theoretical maximum data bit width) of the CRC calculation module.

Optionally, before splitting the data to be processed, if the bit width of the data to be processed is smaller than the sum of the theoretical maximum data bit widths of all CRC calculation modules in the M-level CRC calculation module, it indicates that the bit width of the data to be processed cannot divide the data bit width of the CRC calculation module, so that the data bit width of the sub-processing data obtained by part of the CRC calculation modules is smaller than the data bit width that can be processed by the CRC calculation module, at this time, zero padding processing may be performed on the data to be processed, and the data to be processed after zero padding is split, so as to obtain the sub-data to be processed. S330, distributing the N first-level sub-to-be-processed data to the M-level CRC calculation module to obtain a target CRC calculation result corresponding to the to-be-processed data.

The M-level CRC calculation module is configured to perform CRC calculation on the received first-level sub data to be processed respectively to obtain a CRC calculation result, where the CRC calculation result is a check code, and after performing CRC calculation on the last first-level sub data to be processed, the obtained CRC calculation result is a target CRC calculation result, where the target CRC calculation result is a check code corresponding to the data to be processed. The CRC calculation module calculates the bits of the CRC calculation result obtained by CRC calculation according to a specific CRC algorithm. For example, if the CRC calculation module adopts the CRC-8 algorithm, the CRC calculation module outputs a calculation result of 8 bits. If the CRC calculation module adopts a CRC-16 algorithm, the CRC calculation module outputs a 16-bit calculation result. If the CRC calculation module adopts a CRC-32 algorithm, the CRC calculation module outputs a calculation result of 32 bits.

In a possible example, the allocating the N first-level sub-to-be-processed data to the M-level CRC calculation module to obtain a target CRC calculation result corresponding to the to-be-processed data includes: allocating ith first-stage sub-to-be-processed data in the N first-stage sub-to-be-processed data to a jth-stage CRC calculation module in the M-stage CRC calculation modules to obtain an ith CRC calculation result corresponding to the ith first-stage sub-to-be-processed data, wherein i is a positive integer greater than 1, and the jth-stage CRC calculation module is any one of the M-stage CRC calculation modules; distributing the i CRC calculation results and the (i + 1) th first-stage sub-to-be-processed data to a j +1 th-stage CRC calculation module to obtain an (i + 1) th CRC calculation result; and determining the target CRC calculation result according to the (i + 1) th CRC calculation result.

Wherein, i is a positive integer greater than 1 and less than or equal to N, the jth CRC calculation module is any one of the M CRC calculation modules, and j is a positive integer less than or equal to M.

In a specific implementation, after the ith first-level sub-to-be-processed data is distributed to the jth-level CRC calculation module, an ith CRC calculation result corresponding to the ith first-level sub-to-be-processed data is obtained through CRC calculation, and further, the ith CRC calculation result may be used as an input of the jth + 1-level CRC calculation module, and is subjected to CRC calculation with the (i + 1) -th first-level sub-to-be-processed data, so as to obtain an (i + 1) -th CRC calculation result corresponding to the (i + 1) -th first-level sub-to-be-processed data; and performing CRC calculation in such a cycle, wherein each stage of CRC calculation module is related to the CRC calculation result obtained by the calculation of the previous stage of CRC calculation module.

In one possible example, when i =1, the method further includes: and distributing a preset initial value and the first-stage sub data to be processed to a j-th-stage CRC calculation module to obtain a first CRC calculation result corresponding to the first-stage sub data to be processed.

The preset initial value can be set by a user or defaulted by a system, and is not limited herein; for example, when the CRC algorithm is CRC-32, the predetermined initial value may be 32 bits, and the number of bits of the predetermined initial value is related to the selected CRC algorithm. The preset initial value may also be generated by the CRC module.

When i =1, that is, the first-stage sub data to be processed is allocated to the CRC calculation module, CRC calculation may be performed according to the first-stage sub data to be processed and a preset initial value, so as to obtain a first CRC calculation result.

In one possible example, the determining the target CRC calculation result according to the (i + 1) th CRC calculation result may include: if the i +1=N is the i +1 th CRC calculation result, taking the i +1 th CRC calculation result as the target CRC calculation result; if the i +1<N is determined, the i +1 th CRC calculation result and the i +2 th first-level sub-to-be-processed data are distributed to a j +2 th CRC calculation module to obtain an i +2 th CRC calculation result, and the target CRC calculation result is determined according to the i +2 th CRC calculation result.

When the (i + 1) th first-level sub data to be processed is the last of the N first-level sub data to be processed, then, the (i + 1) th CRC calculation result obtained by CRC calculation can be used as a target CRC calculation result corresponding to the data to be processed; if the (i + 1) th sub-to-be-processed data is not the last of the N first-stage sub-to-be-processed data, the (i + 1) th CRC calculation result and the (i + 2) th sub-to-be-processed data can be continuously calculated by the (j + 2) th CRC calculation module to obtain the (i + 2) th CRC calculation result, and the above steps are repeated to obtain the CRC calculation result corresponding to the last sub-to-be-processed data, that is, the target CRC calculation result corresponding to the to-be-processed data. Each CRC calculation module can perform CRC calculation on the first-level sub data to be processed to obtain a CRC calculation result, wherein the CRC calculation result is a check code corresponding to the first-level sub data to be processed.

In one possible example, the method may further include the steps of: in the process of allocating the N first-stage sub data to be processed to the M-stage CRC calculation module, if an actual maximum data bit width corresponding to the P-th stage CRC calculation module is smaller than a bit width of a kth first-stage sub data to be processed, splitting the kth first-stage sub data to be processed according to the actual maximum data bit width of the P-th stage CRC calculation module to obtain Q split second-stage sub data to be processed, where P, Q is a positive integer; distributing the first second-level sub-to-be-processed data in the Q second-level sub-to-be-processed data to the P-level CRC calculation module to obtain a ki CRC calculation result, distributing the ki CRC calculation result and the second-level sub-to-be-processed data to the P + 1-level CRC calculation module to obtain a ki + 1-level CRC calculation result until the Q second-level sub-to-be-processed data are processed by the CRC calculation module to obtain a CRC calculation result corresponding to the kth first-level sub-to-be-processed data; and ki is the CRC calculation result corresponding to one of the Q pieces of second-level sub data to be processed. P, Q are positive integers. The bit width of each second-level sub-to-be-processed data in the Q second-level sub-to-be-processed data is smaller than the actual maximum data bit width corresponding to the P-level CRC calculation module.

In this embodiment of the application, if the data to be processed is split into N first-level sub data to be processed, the electronic device splits the actual maximum data bit width of the CRC calculation module according to the theoretical maximum data bit width of the CRC calculation module, which may be less than or equal to the theoretical maximum data bit width. When the P-th CRC calculation module performs CRC calculation on the kth first-stage sub data to be processed, if the actual maximum data bit width of the P-th CRC calculation module is smaller than the theoretical maximum data bit width, for example, if the theoretical maximum data bit width of the CRC calculation module is 512 bits, the bit width of the split first-stage sub data to be processed is 512 bits, and the actual maximum data bit width of the CRC calculation module is 256 bits, at this time, the CRC calculation module does not have the capability of processing the kth first-stage sub data to be processed, so that the kth first-stage sub data to be processed needs to be split at a finer granularity, so as to ensure that the whole cyclic redundancy check is performed normally.

Specifically, the kth first-stage sub data to be processed may be split according to the bit width of the kth first-stage sub data to be processed and the actual maximum bit width of the pth CRC calculation module, so as to obtain Q second-stage sub data to be processed, where the bit width of each second-stage sub data to be processed is less than or equal to the actual maximum data bit width corresponding to the pth CRC calculation module.

Further, the Q second-level sub data to be processed are sequentially allocated to the P-level CRC calculation module, and in a specific implementation, the first second-level sub data to be processed may be allocated to the P-level CRC calculation module, at this time, the ki CRC calculation result may be obtained, and then the ki CRC calculation result and the second-level sub data to be processed are allocated to the next-level CRC calculation module, that is, the P + 1-level CRC calculation module, so as to obtain the ki + 1-level CRC calculation results corresponding to the second-level sub data to be processed, until the Q second-level sub data to be processed are all processed by the CRC calculation module. After the Q second-level sub data to be processed are all processed by the CRC calculation module, a CRC calculation result corresponding to the kth first-level sub data to be processed may be obtained.

Optionally, after the ki CRC calculation result and the second-stage sub data to be processed are allocated to the P + 1-th-stage CRC calculation module, and the ki + 1-th CRC calculation result is obtained, since Q second-stage sub data to be processed are added, the number of the original k + 1-th first-stage sub data to be processed is updated to the [ (k +1+ (Q-1)) ] = (k + Q) -th first-stage sub data to be processed, at this time, the (P +1+ (Q-1) ] = (P + Q) -th CRC calculation module may perform CRC calculation on the original k + 1-th, that is, the k + Q-th first-stage sub data to be processed, and so on until all the first-stage data to be processed are completely processed by the M-stage CRC calculation module.

It can be seen that, in the embodiment of the present application, if the data to be processed is divided according to the corresponding bit width and the theoretical maximum data bit width of the M-level CRC calculation module, in the process of allocating N pieces of first-level sub data to be processed, there may be a case where the actual maximum data bit width of a certain CRC calculation module is smaller than the corresponding theoretical maximum data bit width, that is, in the present case, the CRC calculation module does not have the capability of processing the first-level sub data to be processed, then the first-level sub data to be processed may be divided according to the actual maximum data bit width corresponding to the CRC calculation module, so as to obtain a plurality of second-level sub data to be processed, and further, the CRC calculation module has the capability of processing the second-level sub data to be processed, and the CRC calculation module may process the second-level sub data to be processed, and at the same time, the next second-level sub data to be processed of the second-level sub data to be processed is processed by the next-level CRC calculation module, and the cycle is performed. Therefore, the second-level sub-to-be-processed data with the capacity adapted to the CRC calculation module can be adapted to the CRC calculation module in real time according to the actual maximum data bit width of the CRC calculation module, the situation of blocking or jamming is avoided, normal running of cyclic redundancy check is guaranteed, and the efficiency of the whole cyclic redundancy check is improved.

Optionally, after obtaining the Q split second-level sub data to be processed, the method may further include the following steps: sequentially distributing each second-level sub-to-be-processed data in the Q second-level sub-to-be-processed data distribution to the P-level CRC calculation module, and obtaining a kth CRC calculation result through at least one CRC calculation; and distributing the kth CRC calculation result and the (k + 1) th first-level sub-to-be-processed data to a (P + 1) th-level CRC calculation module to obtain a (k + 1) th CRC calculation result.

In this embodiment of the present application, the P-th CRC calculation module may first complete the calculation of the CRC of the first second-stage sub data to be processed, obtain a check code, and perform CRC calculation according to the check code and the second-stage sub proxy data until the Q second-stage sub data to be processed are all calculated, so as to obtain a kth CRC calculation result corresponding to the kth first-stage sub data to be processed. In the application, after CRC calculation of all the second-level sub data to be processed is completed on the kth first-level sub data to be processed, namely CRC calculation of Q second-level sub data to be processed, a kth CRC calculation result corresponding to the kth first-level sub data to be processed can be obtained, and further CRC calculation of the kth +1 first-level sub data to be processed can be completed through the P + 1-level CRC calculation module and the kth CRC calculation result.

As can be seen, in the embodiment of the present application, since the actual maximum data bit width of the next-stage CRC calculation module, that is, the P + 1-stage CRC calculation module, is not necessarily the same as the actual maximum data bit width of the P-stage CRC calculation module, and the bit width of the second-stage sub data to be processed is related to the actual maximum data bit width of the P-stage CRC calculation module, if the actual maximum data bit width of the P + 1-stage CRC calculation module is smaller than the actual maximum data bit width of the P-stage CRC calculation module, the second-stage sub data to be processed is split again, so that waste of calculation resources is easily caused.

Optionally, when any one of the second-level sub to-be-processed data is allocated to any one of the CRC calculation modules in the M-level CRC calculation module, if an actual maximum data bit width corresponding to the CRC calculation module is greater than a bit width of the second-level sub to-be-processed data, zero padding is performed on the second-level sub to-be-processed data.

For example, when the second-level sub to-be-processed data is allocated to the P-th CRC calculation module or the P + 1-th CRC calculation module, if the bit width of the second-level sub to-be-processed data is smaller than the actual maximum data bit width of any one of the CRC calculation modules, then, in order to make the CRC calculation smoothly performed, zero padding processing may be performed on the second-level sub to-be-processed data, so that the bit width of the second-level sub to-be-processed data is the same as the actual maximum data bit width of the CRC calculation module.

In a possible example, after obtaining a target CRC calculation result corresponding to the data to be processed, the following steps may be further included: and splicing the target CRC calculation result with the data to be processed to obtain target data.

The electronic equipment can send the target data to the receiving side equipment, the receiving side equipment can perform division calculation on the target data, if the remainder is equal to zero, the target data is considered to have no transmission error, and if the remainder is not equal to zero, the target data is considered to have an error in the transmission process.

For example, as shown in fig. 3b, fig. 3b is a schematic processing flow diagram of a cyclic redundancy check method provided in this embodiment of the present application, and as shown in the figure, if the data to be processed is 1536 bits, and each stage of CRC calculation module adopts a CRC-32 algorithm to implement CRC calculation, where each CRC calculation module can be used to process data with a 512bit width, the data with 1536 bits can be split into 3 data with 512 bits, which are respectively a first-stage sub data to be processed 1, a first-stage sub data to be processed 2, and a first-stage sub data to be processed 3, and then the data to be processed can be allocated to the above 3 stages of CRC calculation modules, and the first-stage CRC calculation module performs CRC calculation according to the first-stage sub data to be processed 1 and an initial value (a preset initial value), so as to obtain a CRC calculation result corresponding to the first-stage sub data to be processed 1, that is a check code 1 with 32 bits; furthermore, the 32-bit check code 1 and the first-stage sub data to be processed 2 can be continuously sent to the second-stage CRC calculation module for CRC calculation, and a CRC calculation result corresponding to the first-stage sub data to be processed 2, namely a 32-bit check code 2, is obtained; furthermore, the check code 2 of 32 bits and the first-level sub data to be processed 3 can be continuously sent to the 3 rd-level CRC calculation module for CRC calculation, and a CRC calculation result corresponding to the data to be processed, namely a target check code of 32 bits, is obtained; and finally, splicing the target check code and the data to be processed to obtain target data.

It can be seen that the cyclic redundancy check method described in the embodiments of the present application can obtain data to be processed; splitting the data to be processed according to the bit width of the data to be processed to obtain N first-level sub-data to be processed, wherein N is a positive integer; and distributing the N first-stage sub-to-be-processed data to the M-stage CRC calculation module to obtain a target CRC calculation result corresponding to the to-be-processed data. According to the CRC calculation method and device, the data to be processed can be split, the multiple pieces of first-level sub data to be processed obtained after splitting are distributed to the M-level CRC calculation module to be subjected to CRC calculation, CRC calculation of high-bit-width data can be achieved, and the CRC efficiency can be improved.

Referring to fig. 4, fig. 4 is a schematic processing flow diagram of a cyclic redundancy check method according to an embodiment of the present disclosure, where the method is applied to a CRC calculation module; as shown in fig. 4, the method includes the steps of:

s401, receiving first-level sub data to be processed, wherein the first-level sub data to be processed is any one of N first-level sub data to be processed, and the N first-stage sub-data to be processed are obtained by splitting the data to be processed by a cyclic redundancy check system according to the bit width of the data to be processed.

S402, obtaining a preset value, and performing CRC calculation on the first-stage sub data to be processed and the preset value to obtain a CRC calculation result corresponding to the first-stage sub data to be processed, wherein the preset value is an initial value or a previous-stage CRC calculation result corresponding to a previous-stage CRC calculation module, and the CRC calculation result is used for determining a target CRC calculation result corresponding to the data to be processed.

In the embodiment of the present application, the CRC calculation module may be any one of the M-stage CRC calculation modules shown in fig. 2.

The preset value can be set by a user or defaulted by a system, and is not limited herein; the preset value may be a preset initial value, and may also be a CRC calculation result corresponding to a CRC calculation module in a previous stage. The preset initial value may be set by the user or default by the system, and is not limited herein, the preset initial value may be an initial value when the check code corresponding to the first-stage sub data to be processed is calculated, and the number of bits of the initial value is related to the CRC algorithm used.

Wherein, each CRC calculation module has two functions: if the preset value is a preset initial value, the first-stage sub data to be processed received by the CRC calculation module is the first of the N first-stage sub data to be processed; if the preset value is the result of the CRC calculation of the previous stage, the sub-to-be-processed data received by the module is not the first of the N sub-to-be-processed data, and may be the second, the third, etc.

The above description has introduced the solution of the embodiment of the present application mainly from the perspective of the method-side implementation process. It is understood that the electronic device comprises corresponding hardware structures and/or software modules for performing the respective functions in order to realize the above-mentioned functions. Those of skill in the art will readily appreciate that the present application is capable of hardware or a combination of hardware and computer software implementing the various illustrative elements and algorithm steps described in connection with the embodiments provided herein. Whether a function is performed as hardware or computer software drives hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiment of the present application, the electronic device may be divided into the functional units according to the method example, for example, each functional unit may be divided corresponding to each function, or two or more functions may be integrated into one processing unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit. It should be noted that the division of the unit in the embodiment of the present application is schematic, and is only a logic function division, and there may be another division manner in actual implementation.

Referring to fig. 5a, fig. 5a is a block diagram of functional units of a cyclic redundancy check apparatus 500 according to an embodiment of the present disclosure, as shown in fig. 5a, applied to a cyclic redundancy check system, where the cyclic redundancy check system includes M stages of CRC calculation modules, where M is a positive integer; the cyclic redundancy check apparatus 500 includes an obtaining unit 510, a splitting unit 520, and an allocating unit 530.

The acquiring unit 510 is configured to acquire data to be processed;

the splitting unit 520 is configured to split the data to be processed according to the bit width of the data to be processed, so as to obtain N first-level sub-data to be processed, where N is a positive integer;

the allocating unit 530 is configured to allocate the N first-level sub data to be processed to the M-level CRC calculation module, so as to obtain a target CRC calculation result corresponding to the data to be processed.

It can be seen that the embodiments of the present application provide a cyclic redundancy check apparatus, which can obtain data to be processed; splitting the data to be processed according to the bit width of the data to be processed to obtain N first-level sub-data to be processed, wherein N is a positive integer; and distributing the N first-stage sub-to-be-processed data to the M-stage CRC calculation module to obtain a target CRC calculation result corresponding to the to-be-processed data. According to the CRC calculation method and device, the data to be processed can be split, the multiple pieces of first-level sub data to be processed obtained after splitting are distributed to the M-level CRC calculation module to be subjected to CRC calculation, CRC calculation of high-bit-width data can be achieved, and the CRC efficiency can be improved.

Optionally, the N first-level sub-to-be-processed data are allocated to the M-level CRC calculation module, so as to obtain a target CRC calculation result corresponding to the to-be-processed data; the allocating unit 530 is specifically configured to:

allocating ith first-level sub-to-be-processed data in the N first-level sub-to-be-processed data to a jth-level CRC calculation module in the M-level CRC calculation modules to obtain an ith CRC calculation result corresponding to the ith first-level sub-to-be-processed data, wherein i is a positive integer greater than 1, and the jth-level CRC calculation module is any one of the M-level CRC calculation modules;

distributing the i CRC calculation results and the (i + 1) th first-level sub-to-be-processed data to a (j + 1) th CRC calculation module to obtain an (i + 1) th CRC calculation result;

and determining the target CRC calculation result according to the (i + 1) th CRC calculation result.

Optionally, when i = 1; the allocating unit 530 is further specifically configured to:

and distributing a preset initial value and the first-stage sub data to be processed to a j-th-stage CRC calculation module to obtain a first CRC calculation result corresponding to the first-stage sub data to be processed.

Optionally, the target CRC calculation result is determined according to the (i + 1) th CRC calculation result; the allocating unit 530 is further specifically configured to:

if the i +1=N is the i +1 th CRC calculation result, taking the i +1 th CRC calculation result as the target CRC calculation result;

if the i +1<N is determined, the i +1 th CRC calculation result and the i +2 th first-level sub-to-be-processed data are distributed to a j +2 th CRC calculation module to obtain an i +2 th CRC calculation result, and the target CRC calculation result is determined according to the i +2 th CRC calculation result.

Optionally, as shown in fig. 5b, the functional units of another cyclic redundancy check apparatus 500 provided in the embodiment of the present application form a block diagram, where the apparatus 500 further includes: a splicing unit 540;

the splicing unit 540 is configured to splice the target CRC calculation result and the data to be processed to obtain target data.

Optionally, splitting the data to be processed according to the bit width of the data to be processed to obtain N first-level sub-data to be processed; the splitting unit 520 is further specifically configured to:

determining a splitting ratio corresponding to the data to be processed according to the data bit width of each CRC calculation module and the bit width of the data to be processed, wherein the data bit width of each CRC calculation module comprises a theoretical maximum data bit width and an actual maximum data bit width;

and splitting the data to be processed according to the splitting proportion to obtain N first-level sub data to be processed.

Optionally, the allocating unit 530 is further specifically configured to:

in the process of allocating the N first-stage sub-to-be-processed data to the M-stage CRC calculation module, if an actual maximum data bit width corresponding to a P-th-stage CRC calculation module is smaller than a bit width of a kth first-stage sub-to-be-processed data, splitting the kth first-stage sub-to-be-processed data according to the actual maximum data bit width of the P-th-stage CRC calculation module to obtain Q split second-stage sub-to-be-processed data, where P, Q is a positive integer;

distributing the first second-level sub-to-be-processed data in the Q second-level sub-to-be-processed data to the P-level CRC calculation module to obtain a kth CRC calculation result, distributing the kth CRC calculation result and the second-level sub-to-be-processed data to the P + 1-level CRC calculation module to obtain a kth + 1-level CRC calculation result until the Q second-level sub-to-be-processed data are processed by the CRC calculation module to obtain a CRC calculation result corresponding to the kth first-level sub-to-be-processed data; and ki is the CRC calculation result corresponding to one of the Q pieces of second-level sub data to be processed.

Optionally, after obtaining the Q split second-level sub-to-be-processed data, the allocating unit 530 is further specifically configured to:

distributing each second-level sub-to-be-processed data in the Q second-level sub-to-be-processed data distribution to the P-level CRC calculation module to obtain a kth CRC calculation result;

and distributing the kth CRC calculation result and the (k + 1) th first-level sub-to-be-processed data to a (P + 1) th-level CRC calculation module to obtain a (k + 1) th CRC calculation result.

Optionally, the allocating unit 530 is further specifically configured to:

when any one of the first-level sub data to be processed and/or the second-level sub data to be processed is/are distributed to any one of the M-level CRC calculation modules, if the actual maximum data bit width corresponding to the CRC calculation module is greater than the bit width of the first-level sub data to be processed and/or the second-level sub data to be processed, zero padding is performed on the first-level sub data to be processed and/or the second-level sub data to be processed.

It can be understood that the functions of each program module of the cyclic redundancy check device in the embodiments of the present application may be specifically implemented according to the method in the above method embodiments, and the specific implementation process may refer to the description related to the above method embodiments, which is not described herein again.

Embodiments of the present application also provide a computer storage medium, wherein the computer storage medium stores a computer program for electronic data exchange, and the computer program enables a computer to execute part or all of the steps of any one of the methods as described in the above method embodiments.

Embodiments of the present application also provide a computer program product comprising a non-transitory computer readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps of any of the methods as described in the above method embodiments. The computer program product may be a software installation package.

Fig. 6 is a block diagram illustrating a combined processing device 600 according to an embodiment of the present disclosure. As shown in fig. 6, the combined processing device 600 includes a computing processing device 602, an interface device 604, other processing devices 606, and a storage device 608. Depending on the application scenario, one or more computing devices 610 may be included in the computing processing device and may be configured to perform the operations described herein in conjunction with fig. 3a or fig. 4.

In various embodiments, the computing processing device of the present disclosure may be configured to perform user-specified operations. In an exemplary application, the computing processing device may be implemented as a single-core artificial intelligence processor or a multi-core artificial intelligence processor. Similarly, one or more computing devices included within a computing processing device may be implemented as an artificial intelligence processor core or as part of a hardware structure of an artificial intelligence processor core. When multiple computing devices are implemented as artificial intelligence processor cores or as part of a hardware structure of an artificial intelligence processor core, computing processing devices of the present disclosure may be considered to have a single core structure or a homogeneous multi-core structure.

In an exemplary operation, the computing processing device of the present disclosure may interact with other processing devices through an interface device to collectively perform user-specified operations. Other Processing devices of the present disclosure may include one or more types of general and/or special purpose processors, such as Central Processing Units (CPUs), graphics Processing Units (GPUs), and artificial intelligence processors, depending on the implementation. These processors may include, but are not limited to, digital Signal Processors (DSPs), application Specific Integrated Circuits (ASICs), field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic, discrete hardware components, etc., and the number may be determined based on actual needs. As previously mentioned, the computing processing device of the present disclosure may be considered to have a single core structure or an isomorphic multi-core structure only. However, when considered together, a computing processing device and other processing devices may be considered to form a heterogeneous multi-core structure.

In one or more embodiments, the other processing device can interface with external data and controls as a computational processing device of the present disclosure (which can be embodied as an artificial intelligence, e.g., a computing device associated with neural network operations), performing basic controls including, but not limited to, data handling, starting and/or stopping of the computing device, and the like. In further embodiments, other processing devices may also cooperate with the computing processing device to collectively perform computational tasks.

In one or more embodiments, the interface device may be used to transfer data and control instructions between the computing processing device and other processing devices. For example, the computing processing device may obtain input data from other processing devices via the interface device, and write the input data into a storage device (or memory) on the computing processing device. Further, the computing processing device may obtain the control instruction from the other processing device via the interface device, and write the control instruction into the control cache on the computing processing device slice. Alternatively or optionally, the interface device may also read data from the memory device of the computing processing device and transmit the data to the other processing device.

Additionally or alternatively, the combined processing device of the present disclosure may further include a storage device. As shown in the figure, the storage means is connected to the computing processing means and the further processing means, respectively. In one or more embodiments, the storage device may be used to hold data for the computing processing device and/or the other processing devices. For example, the data may be data that is not fully retained within internal or on-chip storage of a computing processing device or other processing device.

In some embodiments, the present disclosure also discloses a neural network chip (e.g., chip 702 shown in fig. 7). In one implementation, the Chip is a System on Chip (SoC) and is integrated with one or more combinatorial processing devices as shown in fig. 6. The chip may be connected to other associated components through an external interface device, such as external interface device 706 shown in fig. 7. The relevant component may be, for example, a camera, a display, a mouse, a keyboard, a network card, or a wifi interface. In some application scenarios, other processing units (e.g., video codecs) and/or interface modules (e.g., DRAM interfaces) and/or the like may be integrated on the chip. In some embodiments, the disclosure also discloses a chip packaging structure, which includes the chip. In some embodiments, the present disclosure also discloses a board card including the above chip packaging structure. The board will be described in detail below with reference to fig. 7.

Fig. 7 is a schematic diagram illustrating a structure of a board card 700 according to an embodiment of the disclosure. As shown in FIG. 7, the board includes a memory device 704 for storing data, which includes one or more memory cells 710. The memory device may be connected and data transferred to and from the control device 708 and the chip 702 as described above, for example, by a bus. Further, the board card further comprises an external interface device 706 configured for data relay or transfer function between the chip (or the chip in the chip package structure) and an external device 712 (e.g. a server or a computer, etc.). For example, the data to be processed may be transferred to the chip by an external device through an external interface means. For another example, the calculation result of the chip may be transmitted back to an external device via the external interface device. According to different application scenarios, the external interface device may have different interface forms, for example, it may adopt a standard PCIE interface or the like.

In one or more embodiments, the control device in the disclosed card may be configured to regulate the state of the chip. Therefore, in an application scenario, the control device may include a single chip Microcomputer (MCU) for controlling the operating state of the chip.

From the above description in conjunction with fig. 6 and 7, it will be understood by those skilled in the art that the present disclosure also discloses an electronic device or apparatus, which may include one or more of the above boards, one or more of the above chips and/or one or more of the above combination processing devices.

According to different application scenarios, the electronic device or apparatus of the present disclosure may include a server, a cloud server, a server cluster, a cyclic redundancy check device, a robot, a computer, a printer, a scanner, a tablet computer, a smart terminal, a PC device, an internet of things terminal, a mobile phone, a vehicle recorder, a navigator, a sensor, a camera, a video camera, a projector, a watch, an earphone, a mobile storage, a wearable device, a visual terminal, an autopilot terminal, a vehicle, a household appliance, and/or a medical device. The vehicle comprises an airplane, a ship and/or a vehicle; the household appliances comprise a television, an air conditioner, a microwave oven, a refrigerator, an electric cooker, a humidifier, a washing machine, an electric lamp, a gas stove and a range hood; the medical equipment comprises a nuclear magnetic resonance apparatus, a B-ultrasonic apparatus and/or an electrocardiograph. The electronic device or apparatus of the present disclosure may also be applied to the fields of the internet, the internet of things, data centers, energy, transportation, public management, manufacturing, education, power grid, telecommunications, finance, retail, construction site, medical, and the like. Further, the electronic device or apparatus disclosed herein may also be used in application scenarios related to artificial intelligence, big data, and/or cloud computing, such as a cloud end, an edge end, and a terminal. In one or more embodiments, a computationally powerful electronic device or apparatus according to the present disclosure may be applied to a cloud device (e.g., a cloud server), while a less power-consuming electronic device or apparatus may be applied to a terminal device and/or an edge-end device (e.g., a smartphone or a camera). In one or more embodiments, the hardware information of the cloud device and the hardware information of the terminal device and/or the edge device are compatible with each other, so that appropriate hardware resources can be matched from the hardware resources of the cloud device to simulate the hardware resources of the terminal device and/or the edge device according to the hardware information of the terminal device and/or the edge device, and uniform management, scheduling and cooperative work of end-cloud integration or cloud-edge-end integration can be completed.

It is noted that for the sake of brevity, the present disclosure describes some methods and embodiments thereof as a series of acts and combinations thereof, but those skilled in the art will appreciate that the aspects of the present disclosure are not limited by the order of the acts described. Accordingly, one of ordinary skill in the art will appreciate that certain steps may be performed in other sequences or simultaneously, in accordance with the disclosure or teachings of the present disclosure. Further, those skilled in the art will appreciate that the embodiments described in this disclosure are capable of alternative embodiments, in that the acts or modules involved are not necessarily required for the implementation of the solution or solutions of the disclosure. In addition, the present disclosure may focus on the description of some embodiments, depending on the solution. In view of the above, those skilled in the art will understand that portions of the disclosure that are not described in detail in one embodiment may also be referred to in the description of other embodiments.

In particular implementation, based on the disclosure and teachings of the present disclosure, one skilled in the art will appreciate that the several embodiments disclosed in the present disclosure may be implemented in other ways not disclosed herein. For example, as for the units in the foregoing embodiments of the electronic device or apparatus, the units are divided based on the logic functions, and there may be other dividing manners in actual implementation. Also for example, multiple units or components may be combined or integrated with another system or some features or functions in a unit or component may be selectively disabled. The connections discussed above in connection with the figures may be direct or indirect couplings between the units or components in terms of connectivity between the different units or components. In some scenarios, the foregoing direct or indirect coupling involves a communication connection utilizing an interface, where the communication interface may support electrical, optical, acoustic, magnetic, or other forms of signal transmission.

In the present disclosure, units described as separate parts may or may not be physically separate, and parts shown as units may or may not be physical units. The aforementioned components or units may be co-located or distributed across multiple network elements. In addition, according to actual needs, part or all of the units can be selected to achieve the purpose of the solution of the embodiment of the present disclosure. In addition, in some scenarios, multiple units in embodiments of the present disclosure may be integrated into one unit or each unit may exist physically separately.

In some implementation scenarios, the integrated units may be implemented in the form of software program modules. If implemented in the form of software program modules and sold or used as a stand-alone product, the integrated units may be stored in a computer readable memory. In this regard, when aspects of the present disclosure are embodied in the form of a software product (e.g., a computer-readable storage medium), the software product may be stored in a memory, which may include instructions for causing a computer device (e.g., a personal computer, a server, or a network device, etc.) to perform some or all of the steps of the methods described in embodiments of the present disclosure. The Memory may include, but is not limited to, a usb disk, a flash disk, a Read Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.

In other implementation scenarios, the integrated unit may also be implemented in hardware, that is, a specific hardware circuit, which may include a digital circuit and/or an analog circuit, etc. The physical implementation of the hardware structure of the circuit may include, but is not limited to, physical devices, which may include, but are not limited to, transistors or memristors, among other devices. In view of this, the various devices described herein (e.g., computing devices or other processing devices) may be implemented by suitable hardware processors, such as CPUs, GPUs, FPGAs, DSPs, ASICs, and the like. Further, the aforementioned storage unit or storage device may be any suitable storage medium (including magnetic storage medium or magneto-optical storage medium, etc.), and may be, for example, a variable Resistive Memory (RRAM), a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), an Enhanced Dynamic Random Access Memory (EDRAM), a High Bandwidth Memory (HBM), a Hybrid Memory Cube (HMC), a ROM, a RAM, or the like.

The foregoing may be better understood in light of the following clauses:

clause a1. A cyclic redundancy check method, applied to a cyclic redundancy check system, the cyclic redundancy check system includes an M-level CRC calculation module, M being a positive integer; the method comprises the following steps:

acquiring data to be processed;

splitting the data to be processed according to the bit width of the data to be processed to obtain N first-level sub-data to be processed, wherein N is a positive integer;

and distributing the N first-stage sub-to-be-processed data to the M-stage CRC calculation module to obtain a target CRC calculation result corresponding to the to-be-processed data.

A2. According to the method described in A1, the allocating the N first-level sub-to-be-processed data to the M-level CRC calculation module to obtain a target CRC calculation result corresponding to the to-be-processed data includes:

A3. The method according to A2, when i =1, further comprising:

A4. The method according to A2, wherein the determining the target CRC calculation result according to the i +1 th CRC calculation result includes:

if the i +1<N is the target CRC calculation result, allocating the i +1 th CRC calculation result and the i +2 th first-level sub-to-be-processed data to a j + 2-level CRC calculation module to obtain an i +2 th CRC calculation result, and determining the target CRC calculation result according to the i +2 th CRC calculation result.

A5. The method according to any one of A1-A4, further comprising:

and splicing the target CRC calculation result with the data to be processed to obtain target data.

A6. According to the method described in A1, splitting the data to be processed according to the bit width of the data to be processed to obtain N first-level sub-data to be processed includes:

determining a splitting ratio corresponding to the data to be processed according to the data bit width of each CRC calculation module and the bit width of the data to be processed, wherein the data bit width of the CRC calculation module comprises a theoretical maximum data bit width and an actual maximum data bit width;

A7. According to the method described in A1 or A6, the bit width of each first-level sub-pending data is the same or different.

A8. The method according to A1 or A6, further comprising:

A9. According to the method described in A8, after the obtaining of the Q split second-level sub-to-be-processed data, the method further includes:

A10. The method according to A8, further comprising:

A11. A cyclic redundancy check device is applied to a cyclic redundancy check system, wherein the cyclic redundancy check system comprises an M-level CRC calculation module, and M is a positive integer; the method comprises the following steps:

the acquisition unit is used for acquiring data to be processed;

A12. According to the apparatus described in a11, the allocating unit is specifically configured to allocate the N first-level sub-to-be-processed data to the M-level CRC calculation module to obtain a target CRC calculation result corresponding to the to-be-processed data, and to:

distributing the i CRC calculation results and the (i + 1) th first-stage sub-to-be-processed data to a j +1 th-stage CRC calculation module to obtain an (i + 1) th CRC calculation result;

A13. According to the apparatus described in a12, when i =1, the allocating unit is further specifically configured to:

A14. According to the apparatus described in a13, the target CRC calculation result is determined according to the i +1 th CRC calculation result, and the allocating unit is specifically configured to:

A15. The apparatus according to any one of a11-a14, further comprising a splicing unit, configured to splice the target CRC calculation result with the data to be processed to obtain target data.

A16. According to the apparatus described in a11, the data to be processed is split according to the bit width of the data to be processed, so as to obtain N first-level sub-data to be processed, where the splitting unit is specifically configured to:

A17. According to the apparatus described in A11 or A16, the bit width of each first-level sub-pending data is the same or different.

A18. According to the apparatus described in a17, each first-stage sub-pending data corresponds to one clock cycle.

A19. According to the apparatus of a11 or a16, the allocation unit is further specifically configured to:

distributing a first second-level sub-to-be-processed data in the Q second-level sub-to-be-processed data to the P-level CRC calculation module to obtain a kth CRC calculation result, distributing the kth CRC calculation result and a second-level sub-to-be-processed data to the P + 1-level CRC calculation module to obtain a kth + 1-level CRC calculation result until the Q second-level sub-to-be-processed data are processed by the CRC calculation module to obtain a CRC calculation result corresponding to the kth first-level sub-to-be-processed data; and ki is the CRC calculation result corresponding to one of the Q pieces of second-level sub data to be processed.

A20. According to the apparatus described in a19, after the Q split second-level sub-to-be-processed data are obtained, the allocating unit is further specifically configured to:

A21. According to the apparatus described in a19, the allocating unit is specifically further configured to:

B1. A cyclic redundancy check method is applied to a CRC calculation module; the method comprises the following steps:

and acquiring a preset value, and performing CRC calculation on the first-stage sub data to be processed and the preset value to obtain a CRC calculation result corresponding to the first-stage sub data to be processed, wherein the preset value is a preset initial value or a previous-stage CRC calculation result corresponding to a previous-stage CRC calculation module, and the CRC calculation result is used for determining a target CRC calculation result corresponding to the data to be processed.

C1. A neural network chip comprising instructions for performing the method of any of clauses A1-a11 and B1.

D1. A computer-readable storage medium comprising a computer program stored for data exchange, which computer program, when executed by a processor, implements the method of any of clauses A1-a11 and B1.

E1. An electronic device, comprising:

a processor;

a memory for storing processor-executable instructions;

wherein the processor is configured to invoke the memory-stored instructions to perform the method of any of clauses A1-A11 and B1.

While various embodiments of the present disclosure have been shown and described herein, it will be obvious to those skilled in the art that such embodiments are provided by way of example only. Numerous modifications, changes, and substitutions will occur to those skilled in the art without departing from the spirit and scope of the present disclosure. It should be understood that various alternatives to the embodiments of the disclosure described herein may be employed in practicing the disclosure. It is intended that the following claims define the scope of the disclosure and that equivalents or alternatives within the scope of these claims be covered thereby.

Claims

1. A cyclic redundancy check method is characterized by being applied to a cyclic redundancy check system, wherein the cyclic redundancy check system comprises an M-level CRC calculation module, and M is a positive integer; the method comprises the following steps:

acquiring data to be processed;

2. The method according to claim 1, wherein said allocating the N first-level sub data to be processed to the M-level CRC calculation module to obtain a target CRC calculation result corresponding to the data to be processed comprises:

3. The method of claim 2, wherein when i =1, the method further comprises:

4. The method of claim 2, wherein determining the target CRC calculation based on the (i + 1) th CRC calculation comprises:

5. The method according to any one of claims 1-4, further comprising:

6. The method according to claim 1, wherein the splitting the to-be-processed data according to the bit width of the to-be-processed data to obtain N first-level sub-to-be-processed data includes:

7. The method according to claim 1 or 6, wherein the bit width of each first-level sub-to-be-processed data is the same or different.

8. The method of claim 1 or 6, further comprising:

distributing the first second-level sub-to-be-processed data in the Q second-level sub-to-be-processed data to the P-level CRC calculation module to obtain a ki CRC calculation result, distributing the ki CRC calculation result and the second-level sub-to-be-processed data to the P + 1-level CRC calculation module to obtain a ki + 1-level CRC calculation result until the Q second-level sub-to-be-processed data are processed by the CRC calculation module to obtain a CRC calculation result corresponding to the kth first-level sub-to-be-processed data; and ki is the CRC calculation result corresponding to one of the Q pieces of second-level sub data to be processed.

9. The method of claim 8, wherein after the obtaining the split Q second-level sub-pending data, the method further comprises:

sequentially distributing each second-level sub-to-be-processed data in the Q second-level sub-to-be-processed data distribution to the P-level CRC calculation module to obtain a kth CRC calculation result;

and distributing the kth CRC calculation result and the (k + 1) th first-level sub-to-be-processed data to a P + 1-level CRC calculation module to obtain a (k + 1) th CRC calculation result.

10. The method of claim 8, further comprising:

11. A cyclic redundancy check method is characterized by being applied to a CRC calculation module; the method comprises the following steps:

12. A neural network chip, wherein the neural network chip is configured to perform the method of any one of claims 1-11.

13. A computer-readable storage medium, characterized in that the computer-readable storage medium comprises a computer program stored for data exchange, which computer program, when being executed by a processor, carries out the method according to any one of claims 1-11.