CN115543000A - Over-temperature protection circuit suitable for ultra-low power consumption linear voltage stabilizer - Google Patents
Over-temperature protection circuit suitable for ultra-low power consumption linear voltage stabilizer Download PDFInfo
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- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
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Abstract
The invention discloses an over-temperature protection circuit suitable for an ultra-low power consumption linear voltage stabilizer, which comprises a load detection module, a PTAT voltage generation module and a voltage comparator module, wherein the load detection module is used for detecting the load state of the linear voltage stabilizer, and when the load is zero, the load detection module outputs a control signal to turn off the PTAT voltage generation module and the voltage comparator module so that the over-temperature protection circuit is in a dormant state; when the load is increased, the load detection module outputs a control signal to start the PTAT voltage generation module and the voltage comparator module; the PTAT voltage generation module uses a self-bias current mirror structure to realize real-time detection of temperature, and the output voltage and the temperature are in a direct proportion relation. In order to reduce the problem of overlarge transient current during logic turnover, the over-temperature protection circuit is characterized in that a current-limiting protection circuit consisting of NMOS (N-channel metal oxide semiconductor) depletion resistors is connected in series with the ground end of a logic gate circuit, so that the impact of the transient current on the ultra-low power consumption linear voltage stabilizer is effectively reduced.
Description
Technical Field
The invention relates to the field of linear voltage regulators, in particular to an over-temperature protection circuit suitable for an ultra-low power consumption linear voltage regulator.
Background
The linear voltage regulator is a commonly used power management chip, which cannot work at a high temperature for a long time, and when the local temperature of the chip exceeds a certain upper limit, the PN junction is thermally broken down to cause overcurrent, so that the whole chip is irreversibly damaged. The reason for the local over-high temperature of the chip is that the output current is too large, the heat dissipation of the chip is not good or the local circuit is short-circuited. Therefore, when the temperature is too high, the linear voltage regulator needs to turn off the chip through the over-temperature protection circuit, so that the chip is prevented from being damaged.
Fig. 1 shows a typical structure of an over-temperature protection circuit of a linear regulator, which utilizes the characteristic that the forward bias voltage of a PN junction of a triode is reduced along with the increase of temperature as a function of the temperature and has good consistency, and the over-temperature protection function is realized by comparing the forward bias voltage of the PN junction related to the temperature with a reference voltage.
In fig. 1, vbias is a temperature-independent bias voltage output by a reference source, M1 and M2 are driven to generate bias currents, and the current I1 generates a reference voltage VY through resistors R1 and R2, wherein VY is also temperature-independent. The voltage Vx at point X is the positive turn-on voltage VBE of the PN junction and has negative temperature characteristics. When the voltage regulator works normally, VX is larger than VY, the output of the comparator is 0, vctrl is 1, the M3 tube is conducted, R2 is short-circuited, and the reference voltage is VY = I1 × R1; when the temperature rises, the voltage VX is reduced, when the maximum value of the limited temperature is reached, VX is smaller than VY, the output of the comparator is 1, vctrl is 0, the M3 tube is turned off, the reference voltage is increased to VY' = I1 (R1 + R2), over-temperature protection is carried out, the power tube of the linear voltage stabilizer is turned off, no output current exists, and the comparator can be turned over when the temperature is required to be reduced to a point lower than the maximum value at the moment, so that the linear voltage stabilizer returns to a normal working state.
The circuit structure uses a double-end input comparator and a normally-on bias circuit, and needs to consume a certain current, so that the circuit structure cannot be applied to a mu A-level static current ultra-low power consumption linear voltage regulator.
Disclosure of Invention
The invention aims to: in order to solve the above problems, the present invention provides an over-temperature protection circuit suitable for an ultra-low power consumption linear voltage regulator.
The technical scheme of the invention is as follows:
an over-temperature protection circuit suitable for an ultra-low power consumption linear voltage regulator comprises a load detection module, a PTAT voltage generation module and a voltage comparator module, wherein:
the load detection module is used for detecting the load state of the linear voltage stabilizer, and when the load is zero, the load detection module outputs a control signal to turn off the PTAT voltage generation module and the voltage comparator module so that the over-temperature protection circuit is in a dormant state; when the load is increased, the load detection module outputs a control signal to start the PTAT voltage generation module and the voltage comparator module, and the temperature of the voltage stabilizer is monitored to realize the function of over-temperature protection;
the PTAT voltage generation module uses a self-bias current mirror structure to realize real-time detection of temperature, and the output voltage and the temperature are in a direct proportional relation;
the voltage comparator adopts a triode single-end input structure, and the threshold voltage of the comparator is equal to the BE junction starting voltage of the NPN triode.
Preferably, the linear voltage regulator comprises a band gap reference module, a high-voltage pre-modulation module, an error amplifier, an over-temperature protection circuit, a power tube and a feedback resistance network; wherein:
the high-voltage pre-modulation module converts a high-voltage input power supply VDD _ H into a low-voltage power supply VDD _ L which is weakly related to the input power supply and supplies power to the error amplifier pre-amplification stage and the over-temperature protection circuit;
the error amplifier comprises a preposed amplification stage EA1 and an output drive stage MN1 which are connected in sequence; the branch circuit of the output drive stage MN1 is connected with a feedback resistance network for controlling the on-off of the power tube MP;
the gap reference module and the feedback resistance network are respectively connected with two-phase input ends of the preposed amplification stage EA 1;
the over-temperature protection circuit is connected between the pre-amplification stage and the output driving stage of the error amplifier, and the load condition of the linear voltage regulator is judged by sampling the grid voltage of the input tube MN1 of the output driving stage.
Preferably, the load detection module comprises MOS transistors M20, M21, M22, M23, M24, inverters INV1, INV2, INV3, and a NAND gate NAND;
the MOS tubes M22, M23 and M20 are sequentially connected in series between a low-voltage power supply VDD _ L and VSS, the grids of M20 and M21 are connected with a grid voltage EA _ O1 of MN1, the source electrode of M21 is connected with VSS, the drain electrode is connected with the drain electrode of M20 through M24, the drain electrode of M20 is also connected with the input end of an inverter INV1, the grid electrode of M24 is connected with the output end of the inverter INV1, and the output end of INV1 is connected with the input end of INV 2; the output end of INV2 and the output end OTP _ ctrn of the voltage comparator are respectively connected with two input ends of the NAND gate NAND, the output end enb of the NAND gate NAND is connected with the input end of the inverter INV3, and the output end of INV3 generates an enable signal en.
Preferably, the PTAT voltage generating module consists of a temperature detection circuit and a starting circuit; the temperature detection circuit comprises a current mirror self-bias circuit and a current mirror copy circuit; the current mirror self-bias circuit generates a current IPTAT which is in direct proportion to absolute temperature; the current mirror copy circuit copies IPTAT current in proportion and generates voltage VPTAT which is in direct proportion to temperature after the IPTAT current flows through a resistor, and real-time monitoring of the temperature is achieved; the starting circuit is used for preventing the PTAT voltage generating module from being in a degenerate state when the PTAT voltage generating module is enabled to be started.
Preferably, the current mirror self-bias circuit of the temperature detection circuit comprises three transistors Q1 and Q2, a resistor R1 and PMOS transistors M1 and M2; the current mirror copy circuit comprises a PMOS tube M3 and resistors R2 and R3; the base electrodes of the transistors Q1 and Q2 are connected in common, the grid electrodes of the PMOS transistors M1, M2 and M3 are connected in common, the PMOS transistor M1, the transistor Q1 and the resistor R1 are sequentially connected in series between a low-voltage power supply VDD _ L and VSS, and the PMOS transistor M2 and the transistor Q2 are sequentially connected in series between the low-voltage power supply VDD _ L and VSS; the PMOS tube M3 and the resistors R2 and R3 are sequentially connected in series between the low-voltage power supply VDD _ L and VSS.
Preferably, the starting circuit comprises M9, M10, M11, M12, M13, M14 and a capacitor C1; when the enable is just turned on, the gate voltage of M13 is high, the gate voltages of M11 and M12 are low, and the gate voltage of M14 is also low, so that the gate voltage of M10 is high and the NMOS transistor M10 is turned on. Because the M9 tube is a depletion tube and the threshold voltage is less than 0, the M9 tube branch and the M10 tube branch generate current to charge the capacitor C1, so that the grid voltage of the M1 is pulled down, and the current mirror starts to work after the self-bias circuit is separated from a degenerate state.
Preferably, after the current mirror self-bias circuit is started, the gate voltage of M13 is low, the gate voltages of M11 and M12 are high, and since the width-to-length ratio of M11 is much greater than the width-to-length ratio of M14, the gate voltage of M10 is low, the M10 transistor is turned off, the branch currents of M9 and M10 are zero, and the operation of the current mirror self-bias circuit is not affected.
The invention has the advantages that:
in order to solve the problem of overlarge transient current during logic turnover, the over-temperature protection circuit of the ultra-low power consumption linear voltage stabilizer is characterized in that a current-limiting protection circuit consisting of NMOS (N-channel metal oxide semiconductor) depletion resistors is connected in series with the ground end of a logic gate circuit, so that the impact of the transient current on the ultra-low power consumption linear voltage stabilizer is effectively reduced.
Drawings
The invention is further described with reference to the following figures and examples:
FIG. 1 is a typical linear regulator over-temperature protection circuit configuration;
FIG. 2 is a schematic block diagram of an ultra-low power consumption linear regulator with over-temperature protection according to the present invention;
FIG. 3 is a block diagram of an over-temperature protection circuit for an ultra-low power linear regulator according to the present invention;
FIG. 4 is an inverter with an NMOS depletion transistor current limiting circuit according to the present invention;
FIG. 5 shows a NAND gate with NMOS depletion transistor current limiting circuit according to the present invention;
FIG. 6 is a comparison graph of the transient current simulation of an inverter with an infinite tube according to the present invention;
FIG. 7 shows the over-temperature protection simulation result of the linear regulator with 1mA load according to the present invention;
fig. 8 is a simulation result of the linear regulator over-temperature protection switching-on process under different load conditions according to the present invention.
Detailed Description
As shown in fig. 2, the ultra-low power consumption linear regulator with over-temperature protection according to the present invention has a schematic block diagram, and the linear regulator mainly includes a bandgap reference, a high voltage pre-modulation, an error amplifier, an over-temperature protection, a power tube, a feedback resistor network, and other modules.
The ultra-low power consumption linear voltage stabilizer supports wide-range input voltage, a high-voltage pre-modulation module is used for converting a high-voltage input power supply VDD _ H into a low-voltage power supply VDD _ L which is weakly related to the input power supply, and power is supplied to modules such as a pre-amplification stage of an error amplifier, over-temperature protection and the like.
The error amplifier is composed of a preamplifier stage EA1 and an output driver stage MN1 branch. The pre-amplifier stage is powered by a low-voltage power supply so as to utilize the superior performance of a low-voltage MOS tube; the input tube MN1 of the output driver stage is still a low voltage tube, and the bias current Ib is generated by a high voltage tube, so that a wide output range can be realized to better drive the gate of the high voltage power tube MP.
The over-temperature protection module is located between a pre-amplification stage and an output driving stage of the error amplifier, and the load condition of the linear voltage stabilizer is judged by sampling the grid voltage of an input tube MN1 of the output driving stage. Because the MOS tube works in the subthreshold region when the micro-power linear voltage stabilizer is in a static state, when the load is zero or light, the grid voltage EA _ O1 of MN1 is very low, the load detection module in the over-temperature protection module generates an enable signal en =1, the PTAT voltage module and the voltage comparator module are turned off, and the static power consumption is reduced. When the load is increased, MN1 works in a saturation region, the gate voltage EA _ O1 of MN is increased, the load detection module in the over-temperature protection module generates an enable signal en =0, the PTAT voltage module and the voltage comparator module start to work, and the detection of the temperature of the chip is realized. When the junction temperature of the chip exceeds a certain threshold voltage, the voltage comparator outputs a high level to pull the grid voltage of the MN1 to the ground, so that the power tube MP is turned off, and the function of over-temperature protection is realized.
Fig. 3 is a structural diagram of an over-temperature protection circuit suitable for an ultra-low power consumption linear voltage regulator according to the present invention, which mainly comprises a load detection module, a PTAT voltage generation module, and a voltage comparator module, and is powered by a low voltage power supply VDD _ L.
The load detection module is mainly used for detecting the load state of the linear voltage regulator. When the load of the linear regulator is zero, EA _ O1 voltage is very low, M20 drain outputs high level, and then inverter INV1 outputs low level, and similarly INV2 outputs high level. Therefore, one input of the NAND gate is high, the other input of the NAND gate is connected to the output OTP _ ctrn of the voltage comparator, and the OTP _ ctrn is high when the NAND gate is just powered on or no over-temperature phenomenon occurs, so the NAND output is low, i.e., enb = "0" and en = "1". At this time, under the action of the pull-down tubes M15, M16 and M17 and the pull-up tubes M18 and M19, the PTAT voltage generation module and the voltage comparator module are forcibly turned off, so that the static power consumption of the linear voltage regulator is reduced.
When the load of the linear voltage regulator is gradually increased, the voltage of EA _ O1 is gradually increased, the voltage of the drain of M20 is gradually decreased, the output of INV1 is gradually increased until the M24 transistor is turned on to form a positive feedback, the drain voltage of M20 is rapidly pulled to the ground, the output of INV1 is high, INV2 is low, the NAND gate NAND outputs high level, that is, enb = '1' and en = '0', at this time, the pull-down transistor and the pull-up transistor are both turned off, and the PTAT voltage generation module and the voltage comparator module start to work.
Because logic circuits such as an inverter, a nand gate and the like have relatively large transient current when the level is inverted, large impact is caused on a low-voltage power supply VDD _ L, and the normal operation of a power supply circuit of the logic circuits is affected, so that the transient current of the logic circuits needs to be reduced. The current limiting circuit composed of NMOS dissipative capacitors is adopted in the circuit to realize the function, namely, the current limiting circuit composed of NMOS dissipative capacitors is connected in series at the end to the ground of the logic circuit, as shown in figures 4 and 5. Since the drain-source voltage of the NMOS is fixed, neglecting the channel length modulation effect, when the source-drain voltage is larger than the gate-source voltage minus the threshold voltage, the drain-source current flowing through the NMOS remains unchanged.
Fig. 6 shows the simulation result of the transient current of the inverter with and without the NMOS depletion transistor current limiting circuit according to the present invention, which shows that the current limiting circuit composed of NMOS depletion transistors can greatly reduce the transient current of the logic circuit, and improve the stability of the internal power supply.
The PTAT voltage generating module consists of a temperature detection circuit and a starting circuit.
The temperature detection circuit comprises a current mirror self-bias circuit and a current mirror copy circuit. The current mirror self-bias circuit consists of three-level transistors Q1 and Q2, a resistor R1 and PMOS transistors M1 and M2, and mainly generates current IPTAT which is in direct proportion to absolute temperature. The current mirror image copying circuit comprises a PMOS (P-channel metal oxide semiconductor) tube M3 and resistors R2 and R3, wherein the M3 tube copies IPTAT current in proportion and generates voltage VPTAT which is in direct proportion to temperature after flowing through the resistors, so that the real-time monitoring of the temperature is realized.
Since the width-to-length ratio of M1 and M2 is 1, the collector currents of the transistors Q1 and Q2 are equal, and the area ratio of Q1 to Q2 is n:1, the base and emitter voltages of Q1 and Q2 can be expressed as:
wherein, I c Represents the collector current of Q1 and Q2; v T = kTq is thermal voltage, proportional to absolute temperature, k is boltzmann constant, T is thermodynamic temperature, q is unit charge amount; n is the area ratio of Q1 to Q2; i is s Is a triode saturation current constant.
Then the drain current through M1, M2 is equal to the current through resistor R1, which can be expressed as:
from equation (3), the drain currents of M1 and M2 are proportional to the thermodynamic temperature T, and are therefore also referred to as PTAT currents. And because the width-length ratio of the M3 tube and the width-length ratio of the M1 tube to the M2 tube are M:1:
when the temperature is low, the collector output voltage OTP _ ctrn of Q3 is high, the control switch M5 is turned on, the resistor R3 is short-circuited, and therefore the drain voltage of M3 is equal to:
according to the above formula, V temp The voltage has a linear relationship with the thermodynamic temperature and has a positive temperature coefficient, so the voltage can be used for representing the temperature of the chip.
The drain output voltage of M3 is applied to the base of Q3 as the input voltage of the voltage comparator. The voltage comparator comprises a single-ended input comparator consisting of Q3 and M4 and an inverter INV4.
When the temperature is lower, V temp The voltage is lower than the starting voltage of the triode Q3, the Q3 tube is cut off, the OTP _ ctrn output by the comparator is high, and the OTP _ ctr output by the inverter is low.
When the temperature gradually rises, V temp When the voltage is larger than the starting voltage of the triode Q3, the Q3 tube is conducted, the OTP _ ctrn output by the comparator becomes low, the OTP _ ctrn output by the inverter becomes high, and the linear voltage stabilizer MN2 tube is controlled to be conducted and pulled down, so that the power tube MP is further turned off. And meanwhile, the OTP _ ctrn is fed back and input to the input end of the NAND gate in the load detection module, and the en voltage is further locked to be kept low, so that the situation that the load becomes zero at the moment to cause the error turn-off of the over-temperature protection module is prevented.
Suppose the turn-on voltage of transistor Q3 is equal to V th When the temperature is changed from low to high, the opening threshold temperature of the over-temperature protection module is easily calculated by the formula (5) as follows:
after over-temperature protection, OTP _ ctrn becomes low, M5 tube is disconnected, and V temp The voltage becomes instantaneously large, equal to:
after the over-temperature protection occurs, the power tube is turned off, the temperature of the chip is gradually reduced, and when V is temp When the voltage drops below the turn-on voltage of Q3, OTP _ ctrn goes high, OTP _ ctr goes low, and the power circuit resumes operation. And (7) calculating the threshold temperature of the turn-off of the over-temperature protection module by combining the formula:
comparing the formula (6) with the formula (8), it can be known that the opening threshold temperature of the over-temperature protection is greater than the closing threshold temperature, and a certain hysteresis interval is reserved to prevent the thermal oscillation phenomenon near the opening threshold temperature.
From the above analysis, it is known that the PTAT voltage generation module may be in the enable on and off states at any time, and the start-up circuit is necessary to prevent the circuit from being in the degenerate state when the enable on. The starting circuit is composed of M9, M10, M11, M12, M13 and M14 and a capacitor C1.
When the enable is just turned on, the gate voltage of M13 is high, the gate voltages of M11 and M12 are low, and the gate voltage of M14 is also low, so that the gate voltage of M10 is high and the NMOS transistor M10 is turned on. Because the M9 tube is a depletion tube and the threshold voltage is less than 0, the M9 tube branch and the M10 tube branch generate current to charge the capacitor C1, so that the grid voltage of the M1 is pulled down, and the current mirror starts to work after the self-bias circuit is separated from a degenerate state.
After the current mirror self-bias circuit is started, the grid voltage of M13 is lowered, the grid voltages of M11 and M12 are raised, and the width-to-length ratio of M11 is far greater than that of M14, so that the grid voltage of M10 is lowered, the M10 tube is cut off, the branch currents of M9 and M10 are zero, and the work of the current mirror self-bias circuit is not influenced.
FIG. 7 shows the simulation result of the over-temperature protection of the linear regulator with 1mA load, which shows that when the temperature is higher than 165 ℃, the over-temperature protection is turned on to turn off the power tube; when the temperature is lower than 154 ℃ again, the over-temperature protection is closed, and the power tube starts to work again. Fig. 8 shows simulation results of the linear regulator over-temperature protection starting process under different load conditions, and it can be known from the figure that when the load current is less than 10 μ a, the over-temperature protection module is in a sleep state, so as to reduce the power consumption of the system, and at this time, the circuit has no over-temperature protection function.
The above embodiments are merely illustrative of the technical ideas and features of the present invention, and the purpose of the embodiments is to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and not to limit the protection scope of the present invention. All modifications made according to the spirit of the main technical scheme of the invention are covered in the protection scope of the invention.
Claims (7)
1. An over-temperature protection circuit suitable for an ultra-low power consumption linear voltage regulator is characterized by comprising a load detection module, a PTAT voltage generation module and a voltage comparator module, wherein:
the load detection module is used for detecting the load state of the linear voltage stabilizer, and when the load is zero, the load detection module outputs a control signal to turn off the PTAT voltage generation module and the voltage comparator module so that the over-temperature protection circuit is in a dormant state; when the load is increased, the load detection module outputs a control signal to start the PTAT voltage generation module and the voltage comparator module, and the temperature of the voltage stabilizer is monitored to realize the over-temperature protection function;
the PTAT voltage generation module uses a self-bias current mirror structure to realize real-time detection of temperature, and the output voltage and the temperature are in a direct proportional relation;
the voltage comparator adopts a triode single-end input structure, and the threshold voltage of the comparator is equal to the BE junction starting voltage of the NPN triode.
2. The over-temperature protection circuit suitable for the ultra-low power consumption linear voltage regulator according to claim 1, wherein the linear voltage regulator comprises a band gap reference module, a high-voltage pre-modulation module, an error amplifier, an over-temperature protection circuit, a power tube and a feedback resistance network; wherein:
the high-voltage pre-modulation module converts a high-voltage input power supply VDD _ H into a low-voltage power supply VDD _ L which is weakly related to the input power supply, and supplies power to the pre-amplification stage of the error amplifier and the over-temperature protection circuit;
the error amplifier comprises a preposed amplification stage EA1 and an output drive stage MN1 which are sequentially connected; the branch circuit of the output drive stage MN1 is connected with a feedback resistance network for controlling the on-off of the power tube MP;
the gap reference module and the feedback resistance network are respectively connected with two-phase input ends of the preamplifier EA 1;
the over-temperature protection circuit is connected between the pre-amplification stage and the output driving stage of the error amplifier, and the load condition of the linear voltage stabilizer is judged by sampling the grid voltage of the input tube MN1 of the output driving stage.
3. The over-temperature protection circuit suitable for the ultra-low power consumption linear voltage regulator according to claim 2, wherein the load detection module comprises MOS transistors M20, M21, M22, M23, M24, inverters INV1, INV2, INV3 and an NAND gate NAND;
the MOS tubes M22, M23 and M20 are sequentially connected in series between a low-voltage power supply VDD _ L and VSS, the grids of M20 and M21 are connected with a grid voltage EA _ O1 of MN1, the source electrode of M21 is connected with VSS, the drain electrode is connected with the drain electrode of M20 through M24, the drain electrode of M20 is also connected with the input end of an inverter INV1, the grid electrode of M24 is connected with the output end of the inverter INV1, and the output end of INV1 is connected with the input end of INV 2; the output end of INV2 and the output end OTP _ ctrn of the voltage comparator are respectively connected with two input ends of the NAND gate NAND, the output end enb of the NAND gate NAND is connected with the input end of the inverter INV3, and the output end of INV3 generates an enable signal en.
4. The over-temperature protection circuit suitable for the ultra-low power consumption linear voltage regulator according to claim 2, wherein the PTAT voltage generating module is composed of a temperature detection circuit and a starting circuit; the temperature detection circuit comprises a current mirror self-bias circuit and a current mirror copy circuit; the current mirror self-bias circuit generates a current IPTAT which is in direct proportion to absolute temperature; the current mirror copy circuit copies IPTAT current in proportion and generates voltage VPTAT which is in direct proportion to temperature after the IPTAT current flows through a resistor, and real-time monitoring of the temperature is achieved; the starting circuit is used for preventing the PTAT voltage generating module from being in a degenerate state when the PTAT voltage generating module is enabled to be started.
5. The over-temperature protection circuit suitable for the ultra-low power consumption linear voltage regulator according to claim 4, wherein the current mirror self-bias circuit of the temperature detection circuit comprises a triode Q1, Q2, a resistor R1 and a PMOS (P-channel metal oxide semiconductor) transistor M1, M2; the current mirror copy circuit comprises a PMOS tube M3 and resistors R2 and R3; the base electrodes of the transistors Q1 and Q2 are connected in common, the grid electrodes of the PMOS transistors M1, M2 and M3 are connected in common, the PMOS transistor M1, the transistor Q1 and the resistor R1 are sequentially connected in series between a low-voltage power supply VDD _ L and VSS, and the PMOS transistor M2 and the transistor Q2 are sequentially connected in series between the low-voltage power supply VDD _ L and VSS; the PMOS tube M3 and the resistors R2 and R3 are sequentially connected in series between the low-voltage power supply VDD _ L and VSS.
6. The over-temperature protection circuit suitable for the ultra-low power consumption linear voltage regulator according to claim 5, wherein the starting circuit comprises M9, M10, M11, M12, M13, M14 and a capacitor C1; when the enable is just turned on, the gate voltage of M13 is high, the gate voltages of M11 and M12 are low, and the gate voltage en of M14 is also low, so that the gate voltage of M10 is high, and the NMOS transistor M10 is turned on;
because the M9 tube is a depletion tube and the threshold voltage is less than 0, the M9 tube branch and the M10 tube branch generate current to charge the capacitor C1, so that the grid voltage of the M1 is reduced, and the current mirror starts to work after the bias circuit is separated from a degenerate state.
7. The over-temperature protection circuit suitable for the ultra-low power consumption linear voltage regulator according to claim 6, wherein after the current mirror self-bias circuit is started, the gate voltage of M13 is lowered, the gate voltages of M11 and M12 are raised, and since the width-to-length ratio of M11 is much greater than that of M14, the gate voltage of M10 is lowered, the M10 transistor is turned off, and the current of the M9 and M10 branches is zero, which does not affect the operation of the current mirror self-bias circuit.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116298481A (en) * | 2023-05-18 | 2023-06-23 | 无锡力芯微电子股份有限公司 | Ultra-low power consumption overvoltage detection circuit |
| CN116436418A (en) * | 2023-06-09 | 2023-07-14 | 尚睿微电子（上海）有限公司 | Protection circuit and amplifying circuit |
| CN116795167A (en) * | 2023-08-29 | 2023-09-22 | 厦门优迅高速芯片有限公司 | Current mirror structure circuit and method for realizing low-voltage input work |
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2022
- 2022-09-30 CN CN202211211117.5A patent/CN115543000A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116298481A (en) * | 2023-05-18 | 2023-06-23 | 无锡力芯微电子股份有限公司 | Ultra-low power consumption overvoltage detection circuit |
| CN116298481B (en) * | 2023-05-18 | 2023-08-15 | 无锡力芯微电子股份有限公司 | Ultra-low power consumption overvoltage detection circuit |
| CN116436418A (en) * | 2023-06-09 | 2023-07-14 | 尚睿微电子（上海）有限公司 | Protection circuit and amplifying circuit |
| CN116436418B (en) * | 2023-06-09 | 2023-09-08 | 尚睿微电子（上海）有限公司 | Protection circuit and amplifying circuit |
| CN116795167A (en) * | 2023-08-29 | 2023-09-22 | 厦门优迅高速芯片有限公司 | Current mirror structure circuit and method for realizing low-voltage input work |
| CN116795167B (en) * | 2023-08-29 | 2023-11-21 | 厦门优迅高速芯片有限公司 | Current mirror structure circuit and method for realizing low-voltage input work |
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