CN115528896A - Control method and structure of interleaved parallel topology and AC/DC power supply - Google Patents

Control method and structure of interleaved parallel topology and AC/DC power supply Download PDF

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Publication number
CN115528896A
CN115528896A CN202211496058.0A CN202211496058A CN115528896A CN 115528896 A CN115528896 A CN 115528896A CN 202211496058 A CN202211496058 A CN 202211496058A CN 115528896 A CN115528896 A CN 115528896A
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fast switching
controlling
switching tube
period
path
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CN202211496058.0A
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CN115528896B (en
Inventor
谭果
黄柱
何乔
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Shenzhen Lorentz Technology Co ltd
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Shenzhen Lorentz Technology Co ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/12—Arrangements for reducing harmonics from ac input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H02M1/4208—Arrangements for improving power factor of AC input
    • H02M1/4233—Arrangements for improving power factor of AC input using a bridge converter comprising active switches
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M7/2173—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a biphase or polyphase circuit arrangement
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M7/219—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Rectifiers (AREA)

Abstract

The invention relates to the technical field of power supply design, and particularly discloses a control method and a control structure of a staggered parallel topology and an AC/DC power supply, wherein the structure comprises a controller and a main circuit, the main circuit comprises an inductor, a first bridge arm circuit and a second bridge arm circuit, the first bridge arm circuit comprises a preset number of paths, a middle node of each path is connected to one end of an alternating current power supply through the inductor, a middle node of the second bridge arm circuit is connected to the other end of the alternating current power supply, and the method comprises the following steps: and controlling each slow switch tube in the second bridge arm circuit to be alternately conducted according to the state of the output voltage of the alternating current power supply, and sequentially controlling each fast switch tube in the access to be alternately conducted according to a preset switch period during the conduction period of any one slow switch tube. According to the embodiment of the invention, on the premise of not increasing the inductance, only one fast switching tube is controlled to be conducted at any time in the preset switching period, so that the ripple of the current in the alternating current input is reduced, and the power density of the power supply is improved.

Description

Control method and structure of interleaved parallel topology and AC/DC power supply
Technical Field
The invention relates to the technical field of power supplies, in particular to a control method and a structure of a staggered parallel topology and an AC/DC power supply.
Background
At present, with the development of power electronics technology becoming more and more rapid, the miniaturization and high power density of electronic devices have become the manifestation of product competitiveness and the technical level. Among them, the power factor correction technology has been widely applied to power electronics as an effective means for improving the quality of electric energy.
With the application of high Power electronic devices, the demand for high Power is increasing, and the conventional PFC (Power Factor Correction) is difficult to implement the high Power design, so the prior art usually adopts the staggered parallel PFC topology structure to solve the above problems. However, in the control method of the interleaved parallel topology in the prior art, the performance of the power supply is generally improved by increasing the number of topology paths, but the number of inductors is also increased correspondingly, so that the volume of the circuit is increased, and the power density of the power supply is deteriorated.
Therefore, how to increase the power density of the power supply on the basis of ensuring the performance of the power supply is a technical problem to be solved urgently in the field.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a control method and a structure of an interleaved parallel topology and an AC/DC power supply, so as to improve the power density of the power supply on the basis of reducing the ripple of current during AC input.
In order to achieve the above object, the embodiments of the present invention adopt the following technical solutions:
in a first aspect, an embodiment of the present invention provides a control method for an interleaved parallel topology, which is applied to the interleaved parallel topology, where the interleaved parallel topology includes a controller and a main circuit, the main circuit includes an inductor, a first bridge arm circuit and a second bridge arm circuit, the first bridge arm circuit includes a preset number of paths, and intermediate nodes of the paths are connected with each other, where each path includes at least two fast switching tubes connected in series, the intermediate node of each path is used for accessing one end of an ac power supply through the inductor, and the intermediate node of the second bridge arm circuit is used for accessing the other end of the ac power supply, and the method includes:
and controlling each slow switching tube in the second bridge arm circuit to be alternately conducted according to the state of the output voltage of the alternating current power supply, and sequentially controlling each fast switching tube in the passage to be alternately conducted according to a preset switching period during the conduction period of any one slow switching tube.
In one embodiment, one end of the inductor is used for connecting the middle node of each of the paths, the other end of the inductor is used for accessing one end of the ac power supply, and the other end of the ac power supply is used for accessing the middle node of the second bridge arm circuit, and the method further includes:
and determining the state of the inductor according to the conduction state of each fast switching tube and each slow switching tube at the current moment, wherein the state of the inductor comprises a charging state and a discharging state.
In one embodiment, the controlling of the slow switching tubes in the second bridge arm circuit according to the state of the output voltage of the ac power supply to be alternately turned on includes:
when the state of the output voltage is in a negative half cycle, controlling the first slow switching tube to be conducted and controlling the second slow switching tube to be switched off;
and when the state of the output voltage is in a positive half cycle, controlling the second slow switching tube to be switched on and controlling the first slow switching tube to be switched off.
In one embodiment, the dividing the preset switching period into a plurality of sub-periods with the same number as the preset number, and sequentially controlling each fast switching tube in the path to be alternately turned on according to the preset switching period includes:
and sequentially controlling each fast switching tube of only one path to be alternately conducted in any sub-period of the preset switching period.
In one embodiment, the first bridge arm circuit includes a first path and a second path, the first path and the second path each include two fast switching tubes, the preset switching period includes a first sub-period and a second sub-period, and the sequentially controlling that each fast switching tube of only one of the paths is alternately turned on in any one of the sub-periods of the preset switching period includes:
in the first sub-period, controlling two fast switching tubes in the first path to be alternately switched on, and controlling two fast switching tubes in the second path to be switched off;
and in the second sub-period, controlling the two fast switching tubes in the second passage to be alternately switched on, and controlling the two fast switching tubes in the first passage to be switched off.
In one embodiment, each of the sub-cycles is divided into a number of time periods equal to the number of fast switching transistors in the path, the first path includes a first fast switching transistor and a second fast switching transistor, the second path includes a third fast switching transistor and a fourth fast switching transistor, and the controlling of the two fast switching transistors in the first path to be alternately turned on and the two fast switching transistors in the second path to be turned off in the first sub-cycle includes:
in a first time period of the first sub-cycle, controlling the first fast switching tube to be switched on, and switching off the second fast switching tube, the third fast switching tube and the fourth fast switching tube;
in a second time period of the first sub-cycle, controlling the second fast switching tube to be switched on, and switching off the first fast switching tube, the third fast switching tube and the fourth fast switching tube;
in the second sub-period, controlling the two fast switching tubes in the second path to be alternately turned on, and controlling the two fast switching tubes in the first path to be turned off, including:
controlling the third fast switching tube to be switched on in a first time period of the second sub-period, and switching off the first fast switching tube, the second fast switching tube and the fourth fast switching tube;
and in a second time period of the second sub-period, controlling the fourth fast switching tube to be switched on, and switching off the first fast switching tube, the second fast switching tube and the third fast switching tube.
In one embodiment, the preset switching period is equal to the inverse of the product of the preset number and the switching frequency of the fast switching tube.
In a second aspect, an embodiment of the present invention provides an interleaved parallel topology, where the structure includes: the controller comprises a main circuit, wherein the main circuit comprises an inductor, a first bridge arm circuit and a second bridge arm circuit, the first bridge arm circuit comprises a preset number of paths, and intermediate nodes of the paths are connected with each other, each path comprises at least two rapid switching tubes connected in series, the intermediate node of each path is connected with one end of the inductor, the other end of the inductor is connected with one end of an alternating current power supply, the other end of the alternating current power supply is connected with the intermediate node of the second bridge arm circuit, and the controller is used for executing the control method to control the first bridge arm circuit and the second bridge arm circuit.
In one embodiment, the interleaved parallel topology includes any one of a bidirectional totem pole PFC topology, a three-phase vienna PFC topology, a three-phase three-level T-topology, and a three-phase three-level I-topology.
In a third aspect, an embodiment of the present invention further provides an AC/DC power supply, where the power supply includes any one of the interleaved parallel topologies described above.
The embodiment of the invention provides a control method and a control structure of a staggered parallel topological structure and an AC/DC power supply, wherein the method comprises the following steps: and controlling each slow switch tube in the second bridge arm circuit to be alternately conducted according to the state of the output voltage of the alternating current power supply, and sequentially controlling each fast switch tube in the access to be alternately conducted according to a preset switch period during the conduction period of any one slow switch tube. Compared with the prior art, the staggered parallel topology structure of the embodiment of the invention only uses one inductor, the middle nodes of all the channels are connected with each other and are all connected with the inductor, meanwhile, the slow switching tube is controlled according to the state of the alternating current power supply, and only one fast switching tube is controlled to be conducted at any time in the preset switching period, so that the number of the channels is increased without increasing the number of the corresponding inductors, and the power density of the power supply is improved on the basis of reducing the ripple wave of the current during alternating current input.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings required to be used in the embodiments will be briefly described below, and it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope of the present invention. Like components are numbered similarly in the various figures.
FIG. 1 is a block diagram illustrating an interleaved parallel topology according to an embodiment of the present invention;
FIG. 2 is a flow chart showing a control process in one preset switching period according to an embodiment of the present invention;
FIG. 3 illustrates a circuit schematic of an interleaved parallel topology in an embodiment of the present invention;
fig. 4 shows a waveform diagram for controlling an interleaved parallel topology in an embodiment of the invention.
Description of the main element symbols:
10-a controller, 11-a main circuit, an AC-alternating current power supply, an L-inductor, a C-capacitor, an RL-resistor, a Q1-a first fast switching tube, a Q2-a second fast switching tube, a Q3-a third fast switching tube, a Q4-a fourth fast switching tube, an S1-a first slow switching tube, an S2-a second slow switching tube, 1-a middle node of a first path, 2-a middle node of a second path and 3-a middle node of a second bridge arm circuit.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
Hereinafter, the terms "including", "having", and their derivatives, which may be used in various embodiments of the present invention, are only intended to indicate specific features, numbers, steps, operations, elements, components, or combinations of the foregoing, and should not be construed as first excluding the existence of, or adding to, one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing.
Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another, and are not to be construed as indicating or implying relative importance.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the present invention belong. The terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning that is consistent with their contextual meaning in the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in various embodiments of the present invention.
Example 1
Referring to fig. 1 and fig. 3, an embodiment of the present invention provides a control method for an interleaved parallel topology, which is applied to the interleaved parallel topology, where the interleaved parallel topology includes a controller 10 and a main circuit 11, where the main circuit 11 includes an inductor L, a first bridge arm circuit and a second bridge arm circuit, the first bridge arm circuit includes a preset number of paths, and intermediate nodes of the paths are connected to each other, where each path includes at least two fast switching tubes connected in series, an intermediate node of each path is used for accessing one end of an AC power supply AC through the inductor, and an intermediate node of the second bridge arm circuit is used for accessing the other end of the AC power supply AC, and the method includes:
and controlling each slow switch tube in the second bridge arm circuit to be alternately conducted according to the state of the output voltage of the alternating current power supply AC, and sequentially controlling each fast switch tube in the passage to be alternately conducted according to a preset switch period during the conduction period of any one slow switch tube.
It should be understood that the first bridge arm circuit includes a plurality of fast switching tubes, and the second bridge arm circuit includes a plurality of slow switching tubes, in this embodiment, the switching tubes are divided into fast switching tubes and slow switching tubes, which are only used to distinguish the switching tubes located in different bridge arm circuits, where the types of the fast switching tubes and the slow switching tubes may be the same or different, and are used according to actual situations, and are not limited herein.
The preset switching period refers to a period for controlling the staggered parallel topology structure in the power supply design process, so that the staggered parallel topology structure can run periodically. Further, after receiving a program instruction, the controller controls that only one fast switching tube of the first bridge arm circuit is turned on and only one slow switching tube of the second bridge arm circuit is turned on at any time of a preset switching period, wherein the slow switching tubes in a turned-on state are different along with the change of the state of the output voltage of the alternating current power supply AC.
Specifically, the frequency of the alternating current power supply AC is usually 50Hz, and the specific use frequency is selected according to the actual situation, which is not limited herein. Further, the switching frequency of the slow switch tube is the same as the frequency of the alternating current power AC, for example, the frequency of the alternating current power AC is 50Hz, and then the switching frequency of the slow switch tube is also 50Hz. And the switching frequency of the fast switching tube is designed according to different actual requirements of a preset switching period. The fast switching tube and the slow switching tube may be power electronic conversion devices such as MOSFET and IGBT, and the specific use type may be determined according to the actual situation, which is not limited herein.
In one embodiment, one end of the inductor L is used for connecting the middle node of each of the paths, the other end of the inductor is used for accessing one end of the AC power source AC, and the other end of the AC power source AC is used for accessing the middle node 3 of the second bridge arm circuit, and the method further includes:
and determining the state of the inductor L according to the conduction states of the fast switching tubes and the slow switching tubes at the current moment, wherein the state of the inductor L comprises a charging state and a discharging state.
Specifically, the main circuit 11 further includes a capacitor C and a resistor RL, and the capacitor C and the resistor RL are connected in parallel, where the resistor RL may be a rated resistor, and the capacitor C and the resistor RL are connected in parallel, so that a direct current signal can be filtered out, and an alternating current signal can easily pass through.
Furthermore, the capacitor C and the resistor RL are both connected in parallel with the second bridge arm circuit, so that the fast switching tube and the slow switching tube which are different at the current moment are in a conducting state, current paths formed by the staggered parallel topology structure are different, and if the current paths pass through the capacitor, the state of the inductor is a charging state; and if the current path does not pass through the capacitor, the state of the inductor is a discharging state.
In one embodiment, the second bridge arm circuit includes a first slow switch tube S1 located in an upper bridge arm and a second slow switch tube S2 located in a lower bridge arm, and the controlling, according to the state of the output voltage of the AC power supply AC, each slow switch tube in the second bridge arm circuit to be alternately turned on includes:
when the state of the output voltage is in a negative half cycle, controlling the first slow switch tube S1 to be conducted, and controlling the second slow switch tube S2 to be switched off;
and when the state of the output voltage is in a positive half cycle, controlling the second slow switch tube S2 to be switched on, and controlling the first slow switch tube S1 to be switched off.
Specifically, the number of the slow switching tubes in the upper bridge arm and the lower bridge arm is generally equal, and may be set to be one or multiple. And controlling one of the upper bridge arm or the lower bridge arm to be conducted according to the state of the output voltage, namely, the upper bridge arm and the lower bridge arm cannot be conducted simultaneously. Further, according to the change of the output voltage in the direction, the state of the output voltage can be generally determined by the waveform of the output voltage, for example, the waveform of the alternating current power supply AC is a sine wave, then, the process that the voltage waveform rises to the peak and then gradually falls to 0 from the time t of 0 is called a positive half cycle; starting at time t from 0, the process of the voltage waveform falling to a trough and then stepping up again to 0 is called a negative half cycle.
In this embodiment, when the state of the output voltage is in a negative half cycle, the upper bridge arm is controlled to turn on the lower bridge arm and turn off, that is, the first slow switch tube S1 turns on the second slow switch tube S2 and turns off; and when the state of the output voltage is in a positive half cycle, controlling the lower bridge arm to conduct the upper bridge arm to be turned off, namely, the second slow switching tube S2 to conduct the first slow switching tube S1 to be turned off. Specifically, whether the upper bridge arm is on or the lower bridge arm is on is determined according to the state of the output voltage, and the design can be performed according to the actual situation, which is not limited herein.
In one embodiment, the dividing the preset switching period into a plurality of sub-periods with the same number as the preset number, and sequentially controlling each fast switching tube in the path to be alternately turned on according to the preset switching period includes:
and sequentially controlling each fast switching tube of only one path to be alternately conducted in any sub-period of the preset switching period.
It should be understood that, according to the difference between the preset number of the paths, the number of the sub-periods divided by the preset switching period is also different, exemplarily, the preset number is n, which means that the paths are n, and then the preset switching period is divided into n sub-periods, specifically, the preset number is 2, which means that the paths are 2, then the preset switching period is divided into two sub-periods, and the specific division is determined according to the actual number of the paths, which is not limited herein.
Specifically, the path may include a plurality of fast switching tubes, and one sub-period correspondingly controls each fast switching tube of one path to be alternately turned on, and further, sequentially controls each fast switching tube of different paths to be alternately turned on in different sub-periods of the preset switching period, so that the controller completes control of the interleaved parallel topology in one preset switching period.
In an embodiment, referring to fig. 2, the first bridge arm circuit includes a first path and a second path, the first path and the second path each include two fast switching transistors, the preset switching period includes a first sub-period T1 and a second sub-period T2, and the sequentially controlling that each fast switching transistor of only one of the paths is alternately turned on in any one of the sub-periods of the preset switching period includes:
step S110: in the first sub-period T1, controlling two fast switching tubes in the first path to be alternately switched on, and controlling two fast switching tubes in the second path to be switched off;
step S120: and in the second sub-period T2, controlling the two fast switching tubes in the second passage to be alternately switched on, and controlling the two fast switching tubes in the first passage to be switched off.
It can be understood that the number and the specifications of the fast switching tubes in each path are the same, and one sub-period is only used for controlling one path to be alternately conducted, and when the path is alternately conducted, other paths are all turned off. Exemplarily, when there are 2 paths in the first bridge arm circuit, the preset switching period is also correspondingly divided into two sub-periods, and then different paths are controlled to be alternately switched on in different sub-periods, and all other paths are switched off.
It should be understood that, in the present embodiment, the controller 10 may control the first path to be alternately turned on and the second path to be turned off in a first sub-period T1, and control the second path to be alternately turned on and the first path to be turned off in a second sub-period T2; the controller 10 may also control the second path to be alternately turned on and the first path to be turned off in the first sub-period T1, and control the first path to be alternately turned on and the second path to be turned off in the second sub-period T2. Which sub-period specifically controls which path is turned on alternately can be set according to actual conditions, and is not limited herein.
In one embodiment, each of the sub-periods is divided into a number of time periods equal to the number of fast switching transistors in the path, the first path includes a first fast switching transistor Q1 and a second fast switching transistor Q2, and the second path includes a third fast switching transistor Q3 and a fourth fast switching transistor Q4.
Further, the step S110 specifically includes:
in a first time period of the first sub-period T1, controlling the first fast switching tube Q1 to be turned on, and the second fast switching tube Q2, the third fast switching tube Q3 and the fourth fast switching tube Q4 to be turned off;
in a second time period of the first sub-period T2, controlling the second fast switching tube Q2 to be turned on, and turning off the first fast switching tube Q1, the third fast switching tube Q3 and the fourth fast switching tube Q4;
the step S120 specifically includes:
in a first time period of the second sub-period T2, controlling the third fast switching tube Q3 to be turned on, and turning off the first fast switching tube Q1, the second fast switching tube Q2 and the fourth fast switching tube Q4;
and in a second time period of the second sub-period T2, controlling the fourth fast switching tube Q4 to be switched on, and switching off the first fast switching tube Q1, the second fast switching tube Q2 and the third fast switching tube Q3.
Specifically, the number of the fast switching tubes included in all the paths is the same, only one fast switching tube is controlled to be turned on in one time period, and the other fast switching tubes are turned off.
Exemplarily, in four time periods of the preset switching cycle, the fast switching tubes are turned on sequentially by the first fast switching tube Q1, the second fast switching tube Q2, the third fast switching tube Q3 and the fourth fast switching tube Q4, that is, only one fast switching tube is turned on in one time period. The specific conducting sequence of the fast switching tube may be determined according to practical situations, and is not limited herein.
Further, referring to fig. 3, the first bridge arm circuit has two paths, where the first path includes a first fast switching tube Q1 and a second fast switching tube Q2, the second path includes a third fast switching tube Q3 and a fourth fast switching tube Q4, the middle node 1 of the first path and the middle node 2 of the second path are connected to each other and are connected to one end of an AC power supply AC through an inductor L, and the middle node 3 of the second bridge arm circuit is connected to the other end of the AC power supply AC. Therefore, the directions in which the current flows in the alternating current power supply AC are different, the components controlling the current to flow are different, and the states of the inductors L are also different.
The present embodiment will be described in detail by taking the case when the state of the input voltage is in the negative half cycle as an example. Referring to fig. 4, in a first time period of the first sub-period T1, only the first fast switching tube Q1 is controlled to be turned on, and when the other fast switching tubes are turned off, the current of the AC power supply AC only flows through the first slow switching tube S1 and the first fast switching tube Q1, and at this time, the inductor L is in a charging state, and the current corresponding to the inductor L is increased; in a second time period of the first sub-period T1, only the second fast switching tube Q2 is controlled to be turned on, the other fast switching tubes are all turned off, the current of the AC power supply AC flows through the first slow switching tube S1, the second fast switching tube Q2 and the capacitor C, at this time, the inductor L is in a discharging state, and the current corresponding to the inductor L is reduced; in a first time period of the second sub-period T2, only the third fast switching tube Q3 is controlled to be turned on, the other fast switching tubes are all turned off, the current of the AC power supply AC only flows through the first slow switching tube S1 and the third fast switching tube Q3, at this time, the inductor L is in a charging state, and the current corresponding to the inductor L is increased; in a second time period of the second sub-period T2, only the fourth fast switching tube Q4 is controlled to be turned on, the other fast switching tubes are all turned off, the current of the AC power supply AC flows through the first slow switching tube S1, the fourth fast switching tube Q4 and the capacitor C, at this time, the inductor L is in a discharge state, and the current corresponding to the inductor L is reduced, so that the waveform of the inductor current in a preset switching period is obtained, and the ripple of the inductor current can be obtained according to the maximum value and the minimum value of the inductor current. The inductor current is a current flowing through the inductor L. In addition, in the present embodiment, in order to distinguish between positive and negative half cycles, the current is analyzed as positive and negative for charge movement, and for example, when the input voltage is negative half cycle, the inductor current is less than 0A.
The same principle is applied when the state of the input voltage is in the positive half cycle, and the state of the inductor is determined according to the different flowing directions of the current of the alternating current power supply AC and the different components through which the current flows, so that the detailed description is omitted here.
Therefore, in this embodiment, under the condition that the switching frequency of the fast switching tube is ensured to be constant, that is, on the basis of ensuring the switching loss, only one inductor can be used, so that the power cost is reduced, and the power density of the power supply is improved.
In one embodiment, the preset switching period is equal to the inverse of the product of the preset number and the switching frequency of the fast switching tube.
The switching frequency of the fast switching tube is controlled by pulse width modulation, specifically, the bias of the base electrode or the grid electrode of the fast switching tube is modulated according to the change of the corresponding load, so that the conduction time of the fast switching tube is changed. The PWM control technology not only enables the control of the fast switching tube to be simple, but also has the advantages of flexibility, good dynamic response and the like.
Exemplarily, the switching frequency of the fast switching tubes is 1/2T, and the preset number is 2, the switching period is T, and then the waveform of the inductor current is obtained according to the periodic variation of the inductor current, and then, the current frequency of the inductor L is 1/T, so that the current frequency of the inductor L is twice the switching frequency. Specifically, the current frequency of the inductor L is related to the preset number, for example, the preset number is n, and then the current frequency of the inductor L is n times the switching frequency. The preset number can be designed according to actual conditions, and is not limited herein.
Therefore, the control method of the interleaved parallel topology structure provided by the embodiment of the invention can realize the effect of the interleaved parallel topology by controlling the plurality of parallel paths on the basis of not increasing the number of the inductors, reduce the hardware cost to a certain extent, and only allow one fast switching tube to be conducted by controlling any time in the preset switching period, thereby realizing the reduction of the ripple of the current during the alternating current input and improving the power density of the power supply.
Example 2
The embodiment of the invention provides a staggered parallel topological structure, which comprises: the bridge-arm control system comprises a controller 10 and a main circuit 11, wherein the main circuit 11 comprises an inductor L, a first bridge-arm circuit and a second bridge-arm circuit, the first bridge-arm circuit comprises a preset number of paths, middle nodes of the paths are connected with each other, each path comprises at least two fast switching tubes connected in series, the middle node of each path is connected with one end of the inductor L, the other end of the inductor L is connected with one end of an alternating current power supply AC, the other end of the alternating current power supply AC is connected with the middle node of the second bridge-arm circuit, and the controller is configured to execute the control method in embodiment 1 to control the first bridge-arm circuit and the second bridge-arm circuit.
Specifically, the interleaved parallel topology structure comprises a capacitor C and a resistor RL, the capacitor C is connected in parallel with the resistor RL, and both the capacitor C and the resistor RL are connected in parallel with the second slow bridge arm circuit. The controller 10 includes, but is not limited to, a DSP controller, a single chip, a microprocessor, and the like. Further, the present embodiment divides the switching tubes into fast switching tubes and slow switching tubes, which are only used to distinguish the switching tubes located in different bridge arm circuits, wherein the types of the switching tubes include, but are not limited to, MOSFETs, IGBTs, GTRs, and the like.
In one embodiment, the interleaved parallel topology includes any one of a bi-directional totem pole PFC topology, a three-phase vienna PFC topology, a three-phase three-level T-topology, and a three-phase three-level I-topology.
Specifically, any one of the bidirectional totem-pole PFC topology, the three-phase vienna PFC topology, the three-phase three-level T-type topology, and the three-phase three-level I-type topology can be controlled by the control method described in embodiment 1, so that the number of inductors can be reduced in the power supply design process, and the hardware cost can be reduced.
The interleaved parallel topology provided in the embodiment of the present application can implement the steps corresponding to the control method in embodiment 1, and the options in embodiment 1 are also applicable to this embodiment, so details are not described here.
The embodiment of the invention also provides an AC/DC power supply, and the power supply comprises the staggered parallel topology structure.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative and, for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, each functional module or unit in each embodiment of the present invention may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The functions may be stored in a computer-readable storage medium if they are implemented in the form of software functional modules and sold or used as separate products. Based on such understanding, the technical solution of the present invention or a part thereof which contributes to the prior art in essence can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a smart phone, a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk, and various media capable of storing program codes.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention.

Claims (10)

1. A control method of a staggered parallel topology is characterized in that the control method is applied to a staggered parallel topology structure, the staggered parallel topology structure comprises a controller and a main circuit, the main circuit comprises an inductor, a first bridge arm circuit and a second bridge arm circuit, the first bridge arm circuit comprises a preset number of paths, and middle nodes of the paths are mutually connected, wherein each path comprises at least two quick switching tubes which are connected in series, the middle node of each path is used for being connected to one end of an alternating current power supply through the inductor, and the middle node of the second bridge arm circuit is used for being connected to the other end of the alternating current power supply, and the method comprises the following steps:
and controlling each slow switching tube in the second bridge arm circuit to be alternately conducted according to the state of the output voltage of the alternating current power supply, and sequentially controlling each fast switching tube in the passage to be alternately conducted according to a preset switching period during the conduction period of any one slow switching tube.
2. The method of claim 1, wherein one end of the inductor is configured to connect to an intermediate node of each of the paths, the other end of the inductor is configured to be connected to one end of the ac power source, and the other end of the ac power source is configured to be connected to an intermediate node of the second bridge arm circuit, the method further comprising:
and determining the state of the inductor according to the conduction state of each fast switching tube and each slow switching tube at the current moment, wherein the state of the inductor comprises a charging state and a discharging state.
3. The method for controlling the interleaved parallel topology according to claim 1, wherein the second bridge arm circuit comprises a first slow switch tube located in an upper bridge arm and a second slow switch tube located in a lower bridge arm, and the controlling of the slow switch tubes in the second bridge arm circuit to be alternately turned on according to the state of the output voltage of the ac power supply comprises:
when the state of the output voltage is in a negative half cycle, controlling the first slow switching tube to be conducted and controlling the second slow switching tube to be switched off;
and when the state of the output voltage is in a positive half cycle, controlling the second slow switching tube to be switched on and controlling the first slow switching tube to be switched off.
4. The method for controlling the interleaved parallel topology according to claim 1, wherein the preset switching period is divided into a plurality of sub-periods having the same number as the preset number, and the sequentially controlling the fast switching transistors in the path to be alternately turned on according to the preset switching period comprises:
and sequentially controlling each fast switching tube of only one path in any sub-period of the preset switching period to be alternately conducted.
5. The method for controlling the interleaved parallel topology according to claim 4, wherein the first bridge arm circuit comprises a first path and a second path, each of the first path and the second path comprises two fast switching transistors, the preset switching period comprises a first sub-period and a second sub-period, and the sequentially controlling each fast switching transistor of only one of the paths in any one of the sub-periods of the preset switching period to be alternately turned on comprises:
in the first sub-period, controlling two fast switching tubes in the first path to be alternately switched on, and controlling two fast switching tubes in the second path to be switched off;
and in the second sub-period, controlling the two fast switching tubes in the second path to be alternately switched on, and controlling the two fast switching tubes in the first path to be switched off.
6. The method of claim 5, wherein each of the sub-cycles is divided into a number of time segments equal to the number of fast switching transistors in the path, the first path comprises a first fast switching transistor and a second fast switching transistor, and the second path comprises a third fast switching transistor and a fourth fast switching transistor; in the first sub-period, controlling two fast switching tubes in the first path to be alternately turned on and two fast switching tubes in the second path to be turned off, including:
in a first time period of the first sub-cycle, controlling the first fast switching tube to be switched on, and switching off the second fast switching tube, the third fast switching tube and the fourth fast switching tube;
in a second time period of the first sub-cycle, controlling the second fast switching tube to be switched on, and switching off the first fast switching tube, the third fast switching tube and the fourth fast switching tube;
in the second sub-period, controlling the two fast switching tubes in the second path to be alternately turned on, and controlling the two fast switching tubes in the first path to be turned off, includes:
controlling the third fast switching tube to be switched on in a first time period of the second sub-period, and switching off the first fast switching tube, the second fast switching tube and the fourth fast switching tube;
and in a second time period of the second sub-period, controlling the fourth fast switching tube to be switched on, and switching off the first fast switching tube, the second fast switching tube and the third fast switching tube.
7. The method of controlling an interleaved parallel topology according to any of claims 1 to 6, wherein the predetermined switching period is equal to an inverse of a product of the predetermined number and a switching frequency of the fast switching tube.
8. An interleaved parallel topology, comprising: the controller is used for executing the control method according to any one of claims 1 to 7 to control the first bridge arm circuit and the second bridge arm circuit.
9. The interleaved parallel topology of claim 8, comprising any of a bi-directional totem pole PFC topology, a three-phase vienna PFC topology, a three-phase three-level T-topology, and a three-phase three-level I-topology.
10. An AC/DC power supply, comprising: the interleaved parallel topology of any of claims 8 to 9.
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Address before: 518000 area 501A, building 15, Yijing company, 1008 Songbai Road, sunshine community, Xili street, Nanshan District, Shenzhen City, Guangdong Province

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